1/* 2 * pata-cs5535.c - CS5535 PATA for new ATA layer 3 * (C) 2005-2006 Red Hat Inc 4 * Alan Cox <alan@lxorguk.ukuu.org.uk> 5 * 6 * based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and 7 * made readable and Linux style by Wolfgang Zuleger <wolfgang.zuleger@gmx.de> 8 * and Alexander Kiausch <alex.kiausch@t-online.de> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 * Loosely based on the piix & svwks drivers. 24 * 25 * Documentation: 26 * Available from AMD web site. 27 * TODO 28 * Review errata to see if serializing is necessary 29 */ 30 31#include <linux/kernel.h> 32#include <linux/module.h> 33#include <linux/pci.h> 34#include <linux/init.h> 35#include <linux/blkdev.h> 36#include <linux/delay.h> 37#include <scsi/scsi_host.h> 38#include <linux/libata.h> 39#include <asm/msr.h> 40 41#define DRV_NAME "cs5535" 42#define DRV_VERSION "0.2.12" 43 44/* 45 * The Geode (Aka Athlon GX now) uses an internal MSR based 46 * bus system for control. Demented but there you go. 47 */ 48 49#define MSR_ATAC_BASE 0x51300000 50#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0) 51#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01) 52#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02) 53#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03) 54#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04) 55#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05) 56#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08) 57#define ATAC_RESET (MSR_ATAC_BASE+0x10) 58#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20) 59#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21) 60#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22) 61#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23) 62#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24) 63 64#define ATAC_BM0_CMD_PRIM 0x00 65#define ATAC_BM0_STS_PRIM 0x02 66#define ATAC_BM0_PRD 0x04 67 68#define CS5535_CABLE_DETECT 0x48 69 70#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL)==0x00009172 ) 71 72/** 73 * cs5535_cable_detect - detect cable type 74 * @ap: Port to detect on 75 * 76 * Perform cable detection for ATA66 capable cable. Return a libata 77 * cable type. 78 */ 79 80static int cs5535_cable_detect(struct ata_port *ap) 81{ 82 u8 cable; 83 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 84 85 pci_read_config_byte(pdev, CS5535_CABLE_DETECT, &cable); 86 if (cable & 1) 87 return ATA_CBL_PATA80; 88 else 89 return ATA_CBL_PATA40; 90} 91 92/** 93 * cs5535_set_piomode - PIO setup 94 * @ap: ATA interface 95 * @adev: device on the interface 96 * 97 * Set our PIO requirements. The CS5535 is pretty clean about all this 98 */ 99 100static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev) 101{ 102 static const u16 pio_timings[5] = { 103 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 104 }; 105 static const u16 pio_cmd_timings[5] = { 106 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 107 }; 108 u32 reg, dummy; 109 struct ata_device *pair = ata_dev_pair(adev); 110 111 int mode = adev->pio_mode - XFER_PIO_0; 112 int cmdmode = mode; 113 114 /* Command timing has to be for the lowest of the pair of devices */ 115 if (pair) { 116 int pairmode = pair->pio_mode - XFER_PIO_0; 117 cmdmode = min(mode, pairmode); 118 /* Write the other drive timing register if it changed */ 119 if (cmdmode < pairmode) 120 wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno, 121 pio_cmd_timings[cmdmode] << 16 | pio_timings[pairmode], 0); 122 } 123 /* Write the drive timing register */ 124 wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno, 125 pio_cmd_timings[cmdmode] << 16 | pio_timings[mode], 0); 126 127 /* Set the PIO "format 1" bit in the DMA timing register */ 128 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy); 129 wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0); 130} 131 132/** 133 * cs5535_set_dmamode - DMA timing setup 134 * @ap: ATA interface 135 * @adev: Device being configured 136 * 137 */ 138 139static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev) 140{ 141 static const u32 udma_timings[5] = { 142 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 143 }; 144 static const u32 mwdma_timings[3] = { 145 0x7F0FFFF3, 0x7F035352, 0x7F024241 146 }; 147 u32 reg, dummy; 148 int mode = adev->dma_mode; 149 150 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy); 151 reg &= 0x80000000UL; 152 if (mode >= XFER_UDMA_0) 153 reg |= udma_timings[mode - XFER_UDMA_0]; 154 else 155 reg |= mwdma_timings[mode - XFER_MW_DMA_0]; 156 wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0); 157} 158 159static struct scsi_host_template cs5535_sht = { 160 ATA_BMDMA_SHT(DRV_NAME), 161}; 162 163static struct ata_port_operations cs5535_port_ops = { 164 .inherits = &ata_bmdma_port_ops, 165 .cable_detect = cs5535_cable_detect, 166 .set_piomode = cs5535_set_piomode, 167 .set_dmamode = cs5535_set_dmamode, 168}; 169 170/** 171 * cs5535_init_one - Initialise a CS5530 172 * @dev: PCI device 173 * @id: Entry in match table 174 * 175 * Install a driver for the newly found CS5530 companion chip. Most of 176 * this is just housekeeping. We have to set the chip up correctly and 177 * turn off various bits of emulation magic. 178 */ 179 180static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id) 181{ 182 static const struct ata_port_info info = { 183 .flags = ATA_FLAG_SLAVE_POSS, 184 .pio_mask = ATA_PIO4, 185 .mwdma_mask = ATA_MWDMA2, 186 .udma_mask = ATA_UDMA4, 187 .port_ops = &cs5535_port_ops 188 }; 189 const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info }; 190 191 u32 timings, dummy; 192 193 /* Check the BIOS set the initial timing clock. If not set the 194 timings for PIO0 */ 195 rdmsr(ATAC_CH0D0_PIO, timings, dummy); 196 if (CS5535_BAD_PIO(timings)) 197 wrmsr(ATAC_CH0D0_PIO, 0xF7F4F7F4UL, 0); 198 rdmsr(ATAC_CH0D1_PIO, timings, dummy); 199 if (CS5535_BAD_PIO(timings)) 200 wrmsr(ATAC_CH0D1_PIO, 0xF7F4F7F4UL, 0); 201 return ata_pci_bmdma_init_one(dev, ppi, &cs5535_sht, NULL, 0); 202} 203 204static const struct pci_device_id cs5535[] = { 205 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), }, 206 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), }, 207 208 { }, 209}; 210 211static struct pci_driver cs5535_pci_driver = { 212 .name = DRV_NAME, 213 .id_table = cs5535, 214 .probe = cs5535_init_one, 215 .remove = ata_pci_remove_one, 216#ifdef CONFIG_PM 217 .suspend = ata_pci_device_suspend, 218 .resume = ata_pci_device_resume, 219#endif 220}; 221 222static int __init cs5535_init(void) 223{ 224 return pci_register_driver(&cs5535_pci_driver); 225} 226 227static void __exit cs5535_exit(void) 228{ 229 pci_unregister_driver(&cs5535_pci_driver); 230} 231 232MODULE_AUTHOR("Alan Cox, Jens Altmann, Wolfgan Zuleger, Alexander Kiausch"); 233MODULE_DESCRIPTION("low-level driver for the NS/AMD 5530"); 234MODULE_LICENSE("GPL"); 235MODULE_DEVICE_TABLE(pci, cs5535); 236MODULE_VERSION(DRV_VERSION); 237 238module_init(cs5535_init); 239module_exit(cs5535_exit); 240