1/* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17#include <linux/perf_event.h> 18#include <linux/kernel_stat.h> 19#include <linux/mc146818rtc.h> 20#include <linux/acpi_pmtmr.h> 21#include <linux/clockchips.h> 22#include <linux/interrupt.h> 23#include <linux/bootmem.h> 24#include <linux/ftrace.h> 25#include <linux/ioport.h> 26#include <linux/module.h> 27#include <linux/sysdev.h> 28#include <linux/delay.h> 29#include <linux/timex.h> 30#include <linux/dmar.h> 31#include <linux/init.h> 32#include <linux/cpu.h> 33#include <linux/dmi.h> 34#include <linux/nmi.h> 35#include <linux/smp.h> 36#include <linux/mm.h> 37 38#include <asm/perf_event.h> 39#include <asm/x86_init.h> 40#include <asm/pgalloc.h> 41#include <asm/atomic.h> 42#include <asm/mpspec.h> 43#include <asm/i8253.h> 44#include <asm/i8259.h> 45#include <asm/proto.h> 46#include <asm/apic.h> 47#include <asm/desc.h> 48#include <asm/hpet.h> 49#include <asm/idle.h> 50#include <asm/mtrr.h> 51#include <asm/smp.h> 52#include <asm/mce.h> 53#include <asm/kvm_para.h> 54#include <asm/tsc.h> 55 56unsigned int num_processors; 57 58unsigned disabled_cpus __cpuinitdata; 59 60/* Processor that is doing the boot up */ 61unsigned int boot_cpu_physical_apicid = -1U; 62 63/* 64 * The highest APIC ID seen during enumeration. 65 */ 66unsigned int max_physical_apicid; 67 68/* 69 * Bitmask of physically existing CPUs: 70 */ 71physid_mask_t phys_cpu_present_map; 72 73/* 74 * Map cpu index to physical APIC ID 75 */ 76DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 77DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 78EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 79EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 80 81#ifdef CONFIG_X86_32 82/* 83 * Knob to control our willingness to enable the local APIC. 84 * 85 * +1=force-enable 86 */ 87static int force_enable_local_apic; 88/* 89 * APIC command line parameters 90 */ 91static int __init parse_lapic(char *arg) 92{ 93 force_enable_local_apic = 1; 94 return 0; 95} 96early_param("lapic", parse_lapic); 97/* Local APIC was disabled by the BIOS and enabled by the kernel */ 98static int enabled_via_apicbase; 99 100/* 101 * Handle interrupt mode configuration register (IMCR). 102 * This register controls whether the interrupt signals 103 * that reach the BSP come from the master PIC or from the 104 * local APIC. Before entering Symmetric I/O Mode, either 105 * the BIOS or the operating system must switch out of 106 * PIC Mode by changing the IMCR. 107 */ 108static inline void imcr_pic_to_apic(void) 109{ 110 /* select IMCR register */ 111 outb(0x70, 0x22); 112 /* NMI and 8259 INTR go through APIC */ 113 outb(0x01, 0x23); 114} 115 116static inline void imcr_apic_to_pic(void) 117{ 118 /* select IMCR register */ 119 outb(0x70, 0x22); 120 /* NMI and 8259 INTR go directly to BSP */ 121 outb(0x00, 0x23); 122} 123#endif 124 125#ifdef CONFIG_X86_64 126static int apic_calibrate_pmtmr __initdata; 127static __init int setup_apicpmtimer(char *s) 128{ 129 apic_calibrate_pmtmr = 1; 130 notsc_setup(NULL); 131 return 0; 132} 133__setup("apicpmtimer", setup_apicpmtimer); 134#endif 135 136int x2apic_mode; 137#ifdef CONFIG_X86_X2APIC 138/* x2apic enabled before OS handover */ 139static int x2apic_preenabled; 140static __init int setup_nox2apic(char *str) 141{ 142 if (x2apic_enabled()) { 143 pr_warning("Bios already enabled x2apic, " 144 "can't enforce nox2apic"); 145 return 0; 146 } 147 148 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 149 return 0; 150} 151early_param("nox2apic", setup_nox2apic); 152#endif 153 154unsigned long mp_lapic_addr; 155int disable_apic; 156/* Disable local APIC timer from the kernel commandline or via dmi quirk */ 157static int disable_apic_timer __cpuinitdata; 158/* Local APIC timer works in C2 */ 159int local_apic_timer_c2_ok; 160EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 161 162int first_system_vector = 0xfe; 163 164/* 165 * Debug level, exported for io_apic.c 166 */ 167unsigned int apic_verbosity; 168 169int pic_mode; 170 171/* Have we found an MP table */ 172int smp_found_config; 173 174static struct resource lapic_resource = { 175 .name = "Local APIC", 176 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 177}; 178 179static unsigned int calibration_result; 180 181static int lapic_next_event(unsigned long delta, 182 struct clock_event_device *evt); 183static void lapic_timer_setup(enum clock_event_mode mode, 184 struct clock_event_device *evt); 185static void lapic_timer_broadcast(const struct cpumask *mask); 186static void apic_pm_activate(void); 187 188/* 189 * The local apic timer can be used for any function which is CPU local. 190 */ 191static struct clock_event_device lapic_clockevent = { 192 .name = "lapic", 193 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 194 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 195 .shift = 32, 196 .set_mode = lapic_timer_setup, 197 .set_next_event = lapic_next_event, 198 .broadcast = lapic_timer_broadcast, 199 .rating = 100, 200 .irq = -1, 201}; 202static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 203 204static unsigned long apic_phys; 205 206/* 207 * Get the LAPIC version 208 */ 209static inline int lapic_get_version(void) 210{ 211 return GET_APIC_VERSION(apic_read(APIC_LVR)); 212} 213 214/* 215 * Check, if the APIC is integrated or a separate chip 216 */ 217static inline int lapic_is_integrated(void) 218{ 219#ifdef CONFIG_X86_64 220 return 1; 221#else 222 return APIC_INTEGRATED(lapic_get_version()); 223#endif 224} 225 226/* 227 * Check, whether this is a modern or a first generation APIC 228 */ 229static int modern_apic(void) 230{ 231 /* AMD systems use old APIC versions, so check the CPU */ 232 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 233 boot_cpu_data.x86 >= 0xf) 234 return 1; 235 return lapic_get_version() >= 0x14; 236} 237 238/* 239 * right after this call apic become NOOP driven 240 * so apic->write/read doesn't do anything 241 */ 242void apic_disable(void) 243{ 244 pr_info("APIC: switched to apic NOOP\n"); 245 apic = &apic_noop; 246} 247 248void native_apic_wait_icr_idle(void) 249{ 250 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 251 cpu_relax(); 252} 253 254u32 native_safe_apic_wait_icr_idle(void) 255{ 256 u32 send_status; 257 int timeout; 258 259 timeout = 0; 260 do { 261 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 262 if (!send_status) 263 break; 264 udelay(100); 265 } while (timeout++ < 1000); 266 267 return send_status; 268} 269 270void native_apic_icr_write(u32 low, u32 id) 271{ 272 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 273 apic_write(APIC_ICR, low); 274} 275 276u64 native_apic_icr_read(void) 277{ 278 u32 icr1, icr2; 279 280 icr2 = apic_read(APIC_ICR2); 281 icr1 = apic_read(APIC_ICR); 282 283 return icr1 | ((u64)icr2 << 32); 284} 285 286/** 287 * enable_NMI_through_LVT0 - enable NMI through local vector table 0 288 */ 289void __cpuinit enable_NMI_through_LVT0(void) 290{ 291 unsigned int v; 292 293 /* unmask and set to NMI */ 294 v = APIC_DM_NMI; 295 296 /* Level triggered for 82489DX (32bit mode) */ 297 if (!lapic_is_integrated()) 298 v |= APIC_LVT_LEVEL_TRIGGER; 299 300 apic_write(APIC_LVT0, v); 301} 302 303#ifdef CONFIG_X86_32 304/** 305 * get_physical_broadcast - Get number of physical broadcast IDs 306 */ 307int get_physical_broadcast(void) 308{ 309 return modern_apic() ? 0xff : 0xf; 310} 311#endif 312 313/** 314 * lapic_get_maxlvt - get the maximum number of local vector table entries 315 */ 316int lapic_get_maxlvt(void) 317{ 318 unsigned int v; 319 320 v = apic_read(APIC_LVR); 321 /* 322 * - we always have APIC integrated on 64bit mode 323 * - 82489DXs do not report # of LVT entries 324 */ 325 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 326} 327 328/* 329 * Local APIC timer 330 */ 331 332/* Clock divisor */ 333#define APIC_DIVISOR 16 334 335/* 336 * This function sets up the local APIC timer, with a timeout of 337 * 'clocks' APIC bus clock. During calibration we actually call 338 * this function twice on the boot CPU, once with a bogus timeout 339 * value, second time for real. The other (noncalibrating) CPUs 340 * call this function only once, with the real, calibrated value. 341 * 342 * We do reads before writes even if unnecessary, to get around the 343 * P5 APIC double write bug. 344 */ 345static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 346{ 347 unsigned int lvtt_value, tmp_value; 348 349 lvtt_value = LOCAL_TIMER_VECTOR; 350 if (!oneshot) 351 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 352 if (!lapic_is_integrated()) 353 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 354 355 if (!irqen) 356 lvtt_value |= APIC_LVT_MASKED; 357 358 apic_write(APIC_LVTT, lvtt_value); 359 360 /* 361 * Divide PICLK by 16 362 */ 363 tmp_value = apic_read(APIC_TDCR); 364 apic_write(APIC_TDCR, 365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 366 APIC_TDR_DIV_16); 367 368 if (!oneshot) 369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 370} 371 372/* 373 * Setup extended LVT, AMD specific (K8, family 10h) 374 * 375 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and 376 * MCE interrupts are supported. Thus MCE offset must be set to 0. 377 * 378 * If mask=1, the LVT entry does not generate interrupts while mask=0 379 * enables the vector. See also the BKDGs. 380 */ 381 382#define APIC_EILVT_LVTOFF_MCE 0 383#define APIC_EILVT_LVTOFF_IBS 1 384 385static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) 386{ 387 unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0); 388 unsigned int v = (mask << 16) | (msg_type << 8) | vector; 389 390 apic_write(reg, v); 391} 392 393u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) 394{ 395 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); 396 return APIC_EILVT_LVTOFF_MCE; 397} 398 399u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) 400{ 401 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); 402 return APIC_EILVT_LVTOFF_IBS; 403} 404EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); 405 406/* 407 * Program the next event, relative to now 408 */ 409static int lapic_next_event(unsigned long delta, 410 struct clock_event_device *evt) 411{ 412 apic_write(APIC_TMICT, delta); 413 return 0; 414} 415 416/* 417 * Setup the lapic timer in periodic or oneshot mode 418 */ 419static void lapic_timer_setup(enum clock_event_mode mode, 420 struct clock_event_device *evt) 421{ 422 unsigned long flags; 423 unsigned int v; 424 425 /* Lapic used as dummy for broadcast ? */ 426 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 427 return; 428 429 local_irq_save(flags); 430 431 switch (mode) { 432 case CLOCK_EVT_MODE_PERIODIC: 433 case CLOCK_EVT_MODE_ONESHOT: 434 __setup_APIC_LVTT(calibration_result, 435 mode != CLOCK_EVT_MODE_PERIODIC, 1); 436 break; 437 case CLOCK_EVT_MODE_UNUSED: 438 case CLOCK_EVT_MODE_SHUTDOWN: 439 v = apic_read(APIC_LVTT); 440 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 441 apic_write(APIC_LVTT, v); 442 apic_write(APIC_TMICT, 0); 443 break; 444 case CLOCK_EVT_MODE_RESUME: 445 /* Nothing to do here */ 446 break; 447 } 448 449 local_irq_restore(flags); 450} 451 452/* 453 * Local APIC timer broadcast function 454 */ 455static void lapic_timer_broadcast(const struct cpumask *mask) 456{ 457#ifdef CONFIG_SMP 458 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 459#endif 460} 461 462/* 463 * Setup the local APIC timer for this CPU. Copy the initialized values 464 * of the boot CPU and register the clock event in the framework. 465 */ 466static void __cpuinit setup_APIC_timer(void) 467{ 468 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 469 470 if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) { 471 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 472 /* Make LAPIC timer preferrable over percpu HPET */ 473 lapic_clockevent.rating = 150; 474 } 475 476 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 477 levt->cpumask = cpumask_of(smp_processor_id()); 478 479 clockevents_register_device(levt); 480} 481 482/* 483 * In this functions we calibrate APIC bus clocks to the external timer. 484 * 485 * We want to do the calibration only once since we want to have local timer 486 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 487 * frequency. 488 * 489 * This was previously done by reading the PIT/HPET and waiting for a wrap 490 * around to find out, that a tick has elapsed. I have a box, where the PIT 491 * readout is broken, so it never gets out of the wait loop again. This was 492 * also reported by others. 493 * 494 * Monitoring the jiffies value is inaccurate and the clockevents 495 * infrastructure allows us to do a simple substitution of the interrupt 496 * handler. 497 * 498 * The calibration routine also uses the pm_timer when possible, as the PIT 499 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 500 * back to normal later in the boot process). 501 */ 502 503#define LAPIC_CAL_LOOPS (HZ/10) 504 505static __initdata int lapic_cal_loops = -1; 506static __initdata long lapic_cal_t1, lapic_cal_t2; 507static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 508static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 509static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 510 511/* 512 * Temporary interrupt handler. 513 */ 514static void __init lapic_cal_handler(struct clock_event_device *dev) 515{ 516 unsigned long long tsc = 0; 517 long tapic = apic_read(APIC_TMCCT); 518 unsigned long pm = acpi_pm_read_early(); 519 520 if (cpu_has_tsc) 521 rdtscll(tsc); 522 523 switch (lapic_cal_loops++) { 524 case 0: 525 lapic_cal_t1 = tapic; 526 lapic_cal_tsc1 = tsc; 527 lapic_cal_pm1 = pm; 528 lapic_cal_j1 = jiffies; 529 break; 530 531 case LAPIC_CAL_LOOPS: 532 lapic_cal_t2 = tapic; 533 lapic_cal_tsc2 = tsc; 534 if (pm < lapic_cal_pm1) 535 pm += ACPI_PM_OVRRUN; 536 lapic_cal_pm2 = pm; 537 lapic_cal_j2 = jiffies; 538 break; 539 } 540} 541 542static int __init 543calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 544{ 545 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 546 const long pm_thresh = pm_100ms / 100; 547 unsigned long mult; 548 u64 res; 549 550#ifndef CONFIG_X86_PM_TIMER 551 return -1; 552#endif 553 554 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 555 556 /* Check, if the PM timer is available */ 557 if (!deltapm) 558 return -1; 559 560 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 561 562 if (deltapm > (pm_100ms - pm_thresh) && 563 deltapm < (pm_100ms + pm_thresh)) { 564 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 565 return 0; 566 } 567 568 res = (((u64)deltapm) * mult) >> 22; 569 do_div(res, 1000000); 570 pr_warning("APIC calibration not consistent " 571 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 572 573 /* Correct the lapic counter value */ 574 res = (((u64)(*delta)) * pm_100ms); 575 do_div(res, deltapm); 576 pr_info("APIC delta adjusted to PM-Timer: " 577 "%lu (%ld)\n", (unsigned long)res, *delta); 578 *delta = (long)res; 579 580 /* Correct the tsc counter value */ 581 if (cpu_has_tsc) { 582 res = (((u64)(*deltatsc)) * pm_100ms); 583 do_div(res, deltapm); 584 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 585 "PM-Timer: %lu (%ld)\n", 586 (unsigned long)res, *deltatsc); 587 *deltatsc = (long)res; 588 } 589 590 return 0; 591} 592 593static int __init calibrate_APIC_clock(void) 594{ 595 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 596 void (*real_handler)(struct clock_event_device *dev); 597 unsigned long deltaj; 598 long delta, deltatsc; 599 int pm_referenced = 0; 600 601 local_irq_disable(); 602 603 /* Replace the global interrupt handler */ 604 real_handler = global_clock_event->event_handler; 605 global_clock_event->event_handler = lapic_cal_handler; 606 607 /* 608 * Setup the APIC counter to maximum. There is no way the lapic 609 * can underflow in the 100ms detection time frame 610 */ 611 __setup_APIC_LVTT(0xffffffff, 0, 0); 612 613 /* Let the interrupts run */ 614 local_irq_enable(); 615 616 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 617 cpu_relax(); 618 619 local_irq_disable(); 620 621 /* Restore the real event handler */ 622 global_clock_event->event_handler = real_handler; 623 624 /* Build delta t1-t2 as apic timer counts down */ 625 delta = lapic_cal_t1 - lapic_cal_t2; 626 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 627 628 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 629 630 /* we trust the PM based calibration if possible */ 631 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 632 &delta, &deltatsc); 633 634 /* Calculate the scaled math multiplication factor */ 635 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 636 lapic_clockevent.shift); 637 lapic_clockevent.max_delta_ns = 638 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 639 lapic_clockevent.min_delta_ns = 640 clockevent_delta2ns(0xF, &lapic_clockevent); 641 642 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 643 644 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 645 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 646 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 647 calibration_result); 648 649 if (cpu_has_tsc) { 650 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 651 "%ld.%04ld MHz.\n", 652 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 653 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 654 } 655 656 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 657 "%u.%04u MHz.\n", 658 calibration_result / (1000000 / HZ), 659 calibration_result % (1000000 / HZ)); 660 661 /* 662 * Do a sanity check on the APIC calibration result 663 */ 664 if (calibration_result < (1000000 / HZ)) { 665 local_irq_enable(); 666 pr_warning("APIC frequency too slow, disabling apic timer\n"); 667 return -1; 668 } 669 670 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 671 672 /* 673 * PM timer calibration failed or not turned on 674 * so lets try APIC timer based calibration 675 */ 676 if (!pm_referenced) { 677 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 678 679 /* 680 * Setup the apic timer manually 681 */ 682 levt->event_handler = lapic_cal_handler; 683 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 684 lapic_cal_loops = -1; 685 686 /* Let the interrupts run */ 687 local_irq_enable(); 688 689 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 690 cpu_relax(); 691 692 /* Stop the lapic timer */ 693 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 694 695 /* Jiffies delta */ 696 deltaj = lapic_cal_j2 - lapic_cal_j1; 697 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 698 699 /* Check, if the jiffies result is consistent */ 700 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 701 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 702 else 703 levt->features |= CLOCK_EVT_FEAT_DUMMY; 704 } else 705 local_irq_enable(); 706 707 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 708 pr_warning("APIC timer disabled due to verification failure\n"); 709 return -1; 710 } 711 712 return 0; 713} 714 715/* 716 * Setup the boot APIC 717 * 718 * Calibrate and verify the result. 719 */ 720void __init setup_boot_APIC_clock(void) 721{ 722 /* 723 * The local apic timer can be disabled via the kernel 724 * commandline or from the CPU detection code. Register the lapic 725 * timer as a dummy clock event source on SMP systems, so the 726 * broadcast mechanism is used. On UP systems simply ignore it. 727 */ 728 if (disable_apic_timer) { 729 pr_info("Disabling APIC timer\n"); 730 /* No broadcast on UP ! */ 731 if (num_possible_cpus() > 1) { 732 lapic_clockevent.mult = 1; 733 setup_APIC_timer(); 734 } 735 return; 736 } 737 738 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 739 "calibrating APIC timer ...\n"); 740 741 if (calibrate_APIC_clock()) { 742 /* No broadcast on UP ! */ 743 if (num_possible_cpus() > 1) 744 setup_APIC_timer(); 745 return; 746 } 747 748 /* 749 * If nmi_watchdog is set to IO_APIC, we need the 750 * PIT/HPET going. Otherwise register lapic as a dummy 751 * device. 752 */ 753 if (nmi_watchdog != NMI_IO_APIC) 754 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 755 else 756 pr_warning("APIC timer registered as dummy," 757 " due to nmi_watchdog=%d!\n", nmi_watchdog); 758 759 /* Setup the lapic or request the broadcast */ 760 setup_APIC_timer(); 761} 762 763void __cpuinit setup_secondary_APIC_clock(void) 764{ 765 setup_APIC_timer(); 766} 767 768/* 769 * The guts of the apic timer interrupt 770 */ 771static void local_apic_timer_interrupt(void) 772{ 773 int cpu = smp_processor_id(); 774 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 775 776 /* 777 * Normally we should not be here till LAPIC has been initialized but 778 * in some cases like kdump, its possible that there is a pending LAPIC 779 * timer interrupt from previous kernel's context and is delivered in 780 * new kernel the moment interrupts are enabled. 781 * 782 * Interrupts are enabled early and LAPIC is setup much later, hence 783 * its possible that when we get here evt->event_handler is NULL. 784 * Check for event_handler being NULL and discard the interrupt as 785 * spurious. 786 */ 787 if (!evt->event_handler) { 788 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 789 /* Switch it off */ 790 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 791 return; 792 } 793 794 /* 795 * the NMI deadlock-detector uses this. 796 */ 797 inc_irq_stat(apic_timer_irqs); 798 799 evt->event_handler(evt); 800} 801 802/* 803 * Local APIC timer interrupt. This is the most natural way for doing 804 * local interrupts, but local timer interrupts can be emulated by 805 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 806 * 807 * [ if a single-CPU system runs an SMP kernel then we call the local 808 * interrupt as well. Thus we cannot inline the local irq ... ] 809 */ 810void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 811{ 812 struct pt_regs *old_regs = set_irq_regs(regs); 813 814 /* 815 * NOTE! We'd better ACK the irq immediately, 816 * because timer handling can be slow. 817 */ 818 ack_APIC_irq(); 819 /* 820 * update_process_times() expects us to have done irq_enter(). 821 * Besides, if we don't timer interrupts ignore the global 822 * interrupt lock, which is the WrongThing (tm) to do. 823 */ 824 exit_idle(); 825 irq_enter(); 826 local_apic_timer_interrupt(); 827 irq_exit(); 828 829 set_irq_regs(old_regs); 830} 831 832int setup_profiling_timer(unsigned int multiplier) 833{ 834 return -EINVAL; 835} 836 837/* 838 * Local APIC start and shutdown 839 */ 840 841/** 842 * clear_local_APIC - shutdown the local APIC 843 * 844 * This is called, when a CPU is disabled and before rebooting, so the state of 845 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 846 * leftovers during boot. 847 */ 848void clear_local_APIC(void) 849{ 850 int maxlvt; 851 u32 v; 852 853 /* APIC hasn't been mapped yet */ 854 if (!x2apic_mode && !apic_phys) 855 return; 856 857 maxlvt = lapic_get_maxlvt(); 858 /* 859 * Masking an LVT entry can trigger a local APIC error 860 * if the vector is zero. Mask LVTERR first to prevent this. 861 */ 862 if (maxlvt >= 3) { 863 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 864 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 865 } 866 /* 867 * Careful: we have to set masks only first to deassert 868 * any level-triggered sources. 869 */ 870 v = apic_read(APIC_LVTT); 871 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 872 v = apic_read(APIC_LVT0); 873 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 874 v = apic_read(APIC_LVT1); 875 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 876 if (maxlvt >= 4) { 877 v = apic_read(APIC_LVTPC); 878 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 879 } 880 881 /* lets not touch this if we didn't frob it */ 882#ifdef CONFIG_X86_THERMAL_VECTOR 883 if (maxlvt >= 5) { 884 v = apic_read(APIC_LVTTHMR); 885 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 886 } 887#endif 888#ifdef CONFIG_X86_MCE_INTEL 889 if (maxlvt >= 6) { 890 v = apic_read(APIC_LVTCMCI); 891 if (!(v & APIC_LVT_MASKED)) 892 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 893 } 894#endif 895 896 /* 897 * Clean APIC state for other OSs: 898 */ 899 apic_write(APIC_LVTT, APIC_LVT_MASKED); 900 apic_write(APIC_LVT0, APIC_LVT_MASKED); 901 apic_write(APIC_LVT1, APIC_LVT_MASKED); 902 if (maxlvt >= 3) 903 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 904 if (maxlvt >= 4) 905 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 906 907 /* Integrated APIC (!82489DX) ? */ 908 if (lapic_is_integrated()) { 909 if (maxlvt > 3) 910 /* Clear ESR due to Pentium errata 3AP and 11AP */ 911 apic_write(APIC_ESR, 0); 912 apic_read(APIC_ESR); 913 } 914} 915 916/** 917 * disable_local_APIC - clear and disable the local APIC 918 */ 919void disable_local_APIC(void) 920{ 921 unsigned int value; 922 923 /* APIC hasn't been mapped yet */ 924 if (!x2apic_mode && !apic_phys) 925 return; 926 927 clear_local_APIC(); 928 929 /* 930 * Disable APIC (implies clearing of registers 931 * for 82489DX!). 932 */ 933 value = apic_read(APIC_SPIV); 934 value &= ~APIC_SPIV_APIC_ENABLED; 935 apic_write(APIC_SPIV, value); 936 937#ifdef CONFIG_X86_32 938 /* 939 * When LAPIC was disabled by the BIOS and enabled by the kernel, 940 * restore the disabled state. 941 */ 942 if (enabled_via_apicbase) { 943 unsigned int l, h; 944 945 rdmsr(MSR_IA32_APICBASE, l, h); 946 l &= ~MSR_IA32_APICBASE_ENABLE; 947 wrmsr(MSR_IA32_APICBASE, l, h); 948 } 949#endif 950} 951 952/* 953 * If Linux enabled the LAPIC against the BIOS default disable it down before 954 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 955 * not power-off. Additionally clear all LVT entries before disable_local_APIC 956 * for the case where Linux didn't enable the LAPIC. 957 */ 958void lapic_shutdown(void) 959{ 960 unsigned long flags; 961 962 if (!cpu_has_apic && !apic_from_smp_config()) 963 return; 964 965 local_irq_save(flags); 966 967#ifdef CONFIG_X86_32 968 if (!enabled_via_apicbase) 969 clear_local_APIC(); 970 else 971#endif 972 disable_local_APIC(); 973 974 975 local_irq_restore(flags); 976} 977 978/* 979 * This is to verify that we're looking at a real local APIC. 980 * Check these against your board if the CPUs aren't getting 981 * started for no apparent reason. 982 */ 983int __init verify_local_APIC(void) 984{ 985 unsigned int reg0, reg1; 986 987 /* 988 * The version register is read-only in a real APIC. 989 */ 990 reg0 = apic_read(APIC_LVR); 991 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 992 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 993 reg1 = apic_read(APIC_LVR); 994 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 995 996 /* 997 * The two version reads above should print the same 998 * numbers. If the second one is different, then we 999 * poke at a non-APIC. 1000 */ 1001 if (reg1 != reg0) 1002 return 0; 1003 1004 /* 1005 * Check if the version looks reasonably. 1006 */ 1007 reg1 = GET_APIC_VERSION(reg0); 1008 if (reg1 == 0x00 || reg1 == 0xff) 1009 return 0; 1010 reg1 = lapic_get_maxlvt(); 1011 if (reg1 < 0x02 || reg1 == 0xff) 1012 return 0; 1013 1014 /* 1015 * The ID register is read/write in a real APIC. 1016 */ 1017 reg0 = apic_read(APIC_ID); 1018 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1019 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1020 reg1 = apic_read(APIC_ID); 1021 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1022 apic_write(APIC_ID, reg0); 1023 if (reg1 != (reg0 ^ apic->apic_id_mask)) 1024 return 0; 1025 1026 /* 1027 * The next two are just to see if we have sane values. 1028 * They're only really relevant if we're in Virtual Wire 1029 * compatibility mode, but most boxes are anymore. 1030 */ 1031 reg0 = apic_read(APIC_LVT0); 1032 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1033 reg1 = apic_read(APIC_LVT1); 1034 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1035 1036 return 1; 1037} 1038 1039/** 1040 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1041 */ 1042void __init sync_Arb_IDs(void) 1043{ 1044 /* 1045 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1046 * needed on AMD. 1047 */ 1048 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1049 return; 1050 1051 /* 1052 * Wait for idle. 1053 */ 1054 apic_wait_icr_idle(); 1055 1056 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1057 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1058 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1059} 1060 1061/* 1062 * An initial setup of the virtual wire mode. 1063 */ 1064void __init init_bsp_APIC(void) 1065{ 1066 unsigned int value; 1067 1068 /* 1069 * Don't do the setup now if we have a SMP BIOS as the 1070 * through-I/O-APIC virtual wire mode might be active. 1071 */ 1072 if (smp_found_config || !cpu_has_apic) 1073 return; 1074 1075 /* 1076 * Do not trust the local APIC being empty at bootup. 1077 */ 1078 clear_local_APIC(); 1079 1080 /* 1081 * Enable APIC. 1082 */ 1083 value = apic_read(APIC_SPIV); 1084 value &= ~APIC_VECTOR_MASK; 1085 value |= APIC_SPIV_APIC_ENABLED; 1086 1087#ifdef CONFIG_X86_32 1088 /* This bit is reserved on P4/Xeon and should be cleared */ 1089 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1090 (boot_cpu_data.x86 == 15)) 1091 value &= ~APIC_SPIV_FOCUS_DISABLED; 1092 else 1093#endif 1094 value |= APIC_SPIV_FOCUS_DISABLED; 1095 value |= SPURIOUS_APIC_VECTOR; 1096 apic_write(APIC_SPIV, value); 1097 1098 /* 1099 * Set up the virtual wire mode. 1100 */ 1101 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1102 value = APIC_DM_NMI; 1103 if (!lapic_is_integrated()) /* 82489DX */ 1104 value |= APIC_LVT_LEVEL_TRIGGER; 1105 apic_write(APIC_LVT1, value); 1106} 1107 1108static void __cpuinit lapic_setup_esr(void) 1109{ 1110 unsigned int oldvalue, value, maxlvt; 1111 1112 if (!lapic_is_integrated()) { 1113 pr_info("No ESR for 82489DX.\n"); 1114 return; 1115 } 1116 1117 if (apic->disable_esr) { 1118 /* 1119 * Something untraceable is creating bad interrupts on 1120 * secondary quads ... for the moment, just leave the 1121 * ESR disabled - we can't do anything useful with the 1122 * errors anyway - mbligh 1123 */ 1124 pr_info("Leaving ESR disabled.\n"); 1125 return; 1126 } 1127 1128 maxlvt = lapic_get_maxlvt(); 1129 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1130 apic_write(APIC_ESR, 0); 1131 oldvalue = apic_read(APIC_ESR); 1132 1133 /* enables sending errors */ 1134 value = ERROR_APIC_VECTOR; 1135 apic_write(APIC_LVTERR, value); 1136 1137 /* 1138 * spec says clear errors after enabling vector. 1139 */ 1140 if (maxlvt > 3) 1141 apic_write(APIC_ESR, 0); 1142 value = apic_read(APIC_ESR); 1143 if (value != oldvalue) 1144 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1145 "vector: 0x%08x after: 0x%08x\n", 1146 oldvalue, value); 1147} 1148 1149 1150/** 1151 * setup_local_APIC - setup the local APIC 1152 */ 1153void __cpuinit setup_local_APIC(void) 1154{ 1155 unsigned int value, queued; 1156 int i, j, acked = 0; 1157 unsigned long long tsc = 0, ntsc; 1158 long long max_loops = cpu_khz; 1159 1160 if (cpu_has_tsc) 1161 rdtscll(tsc); 1162 1163 if (disable_apic) { 1164 arch_disable_smp_support(); 1165 return; 1166 } 1167 1168#ifdef CONFIG_X86_32 1169 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1170 if (lapic_is_integrated() && apic->disable_esr) { 1171 apic_write(APIC_ESR, 0); 1172 apic_write(APIC_ESR, 0); 1173 apic_write(APIC_ESR, 0); 1174 apic_write(APIC_ESR, 0); 1175 } 1176#endif 1177 perf_events_lapic_init(); 1178 1179 preempt_disable(); 1180 1181 /* 1182 * Double-check whether this APIC is really registered. 1183 * This is meaningless in clustered apic mode, so we skip it. 1184 */ 1185 BUG_ON(!apic->apic_id_registered()); 1186 1187 /* 1188 * Intel recommends to set DFR, LDR and TPR before enabling 1189 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1190 * document number 292116). So here it goes... 1191 */ 1192 apic->init_apic_ldr(); 1193 1194 /* 1195 * Set Task Priority to 'accept all'. We never change this 1196 * later on. 1197 */ 1198 value = apic_read(APIC_TASKPRI); 1199 value &= ~APIC_TPRI_MASK; 1200 apic_write(APIC_TASKPRI, value); 1201 1202 /* 1203 * After a crash, we no longer service the interrupts and a pending 1204 * interrupt from previous kernel might still have ISR bit set. 1205 * 1206 * Most probably by now CPU has serviced that pending interrupt and 1207 * it might not have done the ack_APIC_irq() because it thought, 1208 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1209 * does not clear the ISR bit and cpu thinks it has already serivced 1210 * the interrupt. Hence a vector might get locked. It was noticed 1211 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1212 */ 1213 do { 1214 queued = 0; 1215 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1216 queued |= apic_read(APIC_IRR + i*0x10); 1217 1218 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1219 value = apic_read(APIC_ISR + i*0x10); 1220 for (j = 31; j >= 0; j--) { 1221 if (value & (1<<j)) { 1222 ack_APIC_irq(); 1223 acked++; 1224 } 1225 } 1226 } 1227 if (acked > 256) { 1228 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1229 acked); 1230 break; 1231 } 1232 if (cpu_has_tsc) { 1233 rdtscll(ntsc); 1234 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1235 } else 1236 max_loops--; 1237 } while (queued && max_loops > 0); 1238 WARN_ON(max_loops <= 0); 1239 1240 /* 1241 * Now that we are all set up, enable the APIC 1242 */ 1243 value = apic_read(APIC_SPIV); 1244 value &= ~APIC_VECTOR_MASK; 1245 /* 1246 * Enable APIC 1247 */ 1248 value |= APIC_SPIV_APIC_ENABLED; 1249 1250#ifdef CONFIG_X86_32 1251 /* 1252 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1253 * certain networking cards. If high frequency interrupts are 1254 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1255 * entry is masked/unmasked at a high rate as well then sooner or 1256 * later IOAPIC line gets 'stuck', no more interrupts are received 1257 * from the device. If focus CPU is disabled then the hang goes 1258 * away, oh well :-( 1259 * 1260 * [ This bug can be reproduced easily with a level-triggered 1261 * PCI Ne2000 networking cards and PII/PIII processors, dual 1262 * BX chipset. ] 1263 */ 1264 /* 1265 * Actually disabling the focus CPU check just makes the hang less 1266 * frequent as it makes the interrupt distributon model be more 1267 * like LRU than MRU (the short-term load is more even across CPUs). 1268 * See also the comment in end_level_ioapic_irq(). --macro 1269 */ 1270 1271 /* 1272 * - enable focus processor (bit==0) 1273 * - 64bit mode always use processor focus 1274 * so no need to set it 1275 */ 1276 value &= ~APIC_SPIV_FOCUS_DISABLED; 1277#endif 1278 1279 /* 1280 * Set spurious IRQ vector 1281 */ 1282 value |= SPURIOUS_APIC_VECTOR; 1283 apic_write(APIC_SPIV, value); 1284 1285 /* 1286 * Set up LVT0, LVT1: 1287 * 1288 * set up through-local-APIC on the BP's LINT0. This is not 1289 * strictly necessary in pure symmetric-IO mode, but sometimes 1290 * we delegate interrupts to the 8259A. 1291 */ 1292 /* 1293 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1294 */ 1295 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1296 if (!smp_processor_id() && (pic_mode || !value)) { 1297 value = APIC_DM_EXTINT; 1298 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", 1299 smp_processor_id()); 1300 } else { 1301 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1302 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", 1303 smp_processor_id()); 1304 } 1305 apic_write(APIC_LVT0, value); 1306 1307 /* 1308 * only the BP should see the LINT1 NMI signal, obviously. 1309 */ 1310 if (!smp_processor_id()) 1311 value = APIC_DM_NMI; 1312 else 1313 value = APIC_DM_NMI | APIC_LVT_MASKED; 1314 if (!lapic_is_integrated()) /* 82489DX */ 1315 value |= APIC_LVT_LEVEL_TRIGGER; 1316 apic_write(APIC_LVT1, value); 1317 1318 preempt_enable(); 1319 1320#ifdef CONFIG_X86_MCE_INTEL 1321 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1322 if (smp_processor_id() == 0) 1323 cmci_recheck(); 1324#endif 1325} 1326 1327void __cpuinit end_local_APIC_setup(void) 1328{ 1329 lapic_setup_esr(); 1330 1331#ifdef CONFIG_X86_32 1332 { 1333 unsigned int value; 1334 /* Disable the local apic timer */ 1335 value = apic_read(APIC_LVTT); 1336 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1337 apic_write(APIC_LVTT, value); 1338 } 1339#endif 1340 1341 setup_apic_nmi_watchdog(NULL); 1342 apic_pm_activate(); 1343 1344 /* 1345 * Now that local APIC setup is completed for BP, configure the fault 1346 * handling for interrupt remapping. 1347 */ 1348 if (!smp_processor_id() && intr_remapping_enabled) 1349 enable_drhd_fault_handling(); 1350 1351} 1352 1353#ifdef CONFIG_X86_X2APIC 1354void check_x2apic(void) 1355{ 1356 if (x2apic_enabled()) { 1357 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1358 x2apic_preenabled = x2apic_mode = 1; 1359 } 1360} 1361 1362void enable_x2apic(void) 1363{ 1364 int msr, msr2; 1365 1366 if (!x2apic_mode) 1367 return; 1368 1369 rdmsr(MSR_IA32_APICBASE, msr, msr2); 1370 if (!(msr & X2APIC_ENABLE)) { 1371 printk_once(KERN_INFO "Enabling x2apic\n"); 1372 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1373 } 1374} 1375#endif /* CONFIG_X86_X2APIC */ 1376 1377int __init enable_IR(void) 1378{ 1379#ifdef CONFIG_INTR_REMAP 1380 if (!intr_remapping_supported()) { 1381 pr_debug("intr-remapping not supported\n"); 1382 return 0; 1383 } 1384 1385 if (!x2apic_preenabled && skip_ioapic_setup) { 1386 pr_info("Skipped enabling intr-remap because of skipping " 1387 "io-apic setup\n"); 1388 return 0; 1389 } 1390 1391 if (enable_intr_remapping(x2apic_supported())) 1392 return 0; 1393 1394 pr_info("Enabled Interrupt-remapping\n"); 1395 1396 return 1; 1397 1398#endif 1399 return 0; 1400} 1401 1402void __init enable_IR_x2apic(void) 1403{ 1404 unsigned long flags; 1405 struct IO_APIC_route_entry **ioapic_entries = NULL; 1406 int ret, x2apic_enabled = 0; 1407 int dmar_table_init_ret; 1408 1409 dmar_table_init_ret = dmar_table_init(); 1410 if (dmar_table_init_ret && !x2apic_supported()) 1411 return; 1412 1413 ioapic_entries = alloc_ioapic_entries(); 1414 if (!ioapic_entries) { 1415 pr_err("Allocate ioapic_entries failed\n"); 1416 goto out; 1417 } 1418 1419 ret = save_IO_APIC_setup(ioapic_entries); 1420 if (ret) { 1421 pr_info("Saving IO-APIC state failed: %d\n", ret); 1422 goto out; 1423 } 1424 1425 local_irq_save(flags); 1426 legacy_pic->mask_all(); 1427 mask_IO_APIC_setup(ioapic_entries); 1428 1429 if (dmar_table_init_ret) 1430 ret = 0; 1431 else 1432 ret = enable_IR(); 1433 1434 if (!ret) { 1435 /* IR is required if there is APIC ID > 255 even when running 1436 * under KVM 1437 */ 1438 if (max_physical_apicid > 255 || !kvm_para_available()) 1439 goto nox2apic; 1440 /* 1441 * without IR all CPUs can be addressed by IOAPIC/MSI 1442 * only in physical mode 1443 */ 1444 x2apic_force_phys(); 1445 } 1446 1447 x2apic_enabled = 1; 1448 1449 if (x2apic_supported() && !x2apic_mode) { 1450 x2apic_mode = 1; 1451 enable_x2apic(); 1452 pr_info("Enabled x2apic\n"); 1453 } 1454 1455nox2apic: 1456 if (!ret) /* IR enabling failed */ 1457 restore_IO_APIC_setup(ioapic_entries); 1458 legacy_pic->restore_mask(); 1459 local_irq_restore(flags); 1460 1461out: 1462 if (ioapic_entries) 1463 free_ioapic_entries(ioapic_entries); 1464 1465 if (x2apic_enabled) 1466 return; 1467 1468 if (x2apic_preenabled) 1469 panic("x2apic: enabled by BIOS but kernel init failed."); 1470 else if (cpu_has_x2apic) 1471 pr_info("Not enabling x2apic, Intr-remapping init failed.\n"); 1472} 1473 1474#ifdef CONFIG_X86_64 1475/* 1476 * Detect and enable local APICs on non-SMP boards. 1477 * Original code written by Keir Fraser. 1478 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1479 * not correctly set up (usually the APIC timer won't work etc.) 1480 */ 1481static int __init detect_init_APIC(void) 1482{ 1483 if (!cpu_has_apic) { 1484 pr_info("No local APIC present\n"); 1485 return -1; 1486 } 1487 1488 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1489 return 0; 1490} 1491#else 1492/* 1493 * Detect and initialize APIC 1494 */ 1495static int __init detect_init_APIC(void) 1496{ 1497 u32 h, l, features; 1498 1499 /* Disabled by kernel option? */ 1500 if (disable_apic) 1501 return -1; 1502 1503 switch (boot_cpu_data.x86_vendor) { 1504 case X86_VENDOR_AMD: 1505 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1506 (boot_cpu_data.x86 >= 15)) 1507 break; 1508 goto no_apic; 1509 case X86_VENDOR_INTEL: 1510 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1511 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1512 break; 1513 goto no_apic; 1514 default: 1515 goto no_apic; 1516 } 1517 1518 if (!cpu_has_apic) { 1519 /* 1520 * Over-ride BIOS and try to enable the local APIC only if 1521 * "lapic" specified. 1522 */ 1523 if (!force_enable_local_apic) { 1524 pr_info("Local APIC disabled by BIOS -- " 1525 "you can enable it with \"lapic\"\n"); 1526 return -1; 1527 } 1528 /* 1529 * Some BIOSes disable the local APIC in the APIC_BASE 1530 * MSR. This can only be done in software for Intel P6 or later 1531 * and AMD K7 (Model > 1) or later. 1532 */ 1533 rdmsr(MSR_IA32_APICBASE, l, h); 1534 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1535 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1536 l &= ~MSR_IA32_APICBASE_BASE; 1537 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 1538 wrmsr(MSR_IA32_APICBASE, l, h); 1539 enabled_via_apicbase = 1; 1540 } 1541 } 1542 /* 1543 * The APIC feature bit should now be enabled 1544 * in `cpuid' 1545 */ 1546 features = cpuid_edx(1); 1547 if (!(features & (1 << X86_FEATURE_APIC))) { 1548 pr_warning("Could not enable APIC!\n"); 1549 return -1; 1550 } 1551 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1552 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1553 1554 /* The BIOS may have set up the APIC at some other address */ 1555 rdmsr(MSR_IA32_APICBASE, l, h); 1556 if (l & MSR_IA32_APICBASE_ENABLE) 1557 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1558 1559 pr_info("Found and enabled local APIC!\n"); 1560 1561 apic_pm_activate(); 1562 1563 return 0; 1564 1565no_apic: 1566 pr_info("No local APIC present or hardware disabled\n"); 1567 return -1; 1568} 1569#endif 1570 1571#ifdef CONFIG_X86_64 1572void __init early_init_lapic_mapping(void) 1573{ 1574 /* 1575 * If no local APIC can be found then go out 1576 * : it means there is no mpatable and MADT 1577 */ 1578 if (!smp_found_config) 1579 return; 1580 1581 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); 1582 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1583 APIC_BASE, mp_lapic_addr); 1584 1585 /* 1586 * Fetch the APIC ID of the BSP in case we have a 1587 * default configuration (or the MP table is broken). 1588 */ 1589 boot_cpu_physical_apicid = read_apic_id(); 1590} 1591#endif 1592 1593/** 1594 * init_apic_mappings - initialize APIC mappings 1595 */ 1596void __init init_apic_mappings(void) 1597{ 1598 unsigned int new_apicid; 1599 1600 if (x2apic_mode) { 1601 boot_cpu_physical_apicid = read_apic_id(); 1602 return; 1603 } 1604 1605 /* If no local APIC can be found return early */ 1606 if (!smp_found_config && detect_init_APIC()) { 1607 /* lets NOP'ify apic operations */ 1608 pr_info("APIC: disable apic facility\n"); 1609 apic_disable(); 1610 } else { 1611 apic_phys = mp_lapic_addr; 1612 1613 /* 1614 * acpi lapic path already maps that address in 1615 * acpi_register_lapic_address() 1616 */ 1617 if (!acpi_lapic && !smp_found_config) 1618 set_fixmap_nocache(FIX_APIC_BASE, apic_phys); 1619 1620 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", 1621 APIC_BASE, apic_phys); 1622 } 1623 1624 /* 1625 * Fetch the APIC ID of the BSP in case we have a 1626 * default configuration (or the MP table is broken). 1627 */ 1628 new_apicid = read_apic_id(); 1629 if (boot_cpu_physical_apicid != new_apicid) { 1630 boot_cpu_physical_apicid = new_apicid; 1631 /* 1632 * yeah -- we lie about apic_version 1633 * in case if apic was disabled via boot option 1634 * but it's not a problem for SMP compiled kernel 1635 * since smp_sanity_check is prepared for such a case 1636 * and disable smp mode 1637 */ 1638 apic_version[new_apicid] = 1639 GET_APIC_VERSION(apic_read(APIC_LVR)); 1640 } 1641} 1642 1643/* 1644 * This initializes the IO-APIC and APIC hardware if this is 1645 * a UP kernel. 1646 */ 1647int apic_version[MAX_APICS]; 1648 1649int __init APIC_init_uniprocessor(void) 1650{ 1651 if (disable_apic) { 1652 pr_info("Apic disabled\n"); 1653 return -1; 1654 } 1655#ifdef CONFIG_X86_64 1656 if (!cpu_has_apic) { 1657 disable_apic = 1; 1658 pr_info("Apic disabled by BIOS\n"); 1659 return -1; 1660 } 1661#else 1662 if (!smp_found_config && !cpu_has_apic) 1663 return -1; 1664 1665 /* 1666 * Complain if the BIOS pretends there is one. 1667 */ 1668 if (!cpu_has_apic && 1669 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1670 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1671 boot_cpu_physical_apicid); 1672 return -1; 1673 } 1674#endif 1675 1676#ifndef CONFIG_SMP 1677 enable_IR_x2apic(); 1678 default_setup_apic_routing(); 1679#endif 1680 1681 verify_local_APIC(); 1682 connect_bsp_APIC(); 1683 1684#ifdef CONFIG_X86_64 1685 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1686#else 1687 /* 1688 * Hack: In case of kdump, after a crash, kernel might be booting 1689 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1690 * might be zero if read from MP tables. Get it from LAPIC. 1691 */ 1692# ifdef CONFIG_CRASH_DUMP 1693 boot_cpu_physical_apicid = read_apic_id(); 1694# endif 1695#endif 1696 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1697 setup_local_APIC(); 1698 1699#ifdef CONFIG_X86_IO_APIC 1700 /* 1701 * Now enable IO-APICs, actually call clear_IO_APIC 1702 * We need clear_IO_APIC before enabling error vector 1703 */ 1704 if (!skip_ioapic_setup && nr_ioapics) 1705 enable_IO_APIC(); 1706#endif 1707 1708 end_local_APIC_setup(); 1709 1710#ifdef CONFIG_X86_IO_APIC 1711 if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1712 setup_IO_APIC(); 1713 else { 1714 nr_ioapics = 0; 1715 localise_nmi_watchdog(); 1716 } 1717#else 1718 localise_nmi_watchdog(); 1719#endif 1720 1721 x86_init.timers.setup_percpu_clockev(); 1722#ifdef CONFIG_X86_64 1723 check_nmi_watchdog(); 1724#endif 1725 1726 return 0; 1727} 1728 1729/* 1730 * Local APIC interrupts 1731 */ 1732 1733/* 1734 * This interrupt should _never_ happen with our APIC/SMP architecture 1735 */ 1736void smp_spurious_interrupt(struct pt_regs *regs) 1737{ 1738 u32 v; 1739 1740 exit_idle(); 1741 irq_enter(); 1742 /* 1743 * Check if this really is a spurious interrupt and ACK it 1744 * if it is a vectored one. Just in case... 1745 * Spurious interrupts should not be ACKed. 1746 */ 1747 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1748 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1749 ack_APIC_irq(); 1750 1751 inc_irq_stat(irq_spurious_count); 1752 1753 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1754 pr_info("spurious APIC interrupt on CPU#%d, " 1755 "should never happen.\n", smp_processor_id()); 1756 irq_exit(); 1757} 1758 1759/* 1760 * This interrupt should never happen with our APIC/SMP architecture 1761 */ 1762void smp_error_interrupt(struct pt_regs *regs) 1763{ 1764 u32 v, v1; 1765 1766 exit_idle(); 1767 irq_enter(); 1768 /* First tickle the hardware, only then report what went on. -- REW */ 1769 v = apic_read(APIC_ESR); 1770 apic_write(APIC_ESR, 0); 1771 v1 = apic_read(APIC_ESR); 1772 ack_APIC_irq(); 1773 atomic_inc(&irq_err_count); 1774 1775 /* 1776 * Here is what the APIC error bits mean: 1777 * 0: Send CS error 1778 * 1: Receive CS error 1779 * 2: Send accept error 1780 * 3: Receive accept error 1781 * 4: Reserved 1782 * 5: Send illegal vector 1783 * 6: Received illegal vector 1784 * 7: Illegal register address 1785 */ 1786 pr_debug("APIC error on CPU%d: %02x(%02x)\n", 1787 smp_processor_id(), v , v1); 1788 irq_exit(); 1789} 1790 1791/** 1792 * connect_bsp_APIC - attach the APIC to the interrupt system 1793 */ 1794void __init connect_bsp_APIC(void) 1795{ 1796#ifdef CONFIG_X86_32 1797 if (pic_mode) { 1798 /* 1799 * Do not trust the local APIC being empty at bootup. 1800 */ 1801 clear_local_APIC(); 1802 /* 1803 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1804 * local APIC to INT and NMI lines. 1805 */ 1806 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1807 "enabling APIC mode.\n"); 1808 imcr_pic_to_apic(); 1809 } 1810#endif 1811 if (apic->enable_apic_mode) 1812 apic->enable_apic_mode(); 1813} 1814 1815/** 1816 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1817 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1818 * 1819 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1820 * APIC is disabled. 1821 */ 1822void disconnect_bsp_APIC(int virt_wire_setup) 1823{ 1824 unsigned int value; 1825 1826#ifdef CONFIG_X86_32 1827 if (pic_mode) { 1828 /* 1829 * Put the board back into PIC mode (has an effect only on 1830 * certain older boards). Note that APIC interrupts, including 1831 * IPIs, won't work beyond this point! The only exception are 1832 * INIT IPIs. 1833 */ 1834 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1835 "entering PIC mode.\n"); 1836 imcr_apic_to_pic(); 1837 return; 1838 } 1839#endif 1840 1841 /* Go back to Virtual Wire compatibility mode */ 1842 1843 /* For the spurious interrupt use vector F, and enable it */ 1844 value = apic_read(APIC_SPIV); 1845 value &= ~APIC_VECTOR_MASK; 1846 value |= APIC_SPIV_APIC_ENABLED; 1847 value |= 0xf; 1848 apic_write(APIC_SPIV, value); 1849 1850 if (!virt_wire_setup) { 1851 /* 1852 * For LVT0 make it edge triggered, active high, 1853 * external and enabled 1854 */ 1855 value = apic_read(APIC_LVT0); 1856 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1857 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1858 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1859 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1860 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1861 apic_write(APIC_LVT0, value); 1862 } else { 1863 /* Disable LVT0 */ 1864 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1865 } 1866 1867 /* 1868 * For LVT1 make it edge triggered, active high, 1869 * nmi and enabled 1870 */ 1871 value = apic_read(APIC_LVT1); 1872 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1873 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1874 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1875 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1876 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1877 apic_write(APIC_LVT1, value); 1878} 1879 1880void __cpuinit generic_processor_info(int apicid, int version) 1881{ 1882 int cpu; 1883 1884 /* 1885 * Validate version 1886 */ 1887 if (version == 0x0) { 1888 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " 1889 "fixing up to 0x10. (tell your hw vendor)\n", 1890 version); 1891 version = 0x10; 1892 } 1893 apic_version[apicid] = version; 1894 1895 if (num_processors >= nr_cpu_ids) { 1896 int max = nr_cpu_ids; 1897 int thiscpu = max + disabled_cpus; 1898 1899 pr_warning( 1900 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1901 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1902 1903 disabled_cpus++; 1904 return; 1905 } 1906 1907 num_processors++; 1908 cpu = cpumask_next_zero(-1, cpu_present_mask); 1909 1910 if (version != apic_version[boot_cpu_physical_apicid]) 1911 WARN_ONCE(1, 1912 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", 1913 apic_version[boot_cpu_physical_apicid], cpu, version); 1914 1915 physid_set(apicid, phys_cpu_present_map); 1916 if (apicid == boot_cpu_physical_apicid) { 1917 /* 1918 * x86_bios_cpu_apicid is required to have processors listed 1919 * in same order as logical cpu numbers. Hence the first 1920 * entry is BSP, and so on. 1921 */ 1922 cpu = 0; 1923 } 1924 if (apicid > max_physical_apicid) 1925 max_physical_apicid = apicid; 1926 1927#if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1928 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1929 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1930#endif 1931 1932 set_cpu_possible(cpu, true); 1933 set_cpu_present(cpu, true); 1934} 1935 1936int hard_smp_processor_id(void) 1937{ 1938 return read_apic_id(); 1939} 1940 1941void default_init_apic_ldr(void) 1942{ 1943 unsigned long val; 1944 1945 apic_write(APIC_DFR, APIC_DFR_VALUE); 1946 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 1947 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 1948 apic_write(APIC_LDR, val); 1949} 1950 1951#ifdef CONFIG_X86_32 1952int default_apicid_to_node(int logical_apicid) 1953{ 1954#ifdef CONFIG_SMP 1955 return apicid_2_node[hard_smp_processor_id()]; 1956#else 1957 return 0; 1958#endif 1959} 1960#endif 1961 1962/* 1963 * Power management 1964 */ 1965#ifdef CONFIG_PM 1966 1967static struct { 1968 /* 1969 * 'active' is true if the local APIC was enabled by us and 1970 * not the BIOS; this signifies that we are also responsible 1971 * for disabling it before entering apm/acpi suspend 1972 */ 1973 int active; 1974 /* r/w apic fields */ 1975 unsigned int apic_id; 1976 unsigned int apic_taskpri; 1977 unsigned int apic_ldr; 1978 unsigned int apic_dfr; 1979 unsigned int apic_spiv; 1980 unsigned int apic_lvtt; 1981 unsigned int apic_lvtpc; 1982 unsigned int apic_lvt0; 1983 unsigned int apic_lvt1; 1984 unsigned int apic_lvterr; 1985 unsigned int apic_tmict; 1986 unsigned int apic_tdcr; 1987 unsigned int apic_thmr; 1988} apic_pm_state; 1989 1990static int lapic_suspend(struct sys_device *dev, pm_message_t state) 1991{ 1992 unsigned long flags; 1993 int maxlvt; 1994 1995 if (!apic_pm_state.active) 1996 return 0; 1997 1998 maxlvt = lapic_get_maxlvt(); 1999 2000 apic_pm_state.apic_id = apic_read(APIC_ID); 2001 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2002 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2003 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2004 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2005 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2006 if (maxlvt >= 4) 2007 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2008 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2009 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2010 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2011 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2012 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2013#ifdef CONFIG_X86_THERMAL_VECTOR 2014 if (maxlvt >= 5) 2015 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2016#endif 2017 2018 local_irq_save(flags); 2019 disable_local_APIC(); 2020 2021 if (intr_remapping_enabled) 2022 disable_intr_remapping(); 2023 2024 local_irq_restore(flags); 2025 return 0; 2026} 2027 2028static int lapic_resume(struct sys_device *dev) 2029{ 2030 unsigned int l, h; 2031 unsigned long flags; 2032 int maxlvt; 2033 int ret = 0; 2034 struct IO_APIC_route_entry **ioapic_entries = NULL; 2035 2036 if (!apic_pm_state.active) 2037 return 0; 2038 2039 local_irq_save(flags); 2040 if (intr_remapping_enabled) { 2041 ioapic_entries = alloc_ioapic_entries(); 2042 if (!ioapic_entries) { 2043 WARN(1, "Alloc ioapic_entries in lapic resume failed."); 2044 ret = -ENOMEM; 2045 goto restore; 2046 } 2047 2048 ret = save_IO_APIC_setup(ioapic_entries); 2049 if (ret) { 2050 WARN(1, "Saving IO-APIC state failed: %d\n", ret); 2051 free_ioapic_entries(ioapic_entries); 2052 goto restore; 2053 } 2054 2055 mask_IO_APIC_setup(ioapic_entries); 2056 legacy_pic->mask_all(); 2057 } 2058 2059 if (x2apic_mode) 2060 enable_x2apic(); 2061 else { 2062 rdmsr(MSR_IA32_APICBASE, l, h); 2063 l &= ~MSR_IA32_APICBASE_BASE; 2064 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2065 wrmsr(MSR_IA32_APICBASE, l, h); 2066 } 2067 2068 maxlvt = lapic_get_maxlvt(); 2069 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2070 apic_write(APIC_ID, apic_pm_state.apic_id); 2071 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2072 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2073 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2074 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2075 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2076 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2077#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2078 if (maxlvt >= 5) 2079 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2080#endif 2081 if (maxlvt >= 4) 2082 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2083 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2084 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2085 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2086 apic_write(APIC_ESR, 0); 2087 apic_read(APIC_ESR); 2088 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2089 apic_write(APIC_ESR, 0); 2090 apic_read(APIC_ESR); 2091 2092 if (intr_remapping_enabled) { 2093 reenable_intr_remapping(x2apic_mode); 2094 legacy_pic->restore_mask(); 2095 restore_IO_APIC_setup(ioapic_entries); 2096 free_ioapic_entries(ioapic_entries); 2097 } 2098restore: 2099 local_irq_restore(flags); 2100 2101 return ret; 2102} 2103 2104/* 2105 * This device has no shutdown method - fully functioning local APICs 2106 * are needed on every CPU up until machine_halt/restart/poweroff. 2107 */ 2108 2109static struct sysdev_class lapic_sysclass = { 2110 .name = "lapic", 2111 .resume = lapic_resume, 2112 .suspend = lapic_suspend, 2113}; 2114 2115static struct sys_device device_lapic = { 2116 .id = 0, 2117 .cls = &lapic_sysclass, 2118}; 2119 2120static void __cpuinit apic_pm_activate(void) 2121{ 2122 apic_pm_state.active = 1; 2123} 2124 2125static int __init init_lapic_sysfs(void) 2126{ 2127 int error; 2128 2129 if (!cpu_has_apic) 2130 return 0; 2131 2132 error = sysdev_class_register(&lapic_sysclass); 2133 if (!error) 2134 error = sysdev_register(&device_lapic); 2135 return error; 2136} 2137 2138/* local apic needs to resume before other devices access its registers. */ 2139core_initcall(init_lapic_sysfs); 2140 2141#else /* CONFIG_PM */ 2142 2143static void apic_pm_activate(void) { } 2144 2145#endif /* CONFIG_PM */ 2146 2147#ifdef CONFIG_X86_64 2148 2149static int __cpuinit apic_cluster_num(void) 2150{ 2151 int i, clusters, zeros; 2152 unsigned id; 2153 u16 *bios_cpu_apicid; 2154 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2155 2156 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2157 bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2158 2159 for (i = 0; i < nr_cpu_ids; i++) { 2160 /* are we being called early in kernel startup? */ 2161 if (bios_cpu_apicid) { 2162 id = bios_cpu_apicid[i]; 2163 } else if (i < nr_cpu_ids) { 2164 if (cpu_present(i)) 2165 id = per_cpu(x86_bios_cpu_apicid, i); 2166 else 2167 continue; 2168 } else 2169 break; 2170 2171 if (id != BAD_APICID) 2172 __set_bit(APIC_CLUSTERID(id), clustermap); 2173 } 2174 2175 /* Problem: Partially populated chassis may not have CPUs in some of 2176 * the APIC clusters they have been allocated. Only present CPUs have 2177 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2178 * Since clusters are allocated sequentially, count zeros only if 2179 * they are bounded by ones. 2180 */ 2181 clusters = 0; 2182 zeros = 0; 2183 for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2184 if (test_bit(i, clustermap)) { 2185 clusters += 1 + zeros; 2186 zeros = 0; 2187 } else 2188 ++zeros; 2189 } 2190 2191 return clusters; 2192} 2193 2194static int __cpuinitdata multi_checked; 2195static int __cpuinitdata multi; 2196 2197static int __cpuinit set_multi(const struct dmi_system_id *d) 2198{ 2199 if (multi) 2200 return 0; 2201 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2202 multi = 1; 2203 return 0; 2204} 2205 2206static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2207 { 2208 .callback = set_multi, 2209 .ident = "IBM System Summit2", 2210 .matches = { 2211 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2212 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2213 }, 2214 }, 2215 {} 2216}; 2217 2218static void __cpuinit dmi_check_multi(void) 2219{ 2220 if (multi_checked) 2221 return; 2222 2223 dmi_check_system(multi_dmi_table); 2224 multi_checked = 1; 2225} 2226 2227/* 2228 * apic_is_clustered_box() -- Check if we can expect good TSC 2229 * 2230 * Thus far, the major user of this is IBM's Summit2 series: 2231 * Clustered boxes may have unsynced TSC problems if they are 2232 * multi-chassis. 2233 * Use DMI to check them 2234 */ 2235__cpuinit int apic_is_clustered_box(void) 2236{ 2237 dmi_check_multi(); 2238 if (multi) 2239 return 1; 2240 2241 if (!is_vsmp_box()) 2242 return 0; 2243 2244 /* 2245 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2246 * not guaranteed to be synced between boards 2247 */ 2248 if (apic_cluster_num() > 1) 2249 return 1; 2250 2251 return 0; 2252} 2253#endif 2254 2255/* 2256 * APIC command line parameters 2257 */ 2258static int __init setup_disableapic(char *arg) 2259{ 2260 disable_apic = 1; 2261 setup_clear_cpu_cap(X86_FEATURE_APIC); 2262 return 0; 2263} 2264early_param("disableapic", setup_disableapic); 2265 2266/* same as disableapic, for compatibility */ 2267static int __init setup_nolapic(char *arg) 2268{ 2269 return setup_disableapic(arg); 2270} 2271early_param("nolapic", setup_nolapic); 2272 2273static int __init parse_lapic_timer_c2_ok(char *arg) 2274{ 2275 local_apic_timer_c2_ok = 1; 2276 return 0; 2277} 2278early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2279 2280static int __init parse_disable_apic_timer(char *arg) 2281{ 2282 disable_apic_timer = 1; 2283 return 0; 2284} 2285early_param("noapictimer", parse_disable_apic_timer); 2286 2287static int __init parse_nolapic_timer(char *arg) 2288{ 2289 disable_apic_timer = 1; 2290 return 0; 2291} 2292early_param("nolapic_timer", parse_nolapic_timer); 2293 2294static int __init apic_set_verbosity(char *arg) 2295{ 2296 if (!arg) { 2297#ifdef CONFIG_X86_64 2298 skip_ioapic_setup = 0; 2299 return 0; 2300#endif 2301 return -EINVAL; 2302 } 2303 2304 if (strcmp("debug", arg) == 0) 2305 apic_verbosity = APIC_DEBUG; 2306 else if (strcmp("verbose", arg) == 0) 2307 apic_verbosity = APIC_VERBOSE; 2308 else { 2309 pr_warning("APIC Verbosity level %s not recognised" 2310 " use apic=verbose or apic=debug\n", arg); 2311 return -EINVAL; 2312 } 2313 2314 return 0; 2315} 2316early_param("apic", apic_set_verbosity); 2317 2318static int __init lapic_insert_resource(void) 2319{ 2320 if (!apic_phys) 2321 return -1; 2322 2323 /* Put local APIC into the resource map. */ 2324 lapic_resource.start = apic_phys; 2325 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2326 insert_resource(&iomem_resource, &lapic_resource); 2327 2328 return 0; 2329} 2330 2331/* 2332 * need call insert after e820_reserve_resources() 2333 * that is using request_resource 2334 */ 2335late_initcall(lapic_insert_resource); 2336