1/* 2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15/** 16 * @file hypervisor.h 17 * The hypervisor's public API. 18 */ 19 20#ifndef _TILE_HV_H 21#define _TILE_HV_H 22 23#include <arch/chip.h> 24 25#include <hv/pagesize.h> 26 27/* Linux builds want unsigned long constants, but assembler wants numbers */ 28#ifdef __ASSEMBLER__ 29/** One, for assembler */ 30#define __HV_SIZE_ONE 1 31#elif !defined(__tile__) && CHIP_VA_WIDTH() > 32 32/** One, for 64-bit on host */ 33#define __HV_SIZE_ONE 1ULL 34#else 35/** One, for Linux */ 36#define __HV_SIZE_ONE 1UL 37#endif 38 39/** The log2 of the span of a level-1 page table, in bytes. 40 */ 41#define HV_LOG2_L1_SPAN 32 42 43/** The span of a level-1 page table, in bytes. 44 */ 45#define HV_L1_SPAN (__HV_SIZE_ONE << HV_LOG2_L1_SPAN) 46 47/** The size of small pages, in bytes. This value should be verified 48 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL). 49 */ 50#define HV_PAGE_SIZE_SMALL (__HV_SIZE_ONE << HV_LOG2_PAGE_SIZE_SMALL) 51 52/** The size of large pages, in bytes. This value should be verified 53 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE). 54 */ 55#define HV_PAGE_SIZE_LARGE (__HV_SIZE_ONE << HV_LOG2_PAGE_SIZE_LARGE) 56 57/** The log2 of the granularity at which page tables must be aligned; 58 * in other words, the CPA for a page table must have this many zero 59 * bits at the bottom of the address. 60 */ 61#define HV_LOG2_PAGE_TABLE_ALIGN 11 62 63/** The granularity at which page tables must be aligned. 64 */ 65#define HV_PAGE_TABLE_ALIGN (__HV_SIZE_ONE << HV_LOG2_PAGE_TABLE_ALIGN) 66 67/** Normal start of hypervisor glue in client physical memory. */ 68#define HV_GLUE_START_CPA 0x10000 69 70/** This much space is reserved at HV_GLUE_START_CPA 71 * for the hypervisor glue. The client program must start at 72 * some address higher than this, and in particular the address of 73 * its text section should be equal to zero modulo HV_PAGE_SIZE_LARGE 74 * so that relative offsets to the HV glue are correct. 75 */ 76#define HV_GLUE_RESERVED_SIZE 0x10000 77 78/** Each entry in the hv dispatch array takes this many bytes. */ 79#define HV_DISPATCH_ENTRY_SIZE 32 80 81/** Version of the hypervisor interface defined by this file */ 82#define _HV_VERSION 11 83 84/* Index into hypervisor interface dispatch code blocks. 85 * 86 * Hypervisor calls are invoked from user space by calling code 87 * at an address HV_BASE_ADDRESS + (index) * HV_DISPATCH_ENTRY_SIZE, 88 * where index is one of these enum values. 89 * 90 * Normally a supervisor is expected to produce a set of symbols 91 * starting at HV_BASE_ADDRESS that obey this convention, but a user 92 * program could call directly through function pointers if desired. 93 * 94 * These numbers are part of the binary API and will not be changed 95 * without updating HV_VERSION, which should be a rare event. 96 */ 97 98/** reserved. */ 99#define _HV_DISPATCH_RESERVED 0 100 101/** hv_init */ 102#define HV_DISPATCH_INIT 1 103 104/** hv_install_context */ 105#define HV_DISPATCH_INSTALL_CONTEXT 2 106 107/** hv_sysconf */ 108#define HV_DISPATCH_SYSCONF 3 109 110/** hv_get_rtc */ 111#define HV_DISPATCH_GET_RTC 4 112 113/** hv_set_rtc */ 114#define HV_DISPATCH_SET_RTC 5 115 116/** hv_flush_asid */ 117#define HV_DISPATCH_FLUSH_ASID 6 118 119/** hv_flush_page */ 120#define HV_DISPATCH_FLUSH_PAGE 7 121 122/** hv_flush_pages */ 123#define HV_DISPATCH_FLUSH_PAGES 8 124 125/** hv_restart */ 126#define HV_DISPATCH_RESTART 9 127 128/** hv_halt */ 129#define HV_DISPATCH_HALT 10 130 131/** hv_power_off */ 132#define HV_DISPATCH_POWER_OFF 11 133 134/** hv_inquire_physical */ 135#define HV_DISPATCH_INQUIRE_PHYSICAL 12 136 137/** hv_inquire_memory_controller */ 138#define HV_DISPATCH_INQUIRE_MEMORY_CONTROLLER 13 139 140/** hv_inquire_virtual */ 141#define HV_DISPATCH_INQUIRE_VIRTUAL 14 142 143/** hv_inquire_asid */ 144#define HV_DISPATCH_INQUIRE_ASID 15 145 146/** hv_nanosleep */ 147#define HV_DISPATCH_NANOSLEEP 16 148 149/** hv_console_read_if_ready */ 150#define HV_DISPATCH_CONSOLE_READ_IF_READY 17 151 152/** hv_console_write */ 153#define HV_DISPATCH_CONSOLE_WRITE 18 154 155/** hv_downcall_dispatch */ 156#define HV_DISPATCH_DOWNCALL_DISPATCH 19 157 158/** hv_inquire_topology */ 159#define HV_DISPATCH_INQUIRE_TOPOLOGY 20 160 161/** hv_fs_findfile */ 162#define HV_DISPATCH_FS_FINDFILE 21 163 164/** hv_fs_fstat */ 165#define HV_DISPATCH_FS_FSTAT 22 166 167/** hv_fs_pread */ 168#define HV_DISPATCH_FS_PREAD 23 169 170/** hv_physaddr_read64 */ 171#define HV_DISPATCH_PHYSADDR_READ64 24 172 173/** hv_physaddr_write64 */ 174#define HV_DISPATCH_PHYSADDR_WRITE64 25 175 176/** hv_get_command_line */ 177#define HV_DISPATCH_GET_COMMAND_LINE 26 178 179/** hv_set_caching */ 180#define HV_DISPATCH_SET_CACHING 27 181 182/** hv_bzero_page */ 183#define HV_DISPATCH_BZERO_PAGE 28 184 185/** hv_register_message_state */ 186#define HV_DISPATCH_REGISTER_MESSAGE_STATE 29 187 188/** hv_send_message */ 189#define HV_DISPATCH_SEND_MESSAGE 30 190 191/** hv_receive_message */ 192#define HV_DISPATCH_RECEIVE_MESSAGE 31 193 194/** hv_inquire_context */ 195#define HV_DISPATCH_INQUIRE_CONTEXT 32 196 197/** hv_start_all_tiles */ 198#define HV_DISPATCH_START_ALL_TILES 33 199 200/** hv_dev_open */ 201#define HV_DISPATCH_DEV_OPEN 34 202 203/** hv_dev_close */ 204#define HV_DISPATCH_DEV_CLOSE 35 205 206/** hv_dev_pread */ 207#define HV_DISPATCH_DEV_PREAD 36 208 209/** hv_dev_pwrite */ 210#define HV_DISPATCH_DEV_PWRITE 37 211 212/** hv_dev_poll */ 213#define HV_DISPATCH_DEV_POLL 38 214 215/** hv_dev_poll_cancel */ 216#define HV_DISPATCH_DEV_POLL_CANCEL 39 217 218/** hv_dev_preada */ 219#define HV_DISPATCH_DEV_PREADA 40 220 221/** hv_dev_pwritea */ 222#define HV_DISPATCH_DEV_PWRITEA 41 223 224/** hv_flush_remote */ 225#define HV_DISPATCH_FLUSH_REMOTE 42 226 227/** hv_console_putc */ 228#define HV_DISPATCH_CONSOLE_PUTC 43 229 230/** hv_inquire_tiles */ 231#define HV_DISPATCH_INQUIRE_TILES 44 232 233/** hv_confstr */ 234#define HV_DISPATCH_CONFSTR 45 235 236/** hv_reexec */ 237#define HV_DISPATCH_REEXEC 46 238 239/** hv_set_command_line */ 240#define HV_DISPATCH_SET_COMMAND_LINE 47 241 242#if !CHIP_HAS_IPI() 243 244/** hv_clear_intr */ 245#define HV_DISPATCH_CLEAR_INTR 48 246 247/** hv_enable_intr */ 248#define HV_DISPATCH_ENABLE_INTR 49 249 250/** hv_disable_intr */ 251#define HV_DISPATCH_DISABLE_INTR 50 252 253/** hv_raise_intr */ 254#define HV_DISPATCH_RAISE_INTR 51 255 256/** hv_trigger_ipi */ 257#define HV_DISPATCH_TRIGGER_IPI 52 258 259#endif /* !CHIP_HAS_IPI() */ 260 261/** hv_store_mapping */ 262#define HV_DISPATCH_STORE_MAPPING 53 263 264/** hv_inquire_realpa */ 265#define HV_DISPATCH_INQUIRE_REALPA 54 266 267/** hv_flush_all */ 268#define HV_DISPATCH_FLUSH_ALL 55 269 270#if CHIP_HAS_IPI() 271/** hv_get_ipi_pte */ 272#define HV_DISPATCH_GET_IPI_PTE 56 273#endif 274 275/** One more than the largest dispatch value */ 276#define _HV_DISPATCH_END 57 277 278 279#ifndef __ASSEMBLER__ 280 281#ifdef __KERNEL__ 282#include <asm/types.h> 283typedef u32 __hv32; /**< 32-bit value */ 284typedef u64 __hv64; /**< 64-bit value */ 285#else 286#include <stdint.h> 287typedef uint32_t __hv32; /**< 32-bit value */ 288typedef uint64_t __hv64; /**< 64-bit value */ 289#endif 290 291 292/** Hypervisor physical address. */ 293typedef __hv64 HV_PhysAddr; 294 295#if CHIP_VA_WIDTH() > 32 296/** Hypervisor virtual address. */ 297typedef __hv64 HV_VirtAddr; 298#else 299/** Hypervisor virtual address. */ 300typedef __hv32 HV_VirtAddr; 301#endif /* CHIP_VA_WIDTH() > 32 */ 302 303/** Hypervisor ASID. */ 304typedef unsigned int HV_ASID; 305 306/** Hypervisor tile location for a memory access 307 * ("location overridden target"). 308 */ 309typedef unsigned int HV_LOTAR; 310 311/** Hypervisor size of a page. */ 312typedef unsigned long HV_PageSize; 313 314/** A page table entry. 315 */ 316typedef struct 317{ 318 __hv64 val; /**< Value of PTE */ 319} HV_PTE; 320 321/** Hypervisor error code. */ 322typedef int HV_Errno; 323 324#endif /* !__ASSEMBLER__ */ 325 326#define HV_OK 0 /**< No error */ 327#define HV_EINVAL -801 /**< Invalid argument */ 328#define HV_ENODEV -802 /**< No such device */ 329#define HV_ENOENT -803 /**< No such file or directory */ 330#define HV_EBADF -804 /**< Bad file number */ 331#define HV_EFAULT -805 /**< Bad address */ 332#define HV_ERECIP -806 /**< Bad recipients */ 333#define HV_E2BIG -807 /**< Message too big */ 334#define HV_ENOTSUP -808 /**< Service not supported */ 335#define HV_EBUSY -809 /**< Device busy */ 336#define HV_ENOSYS -810 /**< Invalid syscall */ 337#define HV_EPERM -811 /**< No permission */ 338#define HV_ENOTREADY -812 /**< Device not ready */ 339#define HV_EIO -813 /**< I/O error */ 340#define HV_ENOMEM -814 /**< Out of memory */ 341 342#define HV_ERR_MAX -801 /**< Largest HV error code */ 343#define HV_ERR_MIN -814 /**< Smallest HV error code */ 344 345#ifndef __ASSEMBLER__ 346 347/** Pass HV_VERSION to hv_init to request this version of the interface. */ 348typedef enum { HV_VERSION = _HV_VERSION } HV_VersionNumber; 349 350/** Initializes the hypervisor. 351 * 352 * @param interface_version_number The version of the hypervisor interface 353 * that this program expects, typically HV_VERSION. 354 * @param chip_num Architecture number of the chip the client was built for. 355 * @param chip_rev_num Revision number of the chip the client was built for. 356 */ 357void hv_init(HV_VersionNumber interface_version_number, 358 int chip_num, int chip_rev_num); 359 360 361/** Queries we can make for hv_sysconf(). 362 * 363 * These numbers are part of the binary API and guaranteed not to change. 364 */ 365typedef enum { 366 /** An invalid value; do not use. */ 367 _HV_SYSCONF_RESERVED = 0, 368 369 /** The length of the glue section containing the hv_ procs, in bytes. */ 370 HV_SYSCONF_GLUE_SIZE = 1, 371 372 /** The size of small pages, in bytes. */ 373 HV_SYSCONF_PAGE_SIZE_SMALL = 2, 374 375 /** The size of large pages, in bytes. */ 376 HV_SYSCONF_PAGE_SIZE_LARGE = 3, 377 378 /** Processor clock speed, in hertz. */ 379 HV_SYSCONF_CPU_SPEED = 4, 380 381 /** Processor temperature, in degrees Kelvin. The value 382 * HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees 383 * Celsius. If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates 384 * that the temperature has hit an upper limit and is no longer being 385 * accurately tracked. 386 */ 387 HV_SYSCONF_CPU_TEMP = 5, 388 389 /** Board temperature, in degrees Kelvin. The value 390 * HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees 391 * Celsius. If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates 392 * that the temperature has hit an upper limit and is no longer being 393 * accurately tracked. 394 */ 395 HV_SYSCONF_BOARD_TEMP = 6 396 397} HV_SysconfQuery; 398 399/** Offset to subtract from returned Kelvin temperature to get degrees 400 Celsius. */ 401#define HV_SYSCONF_TEMP_KTOC 273 402 403/** Pseudo-temperature value indicating that the temperature has 404 * pegged at its upper limit and is no longer accurate; note that this is 405 * the value after subtracting HV_SYSCONF_TEMP_KTOC. */ 406#define HV_SYSCONF_OVERTEMP 999 407 408/** Query a configuration value from the hypervisor. 409 * @param query Which value is requested (HV_SYSCONF_xxx). 410 * @return The requested value, or -1 the requested value is illegal or 411 * unavailable. 412 */ 413long hv_sysconf(HV_SysconfQuery query); 414 415 416/** Queries we can make for hv_confstr(). 417 * 418 * These numbers are part of the binary API and guaranteed not to change. 419 */ 420typedef enum { 421 /** An invalid value; do not use. */ 422 _HV_CONFSTR_RESERVED = 0, 423 424 /** Board part number. */ 425 HV_CONFSTR_BOARD_PART_NUM = 1, 426 427 /** Board serial number. */ 428 HV_CONFSTR_BOARD_SERIAL_NUM = 2, 429 430 /** Chip serial number. */ 431 HV_CONFSTR_CHIP_SERIAL_NUM = 3, 432 433 /** Board revision level. */ 434 HV_CONFSTR_BOARD_REV = 4, 435 436 /** Hypervisor software version. */ 437 HV_CONFSTR_HV_SW_VER = 5, 438 439 /** The name for this chip model. */ 440 HV_CONFSTR_CHIP_MODEL = 6, 441 442 /** Human-readable board description. */ 443 HV_CONFSTR_BOARD_DESC = 7, 444 445 /** Human-readable description of the hypervisor configuration. */ 446 HV_CONFSTR_HV_CONFIG = 8, 447 448 /** Human-readable version string for the boot image (for instance, 449 * who built it and when, what configuration file was used). */ 450 HV_CONFSTR_HV_CONFIG_VER = 9, 451 452 /** Mezzanine part number. */ 453 HV_CONFSTR_MEZZ_PART_NUM = 10, 454 455 /** Mezzanine serial number. */ 456 HV_CONFSTR_MEZZ_SERIAL_NUM = 11, 457 458 /** Mezzanine revision level. */ 459 HV_CONFSTR_MEZZ_REV = 12, 460 461 /** Human-readable mezzanine description. */ 462 HV_CONFSTR_MEZZ_DESC = 13, 463 464 /** Control path for the onboard network switch. */ 465 HV_CONFSTR_SWITCH_CONTROL = 14, 466 467 /** Chip revision level. */ 468 HV_CONFSTR_CHIP_REV = 15 469 470} HV_ConfstrQuery; 471 472/** Query a configuration string from the hypervisor. 473 * 474 * @param query Identifier for the specific string to be retrieved 475 * (HV_CONFSTR_xxx). 476 * @param buf Buffer in which to place the string. 477 * @param len Length of the buffer. 478 * @return If query is valid, then the length of the corresponding string, 479 * including the trailing null; if this is greater than len, the string 480 * was truncated. If query is invalid, HV_EINVAL. If the specified 481 * buffer is not writable by the client, HV_EFAULT. 482 */ 483int hv_confstr(HV_ConfstrQuery query, HV_VirtAddr buf, int len); 484 485/** Tile coordinate */ 486typedef struct 487{ 488 /** X coordinate, relative to supervisor's top-left coordinate */ 489 int x; 490 491 /** Y coordinate, relative to supervisor's top-left coordinate */ 492 int y; 493} HV_Coord; 494 495 496#if CHIP_HAS_IPI() 497 498/** Get the PTE for sending an IPI to a particular tile. 499 * 500 * @param tile Tile which will receive the IPI. 501 * @param pl Indicates which IPI registers: 0 = IPI_0, 1 = IPI_1. 502 * @param pte Filled with resulting PTE. 503 * @result Zero if no error, non-zero for invalid parameters. 504 */ 505int hv_get_ipi_pte(HV_Coord tile, int pl, HV_PTE* pte); 506 507#else /* !CHIP_HAS_IPI() */ 508 509/** A set of interrupts. */ 510typedef __hv32 HV_IntrMask; 511 512/** The low interrupt numbers are reserved for use by the client in 513 * delivering IPIs. Any interrupt numbers higher than this value are 514 * reserved for use by HV device drivers. */ 515#define HV_MAX_IPI_INTERRUPT 7 516 517/** Enable a set of device interrupts. 518 * 519 * @param enab_mask Bitmap of interrupts to enable. 520 */ 521void hv_enable_intr(HV_IntrMask enab_mask); 522 523/** Disable a set of device interrupts. 524 * 525 * @param disab_mask Bitmap of interrupts to disable. 526 */ 527void hv_disable_intr(HV_IntrMask disab_mask); 528 529/** Clear a set of device interrupts. 530 * 531 * @param clear_mask Bitmap of interrupts to clear. 532 */ 533void hv_clear_intr(HV_IntrMask clear_mask); 534 535/** Raise a set of device interrupts. 536 * 537 * @param raise_mask Bitmap of interrupts to raise. 538 */ 539void hv_raise_intr(HV_IntrMask raise_mask); 540 541/** Trigger a one-shot interrupt on some tile 542 * 543 * @param tile Which tile to interrupt. 544 * @param interrupt Interrupt number to trigger; must be between 0 and 545 * HV_MAX_IPI_INTERRUPT. 546 * @return HV_OK on success, or a hypervisor error code. 547 */ 548HV_Errno hv_trigger_ipi(HV_Coord tile, int interrupt); 549 550#endif /* !CHIP_HAS_IPI() */ 551 552/** Store memory mapping in debug memory so that external debugger can read it. 553 * A maximum of 16 entries can be stored. 554 * 555 * @param va VA of memory that is mapped. 556 * @param len Length of mapped memory. 557 * @param pa PA of memory that is mapped. 558 * @return 0 on success, -1 if the maximum number of mappings is exceeded. 559 */ 560int hv_store_mapping(HV_VirtAddr va, unsigned int len, HV_PhysAddr pa); 561 562/** Given a client PA and a length, return its real (HV) PA. 563 * 564 * @param cpa Client physical address. 565 * @param len Length of mapped memory. 566 * @return physical address, or -1 if cpa or len is not valid. 567 */ 568HV_PhysAddr hv_inquire_realpa(HV_PhysAddr cpa, unsigned int len); 569 570/** RTC return flag for no RTC chip present. 571 */ 572#define HV_RTC_NO_CHIP 0x1 573 574/** RTC return flag for low-voltage condition, indicating that battery had 575 * died and time read is unreliable. 576 */ 577#define HV_RTC_LOW_VOLTAGE 0x2 578 579/** Date/Time of day */ 580typedef struct { 581#if CHIP_WORD_SIZE() > 32 582 __hv64 tm_sec; /**< Seconds, 0-59 */ 583 __hv64 tm_min; /**< Minutes, 0-59 */ 584 __hv64 tm_hour; /**< Hours, 0-23 */ 585 __hv64 tm_mday; /**< Day of month, 0-30 */ 586 __hv64 tm_mon; /**< Month, 0-11 */ 587 __hv64 tm_year; /**< Years since 1900, 0-199 */ 588 __hv64 flags; /**< Return flags, 0 if no error */ 589#else 590 __hv32 tm_sec; /**< Seconds, 0-59 */ 591 __hv32 tm_min; /**< Minutes, 0-59 */ 592 __hv32 tm_hour; /**< Hours, 0-23 */ 593 __hv32 tm_mday; /**< Day of month, 0-30 */ 594 __hv32 tm_mon; /**< Month, 0-11 */ 595 __hv32 tm_year; /**< Years since 1900, 0-199 */ 596 __hv32 flags; /**< Return flags, 0 if no error */ 597#endif 598} HV_RTCTime; 599 600/** Read the current time-of-day clock. 601 * @return HV_RTCTime of current time (GMT). 602 */ 603HV_RTCTime hv_get_rtc(void); 604 605 606/** Set the current time-of-day clock. 607 * @param time time to reset time-of-day to (GMT). 608 */ 609void hv_set_rtc(HV_RTCTime time); 610 611/** Installs a context, comprising a page table and other attributes. 612 * 613 * Once this service completes, page_table will be used to translate 614 * subsequent virtual address references to physical memory. 615 * 616 * Installing a context does not cause an implicit TLB flush. Before 617 * reusing an ASID value for a different address space, the client is 618 * expected to flush old references from the TLB with hv_flush_asid(). 619 * (Alternately, hv_flush_all() may be used to flush many ASIDs at once.) 620 * After invalidating a page table entry, changing its attributes, or 621 * changing its target CPA, the client is expected to flush old references 622 * from the TLB with hv_flush_page() or hv_flush_pages(). Making a 623 * previously invalid page valid does not require a flush. 624 * 625 * Specifying an invalid ASID, or an invalid CPA (client physical address) 626 * (either as page_table_pointer, or within the referenced table), 627 * or another page table data item documented as above as illegal may 628 * lead to client termination; since the validation of the table is 629 * done as needed, this may happen before the service returns, or at 630 * some later time, or never, depending upon the client's pattern of 631 * memory references. Page table entries which supply translations for 632 * invalid virtual addresses may result in client termination, or may 633 * be silently ignored. "Invalid" in this context means a value which 634 * was not provided to the client via the appropriate hv_inquire_* routine. 635 * 636 * To support changing the instruction VAs at the same time as 637 * installing the new page table, this call explicitly supports 638 * setting the "lr" register to a different address and then jumping 639 * directly to the hv_install_context() routine. In this case, the 640 * new page table does not need to contain any mapping for the 641 * hv_install_context address itself. 642 * 643 * @param page_table Root of the page table. 644 * @param access PTE providing info on how to read the page table. This 645 * value must be consistent between multiple tiles sharing a page table, 646 * and must also be consistent with any virtual mappings the client 647 * may be using to access the page table. 648 * @param asid HV_ASID the page table is to be used for. 649 * @param flags Context flags, denoting attributes or privileges of the 650 * current context (HV_CTX_xxx). 651 * @return Zero on success, or a hypervisor error code on failure. 652 */ 653int hv_install_context(HV_PhysAddr page_table, HV_PTE access, HV_ASID asid, 654 __hv32 flags); 655 656#endif /* !__ASSEMBLER__ */ 657 658#define HV_CTX_DIRECTIO 0x1 /**< Direct I/O requests are accepted from 659 PL0. */ 660 661#ifndef __ASSEMBLER__ 662 663/** Value returned from hv_inquire_context(). */ 664typedef struct 665{ 666 /** Physical address of page table */ 667 HV_PhysAddr page_table; 668 669 /** PTE which defines access method for top of page table */ 670 HV_PTE access; 671 672 /** ASID associated with this page table */ 673 HV_ASID asid; 674 675 /** Context flags */ 676 __hv32 flags; 677} HV_Context; 678 679/** Retrieve information about the currently installed context. 680 * @return The data passed to the last successful hv_install_context call. 681 */ 682HV_Context hv_inquire_context(void); 683 684 685/** Flushes all translations associated with the named address space 686 * identifier from the TLB and any other hypervisor data structures. 687 * Translations installed with the "global" bit are not flushed. 688 * 689 * Specifying an invalid ASID may lead to client termination. "Invalid" 690 * in this context means a value which was not provided to the client 691 * via <tt>hv_inquire_asid()</tt>. 692 * 693 * @param asid HV_ASID whose entries are to be flushed. 694 * @return Zero on success, or a hypervisor error code on failure. 695*/ 696int hv_flush_asid(HV_ASID asid); 697 698 699/** Flushes all translations associated with the named virtual address 700 * and page size from the TLB and other hypervisor data structures. Only 701 * pages visible to the current ASID are affected; note that this includes 702 * global pages in addition to pages specific to the current ASID. 703 * 704 * The supplied VA need not be aligned; it may be anywhere in the 705 * subject page. 706 * 707 * Specifying an invalid virtual address may lead to client termination, 708 * or may silently succeed. "Invalid" in this context means a value 709 * which was not provided to the client via hv_inquire_virtual. 710 * 711 * @param address Address of the page to flush. 712 * @param page_size Size of pages to assume. 713 * @return Zero on success, or a hypervisor error code on failure. 714 */ 715int hv_flush_page(HV_VirtAddr address, HV_PageSize page_size); 716 717 718/** Flushes all translations associated with the named virtual address range 719 * and page size from the TLB and other hypervisor data structures. Only 720 * pages visible to the current ASID are affected; note that this includes 721 * global pages in addition to pages specific to the current ASID. 722 * 723 * The supplied VA need not be aligned; it may be anywhere in the 724 * subject page. 725 * 726 * Specifying an invalid virtual address may lead to client termination, 727 * or may silently succeed. "Invalid" in this context means a value 728 * which was not provided to the client via hv_inquire_virtual. 729 * 730 * @param start Address to flush. 731 * @param page_size Size of pages to assume. 732 * @param size The number of bytes to flush. Any page in the range 733 * [start, start + size) will be flushed from the TLB. 734 * @return Zero on success, or a hypervisor error code on failure. 735 */ 736int hv_flush_pages(HV_VirtAddr start, HV_PageSize page_size, 737 unsigned long size); 738 739 740/** Flushes all non-global translations (if preserve_global is true), 741 * or absolutely all translations (if preserve_global is false). 742 * 743 * @param preserve_global Non-zero if we want to preserve "global" mappings. 744 * @return Zero on success, or a hypervisor error code on failure. 745*/ 746int hv_flush_all(int preserve_global); 747 748 749/** Restart machine with optional restart command and optional args. 750 * @param cmd Const pointer to command to restart with, or NULL 751 * @param args Const pointer to argument string to restart with, or NULL 752 */ 753void hv_restart(HV_VirtAddr cmd, HV_VirtAddr args); 754 755 756/** Halt machine. */ 757void hv_halt(void); 758 759 760/** Power off machine. */ 761void hv_power_off(void); 762 763 764/** Re-enter virtual-is-physical memory translation mode and restart 765 * execution at a given address. 766 * @param entry Client physical address at which to begin execution. 767 * @return A hypervisor error code on failure; if the operation is 768 * successful the call does not return. 769 */ 770int hv_reexec(HV_PhysAddr entry); 771 772 773/** Chip topology */ 774typedef struct 775{ 776 /** Relative coordinates of the querying tile */ 777 HV_Coord coord; 778 779 /** Width of the querying supervisor's tile rectangle. */ 780 int width; 781 782 /** Height of the querying supervisor's tile rectangle. */ 783 int height; 784 785} HV_Topology; 786 787/** Returns information about the tile coordinate system. 788 * 789 * Each supervisor is given a rectangle of tiles it potentially controls. 790 * These tiles are labeled using a relative coordinate system with (0,0) as 791 * the upper left tile regardless of their physical location on the chip. 792 * 793 * This call returns both the size of that rectangle and the position 794 * within that rectangle of the querying tile. 795 * 796 * Not all tiles within that rectangle may be available to the supervisor; 797 * to get the precise set of available tiles, you must also call 798 * hv_inquire_tiles(HV_INQ_TILES_AVAIL, ...). 799 **/ 800HV_Topology hv_inquire_topology(void); 801 802/** Sets of tiles we can retrieve with hv_inquire_tiles(). 803 * 804 * These numbers are part of the binary API and guaranteed not to change. 805 */ 806typedef enum { 807 /** An invalid value; do not use. */ 808 _HV_INQ_TILES_RESERVED = 0, 809 810 /** All available tiles within the supervisor's tile rectangle. */ 811 HV_INQ_TILES_AVAIL = 1, 812 813 /** The set of tiles used for hash-for-home caching. */ 814 HV_INQ_TILES_HFH_CACHE = 2, 815 816 /** The set of tiles that can be legally used as a LOTAR for a PTE. */ 817 HV_INQ_TILES_LOTAR = 3 818} HV_InqTileSet; 819 820/** Returns specific information about various sets of tiles within the 821 * supervisor's tile rectangle. 822 * 823 * @param set Which set of tiles to retrieve. 824 * @param cpumask Pointer to a returned bitmask (in row-major order, 825 * supervisor-relative) of tiles. The low bit of the first word 826 * corresponds to the tile at the upper left-hand corner of the 827 * supervisor's rectangle. In order for the supervisor to know the 828 * buffer length to supply, it should first call hv_inquire_topology. 829 * @param length Number of bytes available for the returned bitmask. 830 **/ 831HV_Errno hv_inquire_tiles(HV_InqTileSet set, HV_VirtAddr cpumask, int length); 832 833 834/** An identifier for a memory controller. Multiple memory controllers 835 * may be connected to one chip, and this uniquely identifies each one. 836 */ 837typedef int HV_MemoryController; 838 839/** A range of physical memory. */ 840typedef struct 841{ 842 HV_PhysAddr start; /**< Starting address. */ 843 __hv64 size; /**< Size in bytes. */ 844 HV_MemoryController controller; /**< Which memory controller owns this. */ 845} HV_PhysAddrRange; 846 847/** Returns information about a range of physical memory. 848 * 849 * hv_inquire_physical() returns one of the ranges of client 850 * physical addresses which are available to this client. 851 * 852 * The first range is retrieved by specifying an idx of 0, and 853 * successive ranges are returned with subsequent idx values. Ranges 854 * are ordered by increasing start address (i.e., as idx increases, 855 * so does start), do not overlap, and do not touch (i.e., the 856 * available memory is described with the fewest possible ranges). 857 * 858 * If an out-of-range idx value is specified, the returned size will be zero. 859 * A client can count the number of ranges by increasing idx until the 860 * returned size is zero. There will always be at least one valid range. 861 * 862 * Some clients might not be prepared to deal with more than one 863 * physical address range; they still ought to call this routine and 864 * issue a warning message if they're given more than one range, on the 865 * theory that whoever configured the hypervisor to provide that memory 866 * should know that it's being wasted. 867 */ 868HV_PhysAddrRange hv_inquire_physical(int idx); 869 870 871/** Memory controller information. */ 872typedef struct 873{ 874 HV_Coord coord; /**< Relative tile coordinates of the port used by a 875 specified tile to communicate with this controller. */ 876 __hv64 speed; /**< Speed of this controller in bytes per second. */ 877} HV_MemoryControllerInfo; 878 879/** Returns information about a particular memory controller. 880 * 881 * hv_inquire_memory_controller(coord,idx) returns information about a 882 * particular controller. Two pieces of information are returned: 883 * - The relative coordinates of the port on the controller that the specified 884 * tile would use to contact it. The relative coordinates may lie 885 * outside the supervisor's rectangle, i.e. the controller may not 886 * be attached to a node managed by the querying node's supervisor. 887 * In particular note that x or y may be negative. 888 * - The speed of the memory controller. (This is a not-to-exceed value 889 * based on the raw hardware data rate, and may not be achievable in 890 * practice; it is provided to give clients information on the relative 891 * performance of the available controllers.) 892 * 893 * Clients should avoid calling this interface with invalid values. 894 * A client who does may be terminated. 895 * @param coord Tile for which to calculate the relative port position. 896 * @param controller Index of the controller; identical to value returned 897 * from other routines like hv_inquire_physical. 898 * @return Information about the controller. 899 */ 900HV_MemoryControllerInfo hv_inquire_memory_controller(HV_Coord coord, 901 int controller); 902 903 904/** A range of virtual memory. */ 905typedef struct 906{ 907 HV_VirtAddr start; /**< Starting address. */ 908 __hv64 size; /**< Size in bytes. */ 909} HV_VirtAddrRange; 910 911/** Returns information about a range of virtual memory. 912 * 913 * hv_inquire_virtual() returns one of the ranges of client 914 * virtual addresses which are available to this client. 915 * 916 * The first range is retrieved by specifying an idx of 0, and 917 * successive ranges are returned with subsequent idx values. Ranges 918 * are ordered by increasing start address (i.e., as idx increases, 919 * so does start), do not overlap, and do not touch (i.e., the 920 * available memory is described with the fewest possible ranges). 921 * 922 * If an out-of-range idx value is specified, the returned size will be zero. 923 * A client can count the number of ranges by increasing idx until the 924 * returned size is zero. There will always be at least one valid range. 925 * 926 * Some clients may well have various virtual addresses hardwired 927 * into themselves; for instance, their instruction stream may 928 * have been compiled expecting to live at a particular address. 929 * Such clients should use this interface to verify they've been 930 * given the virtual address space they expect, and issue a (potentially 931 * fatal) warning message otherwise. 932 * 933 * Note that the returned size is a __hv64, not a __hv32, so it is 934 * possible to express a single range spanning the entire 32-bit 935 * address space. 936 */ 937HV_VirtAddrRange hv_inquire_virtual(int idx); 938 939 940/** A range of ASID values. */ 941typedef struct 942{ 943 HV_ASID start; /**< First ASID in the range. */ 944 unsigned int size; /**< Number of ASIDs. Zero for an invalid range. */ 945} HV_ASIDRange; 946 947/** Returns information about a range of ASIDs. 948 * 949 * hv_inquire_asid() returns one of the ranges of address 950 * space identifiers which are available to this client. 951 * 952 * The first range is retrieved by specifying an idx of 0, and 953 * successive ranges are returned with subsequent idx values. Ranges 954 * are ordered by increasing start value (i.e., as idx increases, 955 * so does start), do not overlap, and do not touch (i.e., the 956 * available ASIDs are described with the fewest possible ranges). 957 * 958 * If an out-of-range idx value is specified, the returned size will be zero. 959 * A client can count the number of ranges by increasing idx until the 960 * returned size is zero. There will always be at least one valid range. 961 */ 962HV_ASIDRange hv_inquire_asid(int idx); 963 964 965/** Waits for at least the specified number of nanoseconds then returns. 966 * 967 * @param nanosecs The number of nanoseconds to sleep. 968 */ 969void hv_nanosleep(int nanosecs); 970 971 972/** Reads a character from the console without blocking. 973 * 974 * @return A value from 0-255 indicates the value successfully read. 975 * A negative value means no value was ready. 976 */ 977int hv_console_read_if_ready(void); 978 979 980/** Writes a character to the console, blocking if the console is busy. 981 * 982 * This call cannot fail. If the console is broken for some reason, 983 * output will simply vanish. 984 * @param byte Character to write. 985 */ 986void hv_console_putc(int byte); 987 988 989/** Writes a string to the console, blocking if the console is busy. 990 * @param bytes Pointer to characters to write. 991 * @param len Number of characters to write. 992 * @return Number of characters written, or HV_EFAULT if the buffer is invalid. 993 */ 994int hv_console_write(HV_VirtAddr bytes, int len); 995 996 997/** Dispatch the next interrupt from the client downcall mechanism. 998 * 999 * The hypervisor uses downcalls to notify the client of asynchronous 1000 * events. Some of these events are hypervisor-created (like incoming 1001 * messages). Some are regular interrupts which initially occur in 1002 * the hypervisor, and are normally handled directly by the client; 1003 * when these occur in a client's interrupt critical section, they must 1004 * be delivered through the downcall mechanism. 1005 * 1006 * A downcall is initially delivered to the client as an INTCTRL_1 1007 * interrupt. Upon entry to the INTCTRL_1 vector, the client must 1008 * immediately invoke the hv_downcall_dispatch service. This service 1009 * will not return; instead it will cause one of the client's actual 1010 * downcall-handling interrupt vectors to be entered. The EX_CONTEXT 1011 * registers in the client will be set so that when the client irets, 1012 * it will return to the code which was interrupted by the INTCTRL_1 1013 * interrupt. 1014 * 1015 * Under some circumstances, the firing of INTCTRL_1 can race with 1016 * the lowering of a device interrupt. In such a case, the 1017 * hv_downcall_dispatch service may issue an iret instruction instead 1018 * of entering one of the client's actual downcall-handling interrupt 1019 * vectors. This will return execution to the location that was 1020 * interrupted by INTCTRL_1. 1021 * 1022 * Any saving of registers should be done by the actual handling 1023 * vectors; no registers should be changed by the INTCTRL_1 handler. 1024 * In particular, the client should not use a jal instruction to invoke 1025 * the hv_downcall_dispatch service, as that would overwrite the client's 1026 * lr register. Note that the hv_downcall_dispatch service may overwrite 1027 * one or more of the client's system save registers. 1028 * 1029 * The client must not modify the INTCTRL_1_STATUS SPR. The hypervisor 1030 * will set this register to cause a downcall to happen, and will clear 1031 * it when no further downcalls are pending. 1032 * 1033 * When a downcall vector is entered, the INTCTRL_1 interrupt will be 1034 * masked. When the client is done processing a downcall, and is ready 1035 * to accept another, it must unmask this interrupt; if more downcalls 1036 * are pending, this will cause the INTCTRL_1 vector to be reentered. 1037 * Currently the following interrupt vectors can be entered through a 1038 * downcall: 1039 * 1040 * INT_MESSAGE_RCV_DWNCL (hypervisor message available) 1041 * INT_DMATLB_MISS_DWNCL (DMA TLB miss) 1042 * INT_SNITLB_MISS_DWNCL (SNI TLB miss) 1043 * INT_DMATLB_ACCESS_DWNCL (DMA TLB access violation) 1044 */ 1045void hv_downcall_dispatch(void); 1046 1047#endif /* !__ASSEMBLER__ */ 1048 1049/** We use actual interrupt vectors which never occur (they're only there 1050 * to allow setting MPLs for related SPRs) for our downcall vectors. 1051 */ 1052/** Message receive downcall interrupt vector */ 1053#define INT_MESSAGE_RCV_DWNCL INT_BOOT_ACCESS 1054/** DMA TLB miss downcall interrupt vector */ 1055#define INT_DMATLB_MISS_DWNCL INT_DMA_ASID 1056/** Static nework processor instruction TLB miss interrupt vector */ 1057#define INT_SNITLB_MISS_DWNCL INT_SNI_ASID 1058/** DMA TLB access violation downcall interrupt vector */ 1059#define INT_DMATLB_ACCESS_DWNCL INT_DMA_CPL 1060/** Device interrupt downcall interrupt vector */ 1061#define INT_DEV_INTR_DWNCL INT_WORLD_ACCESS 1062 1063#ifndef __ASSEMBLER__ 1064 1065/** Requests the inode for a specific full pathname. 1066 * 1067 * Performs a lookup in the hypervisor filesystem for a given filename. 1068 * Multiple calls with the same filename will always return the same inode. 1069 * If there is no such filename, HV_ENOENT is returned. 1070 * A bad filename pointer may result in HV_EFAULT instead. 1071 * 1072 * @param filename Constant pointer to name of requested file 1073 * @return Inode of requested file 1074 */ 1075int hv_fs_findfile(HV_VirtAddr filename); 1076 1077 1078/** Data returned from an fstat request. 1079 * Note that this structure should be no more than 40 bytes in size so 1080 * that it can always be returned completely in registers. 1081 */ 1082typedef struct 1083{ 1084 int size; /**< Size of file (or HV_Errno on error) */ 1085 unsigned int flags; /**< Flags (see HV_FS_FSTAT_FLAGS) */ 1086} HV_FS_StatInfo; 1087 1088/** Bitmask flags for fstat request */ 1089typedef enum 1090{ 1091 HV_FS_ISDIR = 0x0001 /**< Is the entry a directory? */ 1092} HV_FS_FSTAT_FLAGS; 1093 1094/** Get stat information on a given file inode. 1095 * 1096 * Return information on the file with the given inode. 1097 * 1098 * IF the HV_FS_ISDIR bit is set, the "file" is a directory. Reading 1099 * it will return NUL-separated filenames (no directory part) relative 1100 * to the path to the inode of the directory "file". These can be 1101 * appended to the path to the directory "file" after a forward slash 1102 * to create additional filenames. Note that it is not required 1103 * that all valid paths be decomposable into valid parent directories; 1104 * a filesystem may validly have just a few files, none of which have 1105 * HV_FS_ISDIR set. However, if clients may wish to enumerate the 1106 * files in the filesystem, it is recommended to include all the 1107 * appropriate parent directory "files" to give a consistent view. 1108 * 1109 * An invalid file inode will cause an HV_EBADF error to be returned. 1110 * 1111 * @param inode The inode number of the query 1112 * @return An HV_FS_StatInfo structure 1113 */ 1114HV_FS_StatInfo hv_fs_fstat(int inode); 1115 1116 1117/** Read data from a specific hypervisor file. 1118 * On error, may return HV_EBADF for a bad inode or HV_EFAULT for a bad buf. 1119 * Reads near the end of the file will return fewer bytes than requested. 1120 * Reads at or beyond the end of a file will return zero. 1121 * 1122 * @param inode the hypervisor file to read 1123 * @param buf the buffer to read data into 1124 * @param length the number of bytes of data to read 1125 * @param offset the offset into the file to read the data from 1126 * @return number of bytes successfully read, or an HV_Errno code 1127 */ 1128int hv_fs_pread(int inode, HV_VirtAddr buf, int length, int offset); 1129 1130 1131/** Read a 64-bit word from the specified physical address. 1132 * The address must be 8-byte aligned. 1133 * Specifying an invalid physical address will lead to client termination. 1134 * @param addr The physical address to read 1135 * @param access The PTE describing how to read the memory 1136 * @return The 64-bit value read from the given address 1137 */ 1138unsigned long long hv_physaddr_read64(HV_PhysAddr addr, HV_PTE access); 1139 1140 1141/** Write a 64-bit word to the specified physical address. 1142 * The address must be 8-byte aligned. 1143 * Specifying an invalid physical address will lead to client termination. 1144 * @param addr The physical address to write 1145 * @param access The PTE that says how to write the memory 1146 * @param val The 64-bit value to write to the given address 1147 */ 1148void hv_physaddr_write64(HV_PhysAddr addr, HV_PTE access, 1149 unsigned long long val); 1150 1151 1152/** Get the value of the command-line for the supervisor, if any. 1153 * This will not include the filename of the booted supervisor, but may 1154 * include configured-in boot arguments or the hv_restart() arguments. 1155 * If the buffer is not long enough the hypervisor will NUL the first 1156 * character of the buffer but not write any other data. 1157 * @param buf The virtual address to write the command-line string to. 1158 * @param length The length of buf, in characters. 1159 * @return The actual length of the command line, including the trailing NUL 1160 * (may be larger than "length"). 1161 */ 1162int hv_get_command_line(HV_VirtAddr buf, int length); 1163 1164 1165/** Set a new value for the command-line for the supervisor, which will 1166 * be returned from subsequent invocations of hv_get_command_line() on 1167 * this tile. 1168 * @param buf The virtual address to read the command-line string from. 1169 * @param length The length of buf, in characters; must be no more than 1170 * HV_COMMAND_LINE_LEN. 1171 * @return Zero if successful, or a hypervisor error code. 1172 */ 1173HV_Errno hv_set_command_line(HV_VirtAddr buf, int length); 1174 1175/** Maximum size of a command line passed to hv_set_command_line(); note 1176 * that a line returned from hv_get_command_line() could be larger than 1177 * this.*/ 1178#define HV_COMMAND_LINE_LEN 256 1179 1180/** Tell the hypervisor how to cache non-priority pages 1181 * (its own as well as pages explicitly represented in page tables). 1182 * Normally these will be represented as red/black pages, but 1183 * when the supervisor starts to allocate "priority" pages in the PTE 1184 * the hypervisor will need to start marking those pages as (e.g.) "red" 1185 * and non-priority pages as either "black" (if they cache-alias 1186 * with the existing priority pages) or "red/black" (if they don't). 1187 * The bitmask provides information on which parts of the cache 1188 * have been used for pinned pages so far on this tile; if (1 << N) 1189 * appears in the bitmask, that indicates that a page has been marked 1190 * "priority" whose PFN equals N, mod 8. 1191 * @param bitmask A bitmap of priority page set values 1192 */ 1193void hv_set_caching(unsigned int bitmask); 1194 1195 1196/** Zero out a specified number of pages. 1197 * The va and size must both be multiples of 4096. 1198 * Caches are bypassed and memory is directly set to zero. 1199 * This API is implemented only in the magic hypervisor and is intended 1200 * to provide a performance boost to the minimal supervisor by 1201 * giving it a fast way to zero memory pages when allocating them. 1202 * @param va Virtual address where the page has been mapped 1203 * @param size Number of bytes (must be a page size multiple) 1204 */ 1205void hv_bzero_page(HV_VirtAddr va, unsigned int size); 1206 1207 1208/** State object for the hypervisor messaging subsystem. */ 1209typedef struct 1210{ 1211#if CHIP_VA_WIDTH() > 32 1212 __hv64 opaque[2]; /**< No user-serviceable parts inside */ 1213#else 1214 __hv32 opaque[2]; /**< No user-serviceable parts inside */ 1215#endif 1216} 1217HV_MsgState; 1218 1219/** Register to receive incoming messages. 1220 * 1221 * This routine configures the current tile so that it can receive 1222 * incoming messages. It must be called before the client can receive 1223 * messages with the hv_receive_message routine, and must be called on 1224 * each tile which will receive messages. 1225 * 1226 * msgstate is the virtual address of a state object of type HV_MsgState. 1227 * Once the state is registered, the client must not read or write the 1228 * state object; doing so will cause undefined results. 1229 * 1230 * If this routine is called with msgstate set to 0, the client's message 1231 * state will be freed and it will no longer be able to receive messages. 1232 * Note that this may cause the loss of any as-yet-undelivered messages 1233 * for the client. 1234 * 1235 * If another client attempts to send a message to a client which has 1236 * not yet called hv_register_message_state, or which has freed its 1237 * message state, the message will not be delivered, as if the client 1238 * had insufficient buffering. 1239 * 1240 * This routine returns HV_OK if the registration was successful, and 1241 * HV_EINVAL if the supplied state object is unsuitable. Note that some 1242 * errors may not be detected during this routine, but might be detected 1243 * during a subsequent message delivery. 1244 * @param msgstate State object. 1245 **/ 1246HV_Errno hv_register_message_state(HV_MsgState* msgstate); 1247 1248/** Possible message recipient states. */ 1249typedef enum 1250{ 1251 HV_TO_BE_SENT, /**< Not sent (not attempted, or recipient not ready) */ 1252 HV_SENT, /**< Successfully sent */ 1253 HV_BAD_RECIP /**< Bad recipient coordinates (permanent error) */ 1254} HV_Recip_State; 1255 1256/** Message recipient. */ 1257typedef struct 1258{ 1259 /** X coordinate, relative to supervisor's top-left coordinate */ 1260 unsigned int x:11; 1261 1262 /** Y coordinate, relative to supervisor's top-left coordinate */ 1263 unsigned int y:11; 1264 1265 /** Status of this recipient */ 1266 HV_Recip_State state:10; 1267} HV_Recipient; 1268 1269/** Send a message to a set of recipients. 1270 * 1271 * This routine sends a message to a set of recipients. 1272 * 1273 * recips is an array of HV_Recipient structures. Each specifies a tile, 1274 * and a message state; initially, it is expected that the state will 1275 * be set to HV_TO_BE_SENT. nrecip specifies the number of recipients 1276 * in the recips array. 1277 * 1278 * For each recipient whose state is HV_TO_BE_SENT, the hypervisor attempts 1279 * to send that tile the specified message. In order to successfully 1280 * receive the message, the receiver must be a valid tile to which the 1281 * sender has access, must not be the sending tile itself, and must have 1282 * sufficient free buffer space. (The hypervisor guarantees that each 1283 * tile which has called hv_register_message_state() will be able to 1284 * buffer one message from every other tile which can legally send to it; 1285 * more space may be provided but is not guaranteed.) If an invalid tile 1286 * is specified, the recipient's state is set to HV_BAD_RECIP; this is a 1287 * permanent delivery error. If the message is successfully delivered 1288 * to the recipient's buffer, the recipient's state is set to HV_SENT. 1289 * Otherwise, the recipient's state is unchanged. Message delivery is 1290 * synchronous; all attempts to send messages are completed before this 1291 * routine returns. 1292 * 1293 * If no permanent delivery errors were encountered, the routine returns 1294 * the number of messages successfully sent: that is, the number of 1295 * recipients whose states changed from HV_TO_BE_SENT to HV_SENT during 1296 * this operation. If any permanent delivery errors were encountered, 1297 * the routine returns HV_ERECIP. In the event of permanent delivery 1298 * errors, it may be the case that delivery was not attempted to all 1299 * recipients; if any messages were succesfully delivered, however, 1300 * recipients' state values will be updated appropriately. 1301 * 1302 * It is explicitly legal to specify a recipient structure whose state 1303 * is not HV_TO_BE_SENT; such a recipient is ignored. One suggested way 1304 * of using hv_send_message to send a message to multiple tiles is to set 1305 * up a list of recipients, and then call the routine repeatedly with the 1306 * same list, each time accumulating the number of messages successfully 1307 * sent, until all messages are sent, a permanent error is encountered, 1308 * or the desired number of attempts have been made. When used in this 1309 * way, the routine will deliver each message no more than once to each 1310 * recipient. 1311 * 1312 * Note that a message being successfully delivered to the recipient's 1313 * buffer space does not guarantee that it is received by the recipient, 1314 * either immediately or at any time in the future; the recipient might 1315 * never call hv_receive_message, or could register a different state 1316 * buffer, losing the message. 1317 * 1318 * Specifiying the same recipient more than once in the recipient list 1319 * is an error, which will not result in an error return but which may 1320 * or may not result in more than one message being delivered to the 1321 * recipient tile. 1322 * 1323 * buf and buflen specify the message to be sent. buf is a virtual address 1324 * which must be currently mapped in the client's page table; if not, the 1325 * routine returns HV_EFAULT. buflen must be greater than zero and less 1326 * than or equal to HV_MAX_MESSAGE_SIZE, and nrecip must be less than the 1327 * number of tiles to which the sender has access; if not, the routine 1328 * returns HV_EINVAL. 1329 * @param recips List of recipients. 1330 * @param nrecip Number of recipients. 1331 * @param buf Address of message data. 1332 * @param buflen Length of message data. 1333 **/ 1334int hv_send_message(HV_Recipient *recips, int nrecip, 1335 HV_VirtAddr buf, int buflen); 1336 1337/** Maximum hypervisor message size, in bytes */ 1338#define HV_MAX_MESSAGE_SIZE 28 1339 1340 1341/** Return value from hv_receive_message() */ 1342typedef struct 1343{ 1344 int msglen; /**< Message length in bytes, or an error code */ 1345 __hv32 source; /**< Code identifying message sender (HV_MSG_xxx) */ 1346} HV_RcvMsgInfo; 1347 1348#define HV_MSG_TILE 0x0 /**< Message source is another tile */ 1349#define HV_MSG_INTR 0x1 /**< Message source is a driver interrupt */ 1350 1351/** Receive a message. 1352 * 1353 * This routine retrieves a message from the client's incoming message 1354 * buffer. 1355 * 1356 * Multiple messages sent from a particular sending tile to a particular 1357 * receiving tile are received in the order that they were sent; however, 1358 * no ordering is guaranteed between messages sent by different tiles. 1359 * 1360 * Whenever the a client's message buffer is empty, the first message 1361 * subsequently received will cause the client's MESSAGE_RCV_DWNCL 1362 * interrupt vector to be invoked through the interrupt downcall mechanism 1363 * (see the description of the hv_downcall_dispatch() routine for details 1364 * on downcalls). 1365 * 1366 * Another message-available downcall will not occur until a call to 1367 * this routine is made when the message buffer is empty, and a message 1368 * subsequently arrives. Note that such a downcall could occur while 1369 * this routine is executing. If the calling code does not wish this 1370 * to happen, it is recommended that this routine be called with the 1371 * INTCTRL_1 interrupt masked, or inside an interrupt critical section. 1372 * 1373 * msgstate is the value previously passed to hv_register_message_state(). 1374 * buf is the virtual address of the buffer into which the message will 1375 * be written; buflen is the length of the buffer. 1376 * 1377 * This routine returns an HV_RcvMsgInfo structure. The msglen member 1378 * of that structure is the length of the message received, zero if no 1379 * message is available, or HV_E2BIG if the message is too large for the 1380 * specified buffer. If the message is too large, it is not consumed, 1381 * and may be retrieved by a subsequent call to this routine specifying 1382 * a sufficiently large buffer. A buffer which is HV_MAX_MESSAGE_SIZE 1383 * bytes long is guaranteed to be able to receive any possible message. 1384 * 1385 * The source member of the HV_RcvMsgInfo structure describes the sender 1386 * of the message. For messages sent by another client tile via an 1387 * hv_send_message() call, this value is HV_MSG_TILE; for messages sent 1388 * as a result of a device interrupt, this value is HV_MSG_INTR. 1389 */ 1390 1391HV_RcvMsgInfo hv_receive_message(HV_MsgState msgstate, HV_VirtAddr buf, 1392 int buflen); 1393 1394 1395/** Start remaining tiles owned by this supervisor. Initially, only one tile 1396 * executes the client program; after it calls this service, the other tiles 1397 * are started. This allows the initial tile to do one-time configuration 1398 * of shared data structures without having to lock them against simultaneous 1399 * access. 1400 */ 1401void hv_start_all_tiles(void); 1402 1403 1404/** Open a hypervisor device. 1405 * 1406 * This service initializes an I/O device and its hypervisor driver software, 1407 * and makes it available for use. The open operation is per-device per-chip; 1408 * once it has been performed, the device handle returned may be used in other 1409 * device services calls made by any tile. 1410 * 1411 * @param name Name of the device. A base device name is just a text string 1412 * (say, "pcie"). If there is more than one instance of a device, the 1413 * base name is followed by a slash and a device number (say, "pcie/0"). 1414 * Some devices may support further structure beneath those components; 1415 * most notably, devices which require control operations do so by 1416 * supporting reads and/or writes to a control device whose name 1417 * includes a trailing "/ctl" (say, "pcie/0/ctl"). 1418 * @param flags Flags (HV_DEV_xxx). 1419 * @return A positive integer device handle, or a negative error code. 1420 */ 1421int hv_dev_open(HV_VirtAddr name, __hv32 flags); 1422 1423 1424/** Close a hypervisor device. 1425 * 1426 * This service uninitializes an I/O device and its hypervisor driver 1427 * software, and makes it unavailable for use. The close operation is 1428 * per-device per-chip; once it has been performed, the device is no longer 1429 * available. Normally there is no need to ever call the close service. 1430 * 1431 * @param devhdl Device handle of the device to be closed. 1432 * @return Zero if the close is successful, otherwise, a negative error code. 1433 */ 1434int hv_dev_close(int devhdl); 1435 1436 1437/** Read data from a hypervisor device synchronously. 1438 * 1439 * This service transfers data from a hypervisor device to a memory buffer. 1440 * When the service returns, the data has been written from the memory buffer, 1441 * and the buffer will not be further modified by the driver. 1442 * 1443 * No ordering is guaranteed between requests issued from different tiles. 1444 * 1445 * Devices may choose to support both the synchronous and asynchronous read 1446 * operations, only one of them, or neither of them. 1447 * 1448 * @param devhdl Device handle of the device to be read from. 1449 * @param flags Flags (HV_DEV_xxx). 1450 * @param va Virtual address of the target data buffer. This buffer must 1451 * be mapped in the currently installed page table; if not, HV_EFAULT 1452 * may be returned. 1453 * @param len Number of bytes to be transferred. 1454 * @param offset Driver-dependent offset. For a random-access device, this is 1455 * often a byte offset from the beginning of the device; in other cases, 1456 * like on a control device, it may have a different meaning. 1457 * @return A non-negative value if the read was at least partially successful; 1458 * otherwise, a negative error code. The precise interpretation of 1459 * the return value is driver-dependent, but many drivers will return 1460 * the number of bytes successfully transferred. 1461 */ 1462int hv_dev_pread(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len, 1463 __hv64 offset); 1464 1465#define HV_DEV_NB_EMPTY 0x1 /**< Don't block when no bytes of data can 1466 be transferred. */ 1467#define HV_DEV_NB_PARTIAL 0x2 /**< Don't block when some bytes, but not all 1468 of the requested bytes, can be 1469 transferred. */ 1470#define HV_DEV_NOCACHE 0x4 /**< The caller warrants that none of the 1471 cache lines which might contain data 1472 from the requested buffer are valid. 1473 Useful with asynchronous operations 1474 only. */ 1475 1476#define HV_DEV_ALLFLAGS (HV_DEV_NB_EMPTY | HV_DEV_NB_PARTIAL | \ 1477 HV_DEV_NOCACHE) /**< All HV_DEV_xxx flags */ 1478 1479/** Write data to a hypervisor device synchronously. 1480 * 1481 * This service transfers data from a memory buffer to a hypervisor device. 1482 * When the service returns, the data has been read from the memory buffer, 1483 * and the buffer may be overwritten by the client; the data may not 1484 * necessarily have been conveyed to the actual hardware I/O interface. 1485 * 1486 * No ordering is guaranteed between requests issued from different tiles. 1487 * 1488 * Devices may choose to support both the synchronous and asynchronous write 1489 * operations, only one of them, or neither of them. 1490 * 1491 * @param devhdl Device handle of the device to be written to. 1492 * @param flags Flags (HV_DEV_xxx). 1493 * @param va Virtual address of the source data buffer. This buffer must 1494 * be mapped in the currently installed page table; if not, HV_EFAULT 1495 * may be returned. 1496 * @param len Number of bytes to be transferred. 1497 * @param offset Driver-dependent offset. For a random-access device, this is 1498 * often a byte offset from the beginning of the device; in other cases, 1499 * like on a control device, it may have a different meaning. 1500 * @return A non-negative value if the write was at least partially successful; 1501 * otherwise, a negative error code. The precise interpretation of 1502 * the return value is driver-dependent, but many drivers will return 1503 * the number of bytes successfully transferred. 1504 */ 1505int hv_dev_pwrite(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len, 1506 __hv64 offset); 1507 1508 1509/** Interrupt arguments, used in the asynchronous I/O interfaces. */ 1510#if CHIP_VA_WIDTH() > 32 1511typedef __hv64 HV_IntArg; 1512#else 1513typedef __hv32 HV_IntArg; 1514#endif 1515 1516/** Interrupt messages are delivered via the mechanism as normal messages, 1517 * but have a message source of HV_DEV_INTR. The message is formatted 1518 * as an HV_IntrMsg structure. 1519 */ 1520 1521typedef struct 1522{ 1523 HV_IntArg intarg; /**< Interrupt argument, passed to the poll/preada/pwritea 1524 services */ 1525 HV_IntArg intdata; /**< Interrupt-specific interrupt data */ 1526} HV_IntrMsg; 1527 1528/** Request an interrupt message when a device condition is satisfied. 1529 * 1530 * This service requests that an interrupt message be delivered to the 1531 * requesting tile when a device becomes readable or writable, or when any 1532 * data queued to the device via previous write operations from this tile 1533 * has been actually sent out on the hardware I/O interface. Devices may 1534 * choose to support any, all, or none of the available conditions. 1535 * 1536 * If multiple conditions are specified, only one message will be 1537 * delivered. If the event mask delivered to that interrupt handler 1538 * indicates that some of the conditions have not yet occurred, the 1539 * client must issue another poll() call if it wishes to wait for those 1540 * conditions. 1541 * 1542 * Only one poll may be outstanding per device handle per tile. If more than 1543 * one tile is polling on the same device and condition, they will all be 1544 * notified when it happens. Because of this, clients may not assume that 1545 * the condition signaled is necessarily still true when they request a 1546 * subsequent service; for instance, the readable data which caused the 1547 * poll call to interrupt may have been read by another tile in the interim. 1548 * 1549 * The notification interrupt message could come directly, or via the 1550 * downcall (intctrl1) method, depending on what the tile is doing 1551 * when the condition is satisfied. Note that it is possible for the 1552 * requested interrupt to be delivered after this service is called but 1553 * before it returns. 1554 * 1555 * @param devhdl Device handle of the device to be polled. 1556 * @param events Flags denoting the events which will cause the interrupt to 1557 * be delivered (HV_DEVPOLL_xxx). 1558 * @param intarg Value which will be delivered as the intarg member of the 1559 * eventual interrupt message; the intdata member will be set to a 1560 * mask of HV_DEVPOLL_xxx values indicating which conditions have been 1561 * satisifed. 1562 * @return Zero if the interrupt was successfully scheduled; otherwise, a 1563 * negative error code. 1564 */ 1565int hv_dev_poll(int devhdl, __hv32 events, HV_IntArg intarg); 1566 1567#define HV_DEVPOLL_READ 0x1 /**< Test device for readability */ 1568#define HV_DEVPOLL_WRITE 0x2 /**< Test device for writability */ 1569#define HV_DEVPOLL_FLUSH 0x4 /**< Test device for output drained */ 1570 1571 1572/** Cancel a request for an interrupt when a device event occurs. 1573 * 1574 * This service requests that no interrupt be delivered when the events 1575 * noted in the last-issued poll() call happen. Once this service returns, 1576 * the interrupt has been canceled; however, it is possible for the interrupt 1577 * to be delivered after this service is called but before it returns. 1578 * 1579 * @param devhdl Device handle of the device on which to cancel polling. 1580 * @return Zero if the poll was successfully canceled; otherwise, a negative 1581 * error code. 1582 */ 1583int hv_dev_poll_cancel(int devhdl); 1584 1585 1586/** Scatter-gather list for preada/pwritea calls. */ 1587typedef struct 1588#if CHIP_VA_WIDTH() <= 32 1589__attribute__ ((packed, aligned(4))) 1590#endif 1591{ 1592 HV_PhysAddr pa; /**< Client physical address of the buffer segment. */ 1593 HV_PTE pte; /**< Page table entry describing the caching and location 1594 override characteristics of the buffer segment. Some 1595 drivers ignore this element and will require that 1596 the NOCACHE flag be set on their requests. */ 1597 __hv32 len; /**< Length of the buffer segment. */ 1598} HV_SGL; 1599 1600#define HV_SGL_MAXLEN 16 /**< Maximum number of entries in a scatter-gather 1601 list */ 1602 1603/** Read data from a hypervisor device asynchronously. 1604 * 1605 * This service transfers data from a hypervisor device to a memory buffer. 1606 * When the service returns, the read has been scheduled. When the read 1607 * completes, an interrupt message will be delivered, and the buffer will 1608 * not be further modified by the driver. 1609 * 1610 * The number of possible outstanding asynchronous requests is defined by 1611 * each driver, but it is recommended that it be at least two requests 1612 * per tile per device. 1613 * 1614 * No ordering is guaranteed between synchronous and asynchronous requests, 1615 * even those issued on the same tile. 1616 * 1617 * The completion interrupt message could come directly, or via the downcall 1618 * (intctrl1) method, depending on what the tile is doing when the read 1619 * completes. Interrupts do not coalesce; one is delivered for each 1620 * asynchronous I/O request. Note that it is possible for the requested 1621 * interrupt to be delivered after this service is called but before it 1622 * returns. 1623 * 1624 * Devices may choose to support both the synchronous and asynchronous read 1625 * operations, only one of them, or neither of them. 1626 * 1627 * @param devhdl Device handle of the device to be read from. 1628 * @param flags Flags (HV_DEV_xxx). 1629 * @param sgl_len Number of elements in the scatter-gather list. 1630 * @param sgl Scatter-gather list describing the memory to which data will be 1631 * written. 1632 * @param offset Driver-dependent offset. For a random-access device, this is 1633 * often a byte offset from the beginning of the device; in other cases, 1634 * like on a control device, it may have a different meaning. 1635 * @param intarg Value which will be delivered as the intarg member of the 1636 * eventual interrupt message; the intdata member will be set to the 1637 * normal return value from the read request. 1638 * @return Zero if the read was successfully scheduled; otherwise, a negative 1639 * error code. Note that some drivers may choose to pre-validate 1640 * their arguments, and may thus detect certain device error 1641 * conditions at this time rather than when the completion notification 1642 * occurs, but this is not required. 1643 */ 1644int hv_dev_preada(int devhdl, __hv32 flags, __hv32 sgl_len, 1645 HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg); 1646 1647 1648/** Write data to a hypervisor device asynchronously. 1649 * 1650 * This service transfers data from a memory buffer to a hypervisor 1651 * device. When the service returns, the write has been scheduled. 1652 * When the write completes, an interrupt message will be delivered, 1653 * and the buffer may be overwritten by the client; the data may not 1654 * necessarily have been conveyed to the actual hardware I/O interface. 1655 * 1656 * The number of possible outstanding asynchronous requests is defined by 1657 * each driver, but it is recommended that it be at least two requests 1658 * per tile per device. 1659 * 1660 * No ordering is guaranteed between synchronous and asynchronous requests, 1661 * even those issued on the same tile. 1662 * 1663 * The completion interrupt message could come directly, or via the downcall 1664 * (intctrl1) method, depending on what the tile is doing when the read 1665 * completes. Interrupts do not coalesce; one is delivered for each 1666 * asynchronous I/O request. Note that it is possible for the requested 1667 * interrupt to be delivered after this service is called but before it 1668 * returns. 1669 * 1670 * Devices may choose to support both the synchronous and asynchronous write 1671 * operations, only one of them, or neither of them. 1672 * 1673 * @param devhdl Device handle of the device to be read from. 1674 * @param flags Flags (HV_DEV_xxx). 1675 * @param sgl_len Number of elements in the scatter-gather list. 1676 * @param sgl Scatter-gather list describing the memory from which data will be 1677 * read. 1678 * @param offset Driver-dependent offset. For a random-access device, this is 1679 * often a byte offset from the beginning of the device; in other cases, 1680 * like on a control device, it may have a different meaning. 1681 * @param intarg Value which will be delivered as the intarg member of the 1682 * eventual interrupt message; the intdata member will be set to the 1683 * normal return value from the write request. 1684 * @return Zero if the write was successfully scheduled; otherwise, a negative 1685 * error code. Note that some drivers may choose to pre-validate 1686 * their arguments, and may thus detect certain device error 1687 * conditions at this time rather than when the completion notification 1688 * occurs, but this is not required. 1689 */ 1690int hv_dev_pwritea(int devhdl, __hv32 flags, __hv32 sgl_len, 1691 HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg); 1692 1693 1694/** Define a pair of tile and ASID to identify a user process context. */ 1695typedef struct 1696{ 1697 /** X coordinate, relative to supervisor's top-left coordinate */ 1698 unsigned int x:11; 1699 1700 /** Y coordinate, relative to supervisor's top-left coordinate */ 1701 unsigned int y:11; 1702 1703 /** ASID of the process on this x,y tile */ 1704 HV_ASID asid:10; 1705} HV_Remote_ASID; 1706 1707/** Flush cache and/or TLB state on remote tiles. 1708 * 1709 * @param cache_pa Client physical address to flush from cache (ignored if 1710 * the length encoded in cache_control is zero, or if 1711 * HV_FLUSH_EVICT_L2 is set, or if cache_cpumask is NULL). 1712 * @param cache_control This argument allows you to specify a length of 1713 * physical address space to flush (maximum HV_FLUSH_MAX_CACHE_LEN). 1714 * You can "or" in HV_FLUSH_EVICT_L2 to flush the whole L2 cache. 1715 * You can "or" in HV_FLUSH_EVICT_L1I to flush the whole L1I cache. 1716 * HV_FLUSH_ALL flushes all caches. 1717 * @param cache_cpumask Bitmask (in row-major order, supervisor-relative) of 1718 * tile indices to perform cache flush on. The low bit of the first 1719 * word corresponds to the tile at the upper left-hand corner of the 1720 * supervisor's rectangle. If passed as a NULL pointer, equivalent 1721 * to an empty bitmask. On chips which support hash-for-home caching, 1722 * if passed as -1, equivalent to a mask containing tiles which could 1723 * be doing hash-for-home caching. 1724 * @param tlb_va Virtual address to flush from TLB (ignored if 1725 * tlb_length is zero or tlb_cpumask is NULL). 1726 * @param tlb_length Number of bytes of data to flush from the TLB. 1727 * @param tlb_pgsize Page size to use for TLB flushes. 1728 * tlb_va and tlb_length need not be aligned to this size. 1729 * @param tlb_cpumask Bitmask for tlb flush, like cache_cpumask. 1730 * If passed as a NULL pointer, equivalent to an empty bitmask. 1731 * @param asids Pointer to an HV_Remote_ASID array of tile/ASID pairs to flush. 1732 * @param asidcount Number of HV_Remote_ASID entries in asids[]. 1733 * @return Zero for success, or else HV_EINVAL or HV_EFAULT for errors that 1734 * are detected while parsing the arguments. 1735 */ 1736int hv_flush_remote(HV_PhysAddr cache_pa, unsigned long cache_control, 1737 unsigned long* cache_cpumask, 1738 HV_VirtAddr tlb_va, unsigned long tlb_length, 1739 unsigned long tlb_pgsize, unsigned long* tlb_cpumask, 1740 HV_Remote_ASID* asids, int asidcount); 1741 1742/** Include in cache_control to ensure a flush of the entire L2. */ 1743#define HV_FLUSH_EVICT_L2 (1UL << 31) 1744 1745/** Include in cache_control to ensure a flush of the entire L1I. */ 1746#define HV_FLUSH_EVICT_L1I (1UL << 30) 1747 1748/** Maximum legal size to use for the "length" component of cache_control. */ 1749#define HV_FLUSH_MAX_CACHE_LEN ((1UL << 30) - 1) 1750 1751/** Use for cache_control to ensure a flush of all caches. */ 1752#define HV_FLUSH_ALL -1UL 1753 1754#else /* __ASSEMBLER__ */ 1755 1756/** Include in cache_control to ensure a flush of the entire L2. */ 1757#define HV_FLUSH_EVICT_L2 (1 << 31) 1758 1759/** Include in cache_control to ensure a flush of the entire L1I. */ 1760#define HV_FLUSH_EVICT_L1I (1 << 30) 1761 1762/** Maximum legal size to use for the "length" component of cache_control. */ 1763#define HV_FLUSH_MAX_CACHE_LEN ((1 << 30) - 1) 1764 1765/** Use for cache_control to ensure a flush of all caches. */ 1766#define HV_FLUSH_ALL -1 1767 1768#endif /* __ASSEMBLER__ */ 1769 1770#ifndef __ASSEMBLER__ 1771 1772/** Return a 64-bit value corresponding to the PTE if needed */ 1773#define hv_pte_val(pte) ((pte).val) 1774 1775/** Cast a 64-bit value to an HV_PTE */ 1776#define hv_pte(val) ((HV_PTE) { val }) 1777 1778#endif /* !__ASSEMBLER__ */ 1779 1780 1781/** Bits in the size of an HV_PTE */ 1782#define HV_LOG2_PTE_SIZE 3 1783 1784/** Size of an HV_PTE */ 1785#define HV_PTE_SIZE (1 << HV_LOG2_PTE_SIZE) 1786 1787 1788/* Bits in HV_PTE's low word. */ 1789#define HV_PTE_INDEX_PRESENT 0 /**< PTE is valid */ 1790#define HV_PTE_INDEX_MIGRATING 1 /**< Page is migrating */ 1791#define HV_PTE_INDEX_CLIENT0 2 /**< Page client state 0 */ 1792#define HV_PTE_INDEX_CLIENT1 3 /**< Page client state 1 */ 1793#define HV_PTE_INDEX_NC 4 /**< L1$/L2$ incoherent with L3$ */ 1794#define HV_PTE_INDEX_NO_ALLOC_L1 5 /**< Page is uncached in local L1$ */ 1795#define HV_PTE_INDEX_NO_ALLOC_L2 6 /**< Page is uncached in local L2$ */ 1796#define HV_PTE_INDEX_CACHED_PRIORITY 7 /**< Page is priority cached */ 1797#define HV_PTE_INDEX_PAGE 8 /**< PTE describes a page */ 1798#define HV_PTE_INDEX_GLOBAL 9 /**< Page is global */ 1799#define HV_PTE_INDEX_USER 10 /**< Page is user-accessible */ 1800#define HV_PTE_INDEX_ACCESSED 11 /**< Page has been accessed */ 1801#define HV_PTE_INDEX_DIRTY 12 /**< Page has been written */ 1802 /* Bits 13-15 are reserved for 1803 future use. */ 1804#define HV_PTE_INDEX_MODE 16 /**< Page mode; see HV_PTE_MODE_xxx */ 1805#define HV_PTE_MODE_BITS 3 /**< Number of bits in mode */ 1806 /* Bit 19 is reserved for 1807 future use. */ 1808#define HV_PTE_INDEX_LOTAR 20 /**< Page's LOTAR; must be high bits 1809 of word */ 1810#define HV_PTE_LOTAR_BITS 12 /**< Number of bits in a LOTAR */ 1811 1812/* Bits in HV_PTE's high word. */ 1813#define HV_PTE_INDEX_READABLE 32 /**< Page is readable */ 1814#define HV_PTE_INDEX_WRITABLE 33 /**< Page is writable */ 1815#define HV_PTE_INDEX_EXECUTABLE 34 /**< Page is executable */ 1816#define HV_PTE_INDEX_PTFN 35 /**< Page's PTFN; must be high bits 1817 of word */ 1818#define HV_PTE_PTFN_BITS 29 /**< Number of bits in a PTFN */ 1819 1820/** Position of the PFN field within the PTE (subset of the PTFN). */ 1821#define HV_PTE_INDEX_PFN (HV_PTE_INDEX_PTFN + (HV_LOG2_PAGE_SIZE_SMALL - \ 1822 HV_LOG2_PAGE_TABLE_ALIGN)) 1823 1824/** Length of the PFN field within the PTE (subset of the PTFN). */ 1825#define HV_PTE_INDEX_PFN_BITS (HV_PTE_INDEX_PTFN_BITS - \ 1826 (HV_LOG2_PAGE_SIZE_SMALL - \ 1827 HV_LOG2_PAGE_TABLE_ALIGN)) 1828 1829/* 1830 * Legal values for the PTE's mode field 1831 */ 1832/** Data is not resident in any caches; loads and stores access memory 1833 * directly. 1834 */ 1835#define HV_PTE_MODE_UNCACHED 1 1836 1837/** Data is resident in the tile's local L1 and/or L2 caches; if a load 1838 * or store misses there, it goes to memory. 1839 * 1840 * The copy in the local L1$/L2$ is not invalidated when the copy in 1841 * memory is changed. 1842 */ 1843#define HV_PTE_MODE_CACHE_NO_L3 2 1844 1845/** Data is resident in the tile's local L1 and/or L2 caches. If a load 1846 * or store misses there, it goes to an L3 cache in a designated tile; 1847 * if it misses there, it goes to memory. 1848 * 1849 * If the NC bit is not set, the copy in the local L1$/L2$ is invalidated 1850 * when the copy in the remote L3$ is changed. Otherwise, such 1851 * invalidation will not occur. 1852 * 1853 * Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support 1854 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is 1855 * clear on such a chip, no copy is kept in the local L1$/L2$ in this mode. 1856 */ 1857#define HV_PTE_MODE_CACHE_TILE_L3 3 1858 1859/** Data is resident in the tile's local L1 and/or L2 caches. If a load 1860 * or store misses there, it goes to an L3 cache in one of a set of 1861 * designated tiles; if it misses there, it goes to memory. Which tile 1862 * is chosen from the set depends upon a hash function applied to the 1863 * physical address. This mode is not supported on chips for which 1864 * CHIP_HAS_CBOX_HOME_MAP() is 0. 1865 * 1866 * If the NC bit is not set, the copy in the local L1$/L2$ is invalidated 1867 * when the copy in the remote L3$ is changed. Otherwise, such 1868 * invalidation will not occur. 1869 * 1870 * Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support 1871 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is 1872 * clear on such a chip, no copy is kept in the local L1$/L2$ in this mode. 1873 */ 1874#define HV_PTE_MODE_CACHE_HASH_L3 4 1875 1876/** Data is not resident in memory; accesses are instead made to an I/O 1877 * device, whose tile coordinates are given by the PTE's LOTAR field. 1878 * This mode is only supported on chips for which CHIP_HAS_MMIO() is 1. 1879 * The EXECUTABLE bit may not be set in an MMIO PTE. 1880 */ 1881#define HV_PTE_MODE_MMIO 5 1882 1883 1884/* C wants 1ULL so it is typed as __hv64, but the assembler needs just numbers. 1885 * The assembler can't handle shifts greater than 31, but treats them 1886 * as shifts mod 32, so assembler code must be aware of which word 1887 * the bit belongs in when using these macros. 1888 */ 1889#ifdef __ASSEMBLER__ 1890#define __HV_PTE_ONE 1 /**< One, for assembler */ 1891#else 1892#define __HV_PTE_ONE 1ULL /**< One, for C */ 1893#endif 1894 1895/** Is this PTE present? 1896 * 1897 * If this bit is set, this PTE represents a valid translation or level-2 1898 * page table pointer. Otherwise, the page table does not contain a 1899 * translation for the subject virtual pages. 1900 * 1901 * If this bit is not set, the other bits in the PTE are not 1902 * interpreted by the hypervisor, and may contain any value. 1903 */ 1904#define HV_PTE_PRESENT (__HV_PTE_ONE << HV_PTE_INDEX_PRESENT) 1905 1906/** Does this PTE map a page? 1907 * 1908 * If this bit is set in the level-1 page table, the entry should be 1909 * interpreted as a level-2 page table entry mapping a large page. 1910 * 1911 * This bit should not be modified by the client while PRESENT is set, as 1912 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits. 1913 * 1914 * In a level-2 page table, this bit is ignored and must be zero. 1915 */ 1916#define HV_PTE_PAGE (__HV_PTE_ONE << HV_PTE_INDEX_PAGE) 1917 1918/** Is this a global (non-ASID) mapping? 1919 * 1920 * If this bit is set, the translations established by this PTE will 1921 * not be flushed from the TLB by the hv_flush_asid() service; they 1922 * will be flushed by the hv_flush_page() or hv_flush_pages() services. 1923 * 1924 * Setting this bit for translations which are identical in all page 1925 * tables (for instance, code and data belonging to a client OS) can 1926 * be very beneficial, as it will reduce the number of TLB misses. 1927 * Note that, while it is not an error which will be detected by the 1928 * hypervisor, it is an extremely bad idea to set this bit for 1929 * translations which are _not_ identical in all page tables. 1930 * 1931 * This bit should not be modified by the client while PRESENT is set, as 1932 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits. 1933 * 1934 * This bit is ignored in level-1 PTEs unless the Page bit is set. 1935 */ 1936#define HV_PTE_GLOBAL (__HV_PTE_ONE << HV_PTE_INDEX_GLOBAL) 1937 1938/** Is this mapping accessible to users? 1939 * 1940 * If this bit is set, code running at any PL will be permitted to 1941 * access the virtual addresses mapped by this PTE. Otherwise, only 1942 * code running at PL 1 or above will be allowed to do so. 1943 * 1944 * This bit should not be modified by the client while PRESENT is set, as 1945 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits. 1946 * 1947 * This bit is ignored in level-1 PTEs unless the Page bit is set. 1948 */ 1949#define HV_PTE_USER (__HV_PTE_ONE << HV_PTE_INDEX_USER) 1950 1951/** Has this mapping been accessed? 1952 * 1953 * This bit is set by the hypervisor when the memory described by the 1954 * translation is accessed for the first time. It is never cleared by 1955 * the hypervisor, but may be cleared by the client. After the bit 1956 * has been cleared, subsequent references are not guaranteed to set 1957 * it again until the translation has been flushed from the TLB. 1958 * 1959 * This bit is ignored in level-1 PTEs unless the Page bit is set. 1960 */ 1961#define HV_PTE_ACCESSED (__HV_PTE_ONE << HV_PTE_INDEX_ACCESSED) 1962 1963/** Is this mapping dirty? 1964 * 1965 * This bit is set by the hypervisor when the memory described by the 1966 * translation is written for the first time. It is never cleared by 1967 * the hypervisor, but may be cleared by the client. After the bit 1968 * has been cleared, subsequent references are not guaranteed to set 1969 * it again until the translation has been flushed from the TLB. 1970 * 1971 * This bit is ignored in level-1 PTEs unless the Page bit is set. 1972 */ 1973#define HV_PTE_DIRTY (__HV_PTE_ONE << HV_PTE_INDEX_DIRTY) 1974 1975/** Migrating bit in PTE. 1976 * 1977 * This bit is guaranteed not to be inspected or modified by the 1978 * hypervisor. The name is indicative of the suggested use by the client 1979 * to tag pages whose L3 cache is being migrated from one cpu to another. 1980 */ 1981#define HV_PTE_MIGRATING (__HV_PTE_ONE << HV_PTE_INDEX_MIGRATING) 1982 1983/** Client-private bit in PTE. 1984 * 1985 * This bit is guaranteed not to be inspected or modified by the 1986 * hypervisor. 1987 */ 1988#define HV_PTE_CLIENT0 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT0) 1989 1990/** Client-private bit in PTE. 1991 * 1992 * This bit is guaranteed not to be inspected or modified by the 1993 * hypervisor. 1994 */ 1995#define HV_PTE_CLIENT1 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT1) 1996 1997/** Non-coherent (NC) bit in PTE. 1998 * 1999 * If this bit is set, the mapping that is set up will be non-coherent 2000 * (also known as non-inclusive). This means that changes to the L3 2001 * cache will not cause a local copy to be invalidated. It is generally 2002 * recommended only for read-only mappings. 2003 * 2004 * In level-1 PTEs, if the Page bit is clear, this bit determines how the 2005 * level-2 page table is accessed. 2006 */ 2007#define HV_PTE_NC (__HV_PTE_ONE << HV_PTE_INDEX_NC) 2008 2009/** Is this page prevented from filling the L1$? 2010 * 2011 * If this bit is set, the page described by the PTE will not be cached 2012 * the local cpu's L1 cache. 2013 * 2014 * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip, 2015 * it is illegal to use this attribute, and may cause client termination. 2016 * 2017 * In level-1 PTEs, if the Page bit is clear, this bit 2018 * determines how the level-2 page table is accessed. 2019 */ 2020#define HV_PTE_NO_ALLOC_L1 (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L1) 2021 2022/** Is this page prevented from filling the L2$? 2023 * 2024 * If this bit is set, the page described by the PTE will not be cached 2025 * the local cpu's L2 cache. 2026 * 2027 * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip, 2028 * it is illegal to use this attribute, and may cause client termination. 2029 * 2030 * In level-1 PTEs, if the Page bit is clear, this bit determines how the 2031 * level-2 page table is accessed. 2032 */ 2033#define HV_PTE_NO_ALLOC_L2 (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L2) 2034 2035/** Is this a priority page? 2036 * 2037 * If this bit is set, the page described by the PTE will be given 2038 * priority in the cache. Normally this translates into allowing the 2039 * page to use only the "red" half of the cache. The client may wish to 2040 * then use the hv_set_caching service to specify that other pages which 2041 * alias this page will use only the "black" half of the cache. 2042 * 2043 * If the Cached Priority bit is clear, the hypervisor uses the 2044 * current hv_set_caching() value to choose how to cache the page. 2045 * 2046 * It is illegal to set the Cached Priority bit if the Non-Cached bit 2047 * is set and the Cached Remotely bit is clear, i.e. if requests to 2048 * the page map directly to memory. 2049 * 2050 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2051 */ 2052#define HV_PTE_CACHED_PRIORITY (__HV_PTE_ONE << \ 2053 HV_PTE_INDEX_CACHED_PRIORITY) 2054 2055/** Is this a readable mapping? 2056 * 2057 * If this bit is set, code will be permitted to read from (e.g., 2058 * issue load instructions against) the virtual addresses mapped by 2059 * this PTE. 2060 * 2061 * It is illegal for this bit to be clear if the Writable bit is set. 2062 * 2063 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2064 */ 2065#define HV_PTE_READABLE (__HV_PTE_ONE << HV_PTE_INDEX_READABLE) 2066 2067/** Is this a writable mapping? 2068 * 2069 * If this bit is set, code will be permitted to write to (e.g., issue 2070 * store instructions against) the virtual addresses mapped by this 2071 * PTE. 2072 * 2073 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2074 */ 2075#define HV_PTE_WRITABLE (__HV_PTE_ONE << HV_PTE_INDEX_WRITABLE) 2076 2077/** Is this an executable mapping? 2078 * 2079 * If this bit is set, code will be permitted to execute from 2080 * (e.g., jump to) the virtual addresses mapped by this PTE. 2081 * 2082 * This bit applies to any processor on the tile, if there are more 2083 * than one. 2084 * 2085 * This bit is ignored in level-1 PTEs unless the Page bit is set. 2086 */ 2087#define HV_PTE_EXECUTABLE (__HV_PTE_ONE << HV_PTE_INDEX_EXECUTABLE) 2088 2089/** The width of a LOTAR's x or y bitfield. */ 2090#define HV_LOTAR_WIDTH 11 2091 2092/** Converts an x,y pair to a LOTAR value. */ 2093#define HV_XY_TO_LOTAR(x, y) ((HV_LOTAR)(((x) << HV_LOTAR_WIDTH) | (y))) 2094 2095/** Extracts the X component of a lotar. */ 2096#define HV_LOTAR_X(lotar) ((lotar) >> HV_LOTAR_WIDTH) 2097 2098/** Extracts the Y component of a lotar. */ 2099#define HV_LOTAR_Y(lotar) ((lotar) & ((1 << HV_LOTAR_WIDTH) - 1)) 2100 2101#ifndef __ASSEMBLER__ 2102 2103/** Define accessor functions for a PTE bit. */ 2104#define _HV_BIT(name, bit) \ 2105static __inline int \ 2106hv_pte_get_##name(HV_PTE pte) \ 2107{ \ 2108 return (pte.val >> HV_PTE_INDEX_##bit) & 1; \ 2109} \ 2110 \ 2111static __inline HV_PTE \ 2112hv_pte_set_##name(HV_PTE pte) \ 2113{ \ 2114 pte.val |= 1ULL << HV_PTE_INDEX_##bit; \ 2115 return pte; \ 2116} \ 2117 \ 2118static __inline HV_PTE \ 2119hv_pte_clear_##name(HV_PTE pte) \ 2120{ \ 2121 pte.val &= ~(1ULL << HV_PTE_INDEX_##bit); \ 2122 return pte; \ 2123} 2124 2125/* Generate accessors to get, set, and clear various PTE flags. 2126 */ 2127_HV_BIT(present, PRESENT) 2128_HV_BIT(page, PAGE) 2129_HV_BIT(client0, CLIENT0) 2130_HV_BIT(client1, CLIENT1) 2131_HV_BIT(migrating, MIGRATING) 2132_HV_BIT(nc, NC) 2133_HV_BIT(readable, READABLE) 2134_HV_BIT(writable, WRITABLE) 2135_HV_BIT(executable, EXECUTABLE) 2136_HV_BIT(accessed, ACCESSED) 2137_HV_BIT(dirty, DIRTY) 2138_HV_BIT(no_alloc_l1, NO_ALLOC_L1) 2139_HV_BIT(no_alloc_l2, NO_ALLOC_L2) 2140_HV_BIT(cached_priority, CACHED_PRIORITY) 2141_HV_BIT(global, GLOBAL) 2142_HV_BIT(user, USER) 2143 2144#undef _HV_BIT 2145 2146/** Get the page mode from the PTE. 2147 * 2148 * This field generally determines whether and how accesses to the page 2149 * are cached; the HV_PTE_MODE_xxx symbols define the legal values for the 2150 * page mode. The NC, NO_ALLOC_L1, and NO_ALLOC_L2 bits modify this 2151 * general policy. 2152 */ 2153static __inline unsigned int 2154hv_pte_get_mode(const HV_PTE pte) 2155{ 2156 return (((__hv32) pte.val) >> HV_PTE_INDEX_MODE) & 2157 ((1 << HV_PTE_MODE_BITS) - 1); 2158} 2159 2160/** Set the page mode into a PTE. See hv_pte_get_mode. */ 2161static __inline HV_PTE 2162hv_pte_set_mode(HV_PTE pte, unsigned int val) 2163{ 2164 pte.val &= ~(((1ULL << HV_PTE_MODE_BITS) - 1) << HV_PTE_INDEX_MODE); 2165 pte.val |= val << HV_PTE_INDEX_MODE; 2166 return pte; 2167} 2168 2169/** Get the page frame number from the PTE. 2170 * 2171 * This field contains the upper bits of the CPA (client physical 2172 * address) of the target page; the complete CPA is this field with 2173 * HV_LOG2_PAGE_SIZE_SMALL zero bits appended to it. 2174 * 2175 * For PTEs in a level-1 page table where the Page bit is set, the 2176 * CPA must be aligned modulo the large page size. 2177 */ 2178static __inline unsigned int 2179hv_pte_get_pfn(const HV_PTE pte) 2180{ 2181 return pte.val >> HV_PTE_INDEX_PFN; 2182} 2183 2184 2185/** Set the page frame number into a PTE. See hv_pte_get_pfn. */ 2186static __inline HV_PTE 2187hv_pte_set_pfn(HV_PTE pte, unsigned int val) 2188{ 2189 /* 2190 * Note that the use of "PTFN" in the next line is intentional; we 2191 * don't want any garbage lower bits left in that field. 2192 */ 2193 pte.val &= ~(((1ULL << HV_PTE_PTFN_BITS) - 1) << HV_PTE_INDEX_PTFN); 2194 pte.val |= (__hv64) val << HV_PTE_INDEX_PFN; 2195 return pte; 2196} 2197 2198/** Get the page table frame number from the PTE. 2199 * 2200 * This field contains the upper bits of the CPA (client physical 2201 * address) of the target page table; the complete CPA is this field with 2202 * with HV_PAGE_TABLE_ALIGN zero bits appended to it. 2203 * 2204 * For PTEs in a level-1 page table when the Page bit is not set, the 2205 * CPA must be aligned modulo the sticter of HV_PAGE_TABLE_ALIGN and 2206 * the level-2 page table size. 2207 */ 2208static __inline unsigned long 2209hv_pte_get_ptfn(const HV_PTE pte) 2210{ 2211 return pte.val >> HV_PTE_INDEX_PTFN; 2212} 2213 2214 2215/** Set the page table frame number into a PTE. See hv_pte_get_ptfn. */ 2216static __inline HV_PTE 2217hv_pte_set_ptfn(HV_PTE pte, unsigned long val) 2218{ 2219 pte.val &= ~(((1ULL << HV_PTE_PTFN_BITS)-1) << HV_PTE_INDEX_PTFN); 2220 pte.val |= (__hv64) val << HV_PTE_INDEX_PTFN; 2221 return pte; 2222} 2223 2224 2225/** Get the remote tile caching this page. 2226 * 2227 * Specifies the remote tile which is providing the L3 cache for this page. 2228 * 2229 * This field is ignored unless the page mode is HV_PTE_MODE_CACHE_TILE_L3. 2230 * 2231 * In level-1 PTEs, if the Page bit is clear, this field determines how the 2232 * level-2 page table is accessed. 2233 */ 2234static __inline unsigned int 2235hv_pte_get_lotar(const HV_PTE pte) 2236{ 2237 unsigned int lotar = ((__hv32) pte.val) >> HV_PTE_INDEX_LOTAR; 2238 2239 return HV_XY_TO_LOTAR( (lotar >> (HV_PTE_LOTAR_BITS / 2)), 2240 (lotar & ((1 << (HV_PTE_LOTAR_BITS / 2)) - 1)) ); 2241} 2242 2243 2244/** Set the remote tile caching a page into a PTE. See hv_pte_get_lotar. */ 2245static __inline HV_PTE 2246hv_pte_set_lotar(HV_PTE pte, unsigned int val) 2247{ 2248 unsigned int x = HV_LOTAR_X(val); 2249 unsigned int y = HV_LOTAR_Y(val); 2250 2251 pte.val &= ~(((1ULL << HV_PTE_LOTAR_BITS)-1) << HV_PTE_INDEX_LOTAR); 2252 pte.val |= (x << (HV_PTE_INDEX_LOTAR + HV_PTE_LOTAR_BITS / 2)) | 2253 (y << HV_PTE_INDEX_LOTAR); 2254 return pte; 2255} 2256 2257#endif /* !__ASSEMBLER__ */ 2258 2259/** Converts a client physical address to a pfn. */ 2260#define HV_CPA_TO_PFN(p) ((p) >> HV_LOG2_PAGE_SIZE_SMALL) 2261 2262/** Converts a pfn to a client physical address. */ 2263#define HV_PFN_TO_CPA(p) (((HV_PhysAddr)(p)) << HV_LOG2_PAGE_SIZE_SMALL) 2264 2265/** Converts a client physical address to a ptfn. */ 2266#define HV_CPA_TO_PTFN(p) ((p) >> HV_LOG2_PAGE_TABLE_ALIGN) 2267 2268/** Converts a ptfn to a client physical address. */ 2269#define HV_PTFN_TO_CPA(p) (((HV_PhysAddr)(p)) << HV_LOG2_PAGE_TABLE_ALIGN) 2270 2271/** Converts a ptfn to a pfn. */ 2272#define HV_PTFN_TO_PFN(p) \ 2273 ((p) >> (HV_LOG2_PAGE_SIZE_SMALL - HV_LOG2_PAGE_TABLE_ALIGN)) 2274 2275/** Converts a pfn to a ptfn. */ 2276#define HV_PFN_TO_PTFN(p) \ 2277 ((p) << (HV_LOG2_PAGE_SIZE_SMALL - HV_LOG2_PAGE_TABLE_ALIGN)) 2278 2279#if CHIP_VA_WIDTH() > 32 2280 2281/** Log number of HV_PTE entries in L0 page table */ 2282#define HV_LOG2_L0_ENTRIES (CHIP_VA_WIDTH() - HV_LOG2_L1_SPAN) 2283 2284/** Number of HV_PTE entries in L0 page table */ 2285#define HV_L0_ENTRIES (1 << HV_LOG2_L0_ENTRIES) 2286 2287/** Log size of L0 page table in bytes */ 2288#define HV_LOG2_L0_SIZE (HV_LOG2_PTE_SIZE + HV_LOG2_L0_ENTRIES) 2289 2290/** Size of L0 page table in bytes */ 2291#define HV_L0_SIZE (1 << HV_LOG2_L0_SIZE) 2292 2293#ifdef __ASSEMBLER__ 2294 2295/** Index in L0 for a specific VA */ 2296#define HV_L0_INDEX(va) \ 2297 (((va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1)) 2298 2299#else 2300 2301/** Index in L1 for a specific VA */ 2302#define HV_L0_INDEX(va) \ 2303 (((HV_VirtAddr)(va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1)) 2304 2305#endif 2306 2307#endif /* CHIP_VA_WIDTH() > 32 */ 2308 2309/** Log number of HV_PTE entries in L1 page table */ 2310#define HV_LOG2_L1_ENTRIES (HV_LOG2_L1_SPAN - HV_LOG2_PAGE_SIZE_LARGE) 2311 2312/** Number of HV_PTE entries in L1 page table */ 2313#define HV_L1_ENTRIES (1 << HV_LOG2_L1_ENTRIES) 2314 2315/** Log size of L1 page table in bytes */ 2316#define HV_LOG2_L1_SIZE (HV_LOG2_PTE_SIZE + HV_LOG2_L1_ENTRIES) 2317 2318/** Size of L1 page table in bytes */ 2319#define HV_L1_SIZE (1 << HV_LOG2_L1_SIZE) 2320 2321/** Log number of HV_PTE entries in level-2 page table */ 2322#define HV_LOG2_L2_ENTRIES (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL) 2323 2324/** Number of HV_PTE entries in level-2 page table */ 2325#define HV_L2_ENTRIES (1 << HV_LOG2_L2_ENTRIES) 2326 2327/** Log size of level-2 page table in bytes */ 2328#define HV_LOG2_L2_SIZE (HV_LOG2_PTE_SIZE + HV_LOG2_L2_ENTRIES) 2329 2330/** Size of level-2 page table in bytes */ 2331#define HV_L2_SIZE (1 << HV_LOG2_L2_SIZE) 2332 2333#ifdef __ASSEMBLER__ 2334 2335#if CHIP_VA_WIDTH() > 32 2336 2337/** Index in L1 for a specific VA */ 2338#define HV_L1_INDEX(va) \ 2339 (((va) >> HV_LOG2_PAGE_SIZE_LARGE) & (HV_L1_ENTRIES - 1)) 2340 2341#else /* CHIP_VA_WIDTH() > 32 */ 2342 2343/** Index in L1 for a specific VA */ 2344#define HV_L1_INDEX(va) \ 2345 (((va) >> HV_LOG2_PAGE_SIZE_LARGE)) 2346 2347#endif /* CHIP_VA_WIDTH() > 32 */ 2348 2349/** Index in level-2 page table for a specific VA */ 2350#define HV_L2_INDEX(va) \ 2351 (((va) >> HV_LOG2_PAGE_SIZE_SMALL) & (HV_L2_ENTRIES - 1)) 2352 2353#else /* __ASSEMBLER __ */ 2354 2355#if CHIP_VA_WIDTH() > 32 2356 2357/** Index in L1 for a specific VA */ 2358#define HV_L1_INDEX(va) \ 2359 (((HV_VirtAddr)(va) >> HV_LOG2_PAGE_SIZE_LARGE) & (HV_L1_ENTRIES - 1)) 2360 2361#else /* CHIP_VA_WIDTH() > 32 */ 2362 2363/** Index in L1 for a specific VA */ 2364#define HV_L1_INDEX(va) \ 2365 (((HV_VirtAddr)(va) >> HV_LOG2_PAGE_SIZE_LARGE)) 2366 2367#endif /* CHIP_VA_WIDTH() > 32 */ 2368 2369/** Index in level-2 page table for a specific VA */ 2370#define HV_L2_INDEX(va) \ 2371 (((HV_VirtAddr)(va) >> HV_LOG2_PAGE_SIZE_SMALL) & (HV_L2_ENTRIES - 1)) 2372 2373#endif /* __ASSEMBLER __ */ 2374 2375#endif /* _TILE_HV_H */ 2376