1/* pci_sabre.c: Sabre specific PCI controller support. 2 * 3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net) 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) 6 */ 7 8#include <linux/kernel.h> 9#include <linux/types.h> 10#include <linux/pci.h> 11#include <linux/init.h> 12#include <linux/slab.h> 13#include <linux/interrupt.h> 14#include <linux/of_device.h> 15 16#include <asm/apb.h> 17#include <asm/iommu.h> 18#include <asm/irq.h> 19#include <asm/prom.h> 20#include <asm/upa.h> 21 22#include "pci_impl.h" 23#include "iommu_common.h" 24#include "psycho_common.h" 25 26#define DRIVER_NAME "sabre" 27#define PFX DRIVER_NAME ": " 28 29/* SABRE PCI controller register offsets and definitions. */ 30#define SABRE_UE_AFSR 0x0030UL 31#define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ 32#define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ 33#define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ 34#define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ 35#define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */ 36#define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */ 37#define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ 38#define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */ 39#define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */ 40#define SABRE_UECE_AFAR 0x0038UL 41#define SABRE_CE_AFSR 0x0040UL 42#define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ 43#define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ 44#define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ 45#define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ 46#define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */ 47#define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ 48#define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */ 49#define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */ 50#define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */ 51#define SABRE_IOMMU_CONTROL 0x0200UL 52#define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */ 53#define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */ 54#define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */ 55#define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */ 56#define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ 57#define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000 58#define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000 59#define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000 60#define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000 61#define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000 62#define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000 63#define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000 64#define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000 65#define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */ 66#define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ 67#define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ 68#define SABRE_IOMMU_TSBBASE 0x0208UL 69#define SABRE_IOMMU_FLUSH 0x0210UL 70#define SABRE_IMAP_A_SLOT0 0x0c00UL 71#define SABRE_IMAP_B_SLOT0 0x0c20UL 72#define SABRE_IMAP_SCSI 0x1000UL 73#define SABRE_IMAP_ETH 0x1008UL 74#define SABRE_IMAP_BPP 0x1010UL 75#define SABRE_IMAP_AU_REC 0x1018UL 76#define SABRE_IMAP_AU_PLAY 0x1020UL 77#define SABRE_IMAP_PFAIL 0x1028UL 78#define SABRE_IMAP_KMS 0x1030UL 79#define SABRE_IMAP_FLPY 0x1038UL 80#define SABRE_IMAP_SHW 0x1040UL 81#define SABRE_IMAP_KBD 0x1048UL 82#define SABRE_IMAP_MS 0x1050UL 83#define SABRE_IMAP_SER 0x1058UL 84#define SABRE_IMAP_UE 0x1070UL 85#define SABRE_IMAP_CE 0x1078UL 86#define SABRE_IMAP_PCIERR 0x1080UL 87#define SABRE_IMAP_GFX 0x1098UL 88#define SABRE_IMAP_EUPA 0x10a0UL 89#define SABRE_ICLR_A_SLOT0 0x1400UL 90#define SABRE_ICLR_B_SLOT0 0x1480UL 91#define SABRE_ICLR_SCSI 0x1800UL 92#define SABRE_ICLR_ETH 0x1808UL 93#define SABRE_ICLR_BPP 0x1810UL 94#define SABRE_ICLR_AU_REC 0x1818UL 95#define SABRE_ICLR_AU_PLAY 0x1820UL 96#define SABRE_ICLR_PFAIL 0x1828UL 97#define SABRE_ICLR_KMS 0x1830UL 98#define SABRE_ICLR_FLPY 0x1838UL 99#define SABRE_ICLR_SHW 0x1840UL 100#define SABRE_ICLR_KBD 0x1848UL 101#define SABRE_ICLR_MS 0x1850UL 102#define SABRE_ICLR_SER 0x1858UL 103#define SABRE_ICLR_UE 0x1870UL 104#define SABRE_ICLR_CE 0x1878UL 105#define SABRE_ICLR_PCIERR 0x1880UL 106#define SABRE_WRSYNC 0x1c20UL 107#define SABRE_PCICTRL 0x2000UL 108#define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */ 109#define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */ 110#define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */ 111#define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */ 112#define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */ 113#define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */ 114#define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */ 115#define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */ 116#define SABRE_PIOAFSR 0x2010UL 117#define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */ 118#define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */ 119#define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */ 120#define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */ 121#define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */ 122#define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */ 123#define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */ 124#define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */ 125#define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */ 126#define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */ 127#define SABRE_PIOAFAR 0x2018UL 128#define SABRE_PCIDIAG 0x2020UL 129#define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */ 130#define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */ 131#define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */ 132#define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */ 133#define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */ 134#define SABRE_PCITASR 0x2028UL 135#define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */ 136#define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */ 137#define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */ 138#define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */ 139#define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */ 140#define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */ 141#define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */ 142#define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */ 143#define SABRE_PIOBUF_DIAG 0x5000UL 144#define SABRE_DMABUF_DIAGLO 0x5100UL 145#define SABRE_DMABUF_DIAGHI 0x51c0UL 146#define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */ 147#define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */ 148#define SABRE_IOMMU_VADIAG 0xa400UL 149#define SABRE_IOMMU_TCDIAG 0xa408UL 150#define SABRE_IOMMU_TAG 0xa580UL 151#define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */ 152#define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */ 153#define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */ 154#define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */ 155#define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */ 156#define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */ 157#define SABRE_IOMMU_DATA 0xa600UL 158#define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */ 159#define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */ 160#define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */ 161#define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */ 162#define SABRE_PCI_IRQSTATE 0xa800UL 163#define SABRE_OBIO_IRQSTATE 0xa808UL 164#define SABRE_FFBCFG 0xf000UL 165#define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */ 166#define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */ 167#define SABRE_MCCTRL0 0xf010UL 168#define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */ 169#define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */ 170#define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */ 171#define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */ 172#define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */ 173#define SABRE_MCCTRL1 0xf018UL 174#define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */ 175#define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */ 176#define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */ 177#define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */ 178#define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */ 179#define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */ 180#define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */ 181#define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */ 182#define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */ 183#define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */ 184#define SABRE_RESETCTRL 0xf020UL 185 186#define SABRE_CONFIGSPACE 0x001000000UL 187#define SABRE_IOSPACE 0x002000000UL 188#define SABRE_IOSPACE_SIZE 0x000ffffffUL 189#define SABRE_MEMSPACE 0x100000000UL 190#define SABRE_MEMSPACE_SIZE 0x07fffffffUL 191 192static int hummingbird_p; 193static struct pci_bus *sabre_root_bus; 194 195static irqreturn_t sabre_ue_intr(int irq, void *dev_id) 196{ 197 struct pci_pbm_info *pbm = dev_id; 198 unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR; 199 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR; 200 unsigned long afsr, afar, error_bits; 201 int reported; 202 203 /* Latch uncorrectable error status. */ 204 afar = upa_readq(afar_reg); 205 afsr = upa_readq(afsr_reg); 206 207 /* Clear the primary/secondary error status bits. */ 208 error_bits = afsr & 209 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | 210 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | 211 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE); 212 if (!error_bits) 213 return IRQ_NONE; 214 upa_writeq(error_bits, afsr_reg); 215 216 /* Log the error. */ 217 printk("%s: Uncorrectable Error, primary error type[%s%s]\n", 218 pbm->name, 219 ((error_bits & SABRE_UEAFSR_PDRD) ? 220 "DMA Read" : 221 ((error_bits & SABRE_UEAFSR_PDWR) ? 222 "DMA Write" : "???")), 223 ((error_bits & SABRE_UEAFSR_PDTE) ? 224 ":Translation Error" : "")); 225 printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n", 226 pbm->name, 227 (afsr & SABRE_UEAFSR_BMSK) >> 32UL, 228 (afsr & SABRE_UEAFSR_OFF) >> 29UL, 229 ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0)); 230 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); 231 printk("%s: UE Secondary errors [", pbm->name); 232 reported = 0; 233 if (afsr & SABRE_UEAFSR_SDRD) { 234 reported++; 235 printk("(DMA Read)"); 236 } 237 if (afsr & SABRE_UEAFSR_SDWR) { 238 reported++; 239 printk("(DMA Write)"); 240 } 241 if (afsr & SABRE_UEAFSR_SDTE) { 242 reported++; 243 printk("(Translation Error)"); 244 } 245 if (!reported) 246 printk("(none)"); 247 printk("]\n"); 248 249 /* Interrogate IOMMU for error status. */ 250 psycho_check_iommu_error(pbm, afsr, afar, UE_ERR); 251 252 return IRQ_HANDLED; 253} 254 255static irqreturn_t sabre_ce_intr(int irq, void *dev_id) 256{ 257 struct pci_pbm_info *pbm = dev_id; 258 unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR; 259 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR; 260 unsigned long afsr, afar, error_bits; 261 int reported; 262 263 /* Latch error status. */ 264 afar = upa_readq(afar_reg); 265 afsr = upa_readq(afsr_reg); 266 267 /* Clear primary/secondary error status bits. */ 268 error_bits = afsr & 269 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | 270 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR); 271 if (!error_bits) 272 return IRQ_NONE; 273 upa_writeq(error_bits, afsr_reg); 274 275 /* Log the error. */ 276 printk("%s: Correctable Error, primary error type[%s]\n", 277 pbm->name, 278 ((error_bits & SABRE_CEAFSR_PDRD) ? 279 "DMA Read" : 280 ((error_bits & SABRE_CEAFSR_PDWR) ? 281 "DMA Write" : "???"))); 282 283 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " 284 "was_block(%d)\n", 285 pbm->name, 286 (afsr & SABRE_CEAFSR_ESYND) >> 48UL, 287 (afsr & SABRE_CEAFSR_BMSK) >> 32UL, 288 (afsr & SABRE_CEAFSR_OFF) >> 29UL, 289 ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0)); 290 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); 291 printk("%s: CE Secondary errors [", pbm->name); 292 reported = 0; 293 if (afsr & SABRE_CEAFSR_SDRD) { 294 reported++; 295 printk("(DMA Read)"); 296 } 297 if (afsr & SABRE_CEAFSR_SDWR) { 298 reported++; 299 printk("(DMA Write)"); 300 } 301 if (!reported) 302 printk("(none)"); 303 printk("]\n"); 304 305 return IRQ_HANDLED; 306} 307 308static void sabre_register_error_handlers(struct pci_pbm_info *pbm) 309{ 310 struct device_node *dp = pbm->op->dev.of_node; 311 struct platform_device *op; 312 unsigned long base = pbm->controller_regs; 313 u64 tmp; 314 int err; 315 316 if (pbm->chip_type == PBM_CHIP_TYPE_SABRE) 317 dp = dp->parent; 318 319 op = of_find_device_by_node(dp); 320 if (!op) 321 return; 322 323 /* Sabre/Hummingbird IRQ property layout is: 324 * 0: PCI ERR 325 * 1: UE ERR 326 * 2: CE ERR 327 * 3: POWER FAIL 328 */ 329 if (op->archdata.num_irqs < 4) 330 return; 331 332 /* We clear the error bits in the appropriate AFSR before 333 * registering the handler so that we don't get spurious 334 * interrupts. 335 */ 336 upa_writeq((SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | 337 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | 338 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE), 339 base + SABRE_UE_AFSR); 340 341 err = request_irq(op->archdata.irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm); 342 if (err) 343 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n", 344 pbm->name, err); 345 346 upa_writeq((SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | 347 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR), 348 base + SABRE_CE_AFSR); 349 350 351 err = request_irq(op->archdata.irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm); 352 if (err) 353 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n", 354 pbm->name, err); 355 err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, 0, 356 "SABRE_PCIERR", pbm); 357 if (err) 358 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n", 359 pbm->name, err); 360 361 tmp = upa_readq(base + SABRE_PCICTRL); 362 tmp |= SABRE_PCICTRL_ERREN; 363 upa_writeq(tmp, base + SABRE_PCICTRL); 364} 365 366static void apb_init(struct pci_bus *sabre_bus) 367{ 368 struct pci_dev *pdev; 369 370 list_for_each_entry(pdev, &sabre_bus->devices, bus_list) { 371 if (pdev->vendor == PCI_VENDOR_ID_SUN && 372 pdev->device == PCI_DEVICE_ID_SUN_SIMBA) { 373 u16 word16; 374 375 pci_read_config_word(pdev, PCI_COMMAND, &word16); 376 word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | 377 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | 378 PCI_COMMAND_IO; 379 pci_write_config_word(pdev, PCI_COMMAND, word16); 380 381 /* Status register bits are "write 1 to clear". */ 382 pci_write_config_word(pdev, PCI_STATUS, 0xffff); 383 pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff); 384 385 /* Use a primary/seconday latency timer value 386 * of 64. 387 */ 388 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); 389 pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64); 390 391 /* Enable reporting/forwarding of master aborts, 392 * parity, and SERR. 393 */ 394 pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL, 395 (PCI_BRIDGE_CTL_PARITY | 396 PCI_BRIDGE_CTL_SERR | 397 PCI_BRIDGE_CTL_MASTER_ABORT)); 398 } 399 } 400} 401 402static void __devinit sabre_scan_bus(struct pci_pbm_info *pbm, 403 struct device *parent) 404{ 405 static int once; 406 407 /* The APB bridge speaks to the Sabre host PCI bridge 408 * at 66Mhz, but the front side of APB runs at 33Mhz 409 * for both segments. 410 * 411 * Hummingbird systems do not use APB, so they run 412 * at 66MHZ. 413 */ 414 if (hummingbird_p) 415 pbm->is_66mhz_capable = 1; 416 else 417 pbm->is_66mhz_capable = 0; 418 419 /* This driver has not been verified to handle 420 * multiple SABREs yet, so trap this. 421 * 422 * Also note that the SABRE host bridge is hardwired 423 * to live at bus 0. 424 */ 425 if (once != 0) { 426 printk(KERN_ERR PFX "Multiple controllers unsupported.\n"); 427 return; 428 } 429 once++; 430 431 pbm->pci_bus = pci_scan_one_pbm(pbm, parent); 432 if (!pbm->pci_bus) 433 return; 434 435 sabre_root_bus = pbm->pci_bus; 436 437 apb_init(pbm->pci_bus); 438 439 sabre_register_error_handlers(pbm); 440} 441 442static void __devinit sabre_pbm_init(struct pci_pbm_info *pbm, 443 struct platform_device *op) 444{ 445 psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE); 446 pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR; 447 pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR; 448 pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL; 449 sabre_scan_bus(pbm, &op->dev); 450} 451 452static int __devinit sabre_probe(struct platform_device *op, 453 const struct of_device_id *match) 454{ 455 const struct linux_prom64_registers *pr_regs; 456 struct device_node *dp = op->dev.of_node; 457 struct pci_pbm_info *pbm; 458 u32 upa_portid, dma_mask; 459 struct iommu *iommu; 460 int tsbsize, err; 461 const u32 *vdma; 462 u64 clear_irq; 463 464 hummingbird_p = (match->data != NULL); 465 if (!hummingbird_p) { 466 struct device_node *cpu_dp; 467 468 /* Of course, Sun has to encode things a thousand 469 * different ways, inconsistently. 470 */ 471 for_each_node_by_type(cpu_dp, "cpu") { 472 if (!strcmp(cpu_dp->name, "SUNW,UltraSPARC-IIe")) 473 hummingbird_p = 1; 474 } 475 } 476 477 err = -ENOMEM; 478 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); 479 if (!pbm) { 480 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); 481 goto out_err; 482 } 483 484 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); 485 if (!iommu) { 486 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n"); 487 goto out_free_controller; 488 } 489 490 pbm->iommu = iommu; 491 492 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); 493 494 pbm->portid = upa_portid; 495 496 /* 497 * Map in SABRE register set and report the presence of this SABRE. 498 */ 499 500 pr_regs = of_get_property(dp, "reg", NULL); 501 err = -ENODEV; 502 if (!pr_regs) { 503 printk(KERN_ERR PFX "No reg property\n"); 504 goto out_free_iommu; 505 } 506 507 /* 508 * First REG in property is base of entire SABRE register space. 509 */ 510 pbm->controller_regs = pr_regs[0].phys_addr; 511 512 /* Clear interrupts */ 513 514 /* PCI first */ 515 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8) 516 upa_writeq(0x0UL, pbm->controller_regs + clear_irq); 517 518 /* Then OBIO */ 519 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8) 520 upa_writeq(0x0UL, pbm->controller_regs + clear_irq); 521 522 /* Error interrupts are enabled later after the bus scan. */ 523 upa_writeq((SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR | 524 SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN), 525 pbm->controller_regs + SABRE_PCICTRL); 526 527 /* Now map in PCI config space for entire SABRE. */ 528 pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE; 529 530 vdma = of_get_property(dp, "virtual-dma", NULL); 531 if (!vdma) { 532 printk(KERN_ERR PFX "No virtual-dma property\n"); 533 goto out_free_iommu; 534 } 535 536 dma_mask = vdma[0]; 537 switch(vdma[1]) { 538 case 0x20000000: 539 dma_mask |= 0x1fffffff; 540 tsbsize = 64; 541 break; 542 case 0x40000000: 543 dma_mask |= 0x3fffffff; 544 tsbsize = 128; 545 break; 546 547 case 0x80000000: 548 dma_mask |= 0x7fffffff; 549 tsbsize = 128; 550 break; 551 default: 552 printk(KERN_ERR PFX "Strange virtual-dma size.\n"); 553 goto out_free_iommu; 554 } 555 556 err = psycho_iommu_init(pbm, tsbsize, vdma[0], dma_mask, SABRE_WRSYNC); 557 if (err) 558 goto out_free_iommu; 559 560 /* 561 * Look for APB underneath. 562 */ 563 sabre_pbm_init(pbm, op); 564 565 pbm->next = pci_pbm_root; 566 pci_pbm_root = pbm; 567 568 dev_set_drvdata(&op->dev, pbm); 569 570 return 0; 571 572out_free_iommu: 573 kfree(pbm->iommu); 574 575out_free_controller: 576 kfree(pbm); 577 578out_err: 579 return err; 580} 581 582static struct of_device_id __initdata sabre_match[] = { 583 { 584 .name = "pci", 585 .compatible = "pci108e,a001", 586 .data = (void *) 1, 587 }, 588 { 589 .name = "pci", 590 .compatible = "pci108e,a000", 591 }, 592 {}, 593}; 594 595static struct of_platform_driver sabre_driver = { 596 .driver = { 597 .name = DRIVER_NAME, 598 .owner = THIS_MODULE, 599 .of_match_table = sabre_match, 600 }, 601 .probe = sabre_probe, 602}; 603 604static int __init sabre_init(void) 605{ 606 return of_register_platform_driver(&sabre_driver); 607} 608 609subsys_initcall(sabre_init); 610