1#ifndef _SPARC_VAC_OPS_H 2#define _SPARC_VAC_OPS_H 3 4/* vac-ops.h: Inline assembly routines to do operations on the Sparc 5 * VAC (virtual address cache) for the sun4c. 6 * 7 * Copyright (C) 1994, David S. Miller (davem@caip.rutgers.edu) 8 */ 9 10#include <asm/sysen.h> 11#include <asm/contregs.h> 12#include <asm/asi.h> 13 14/* The SUN4C models have a virtually addressed write-through 15 * cache. 16 * 17 * The cache tags are directly accessible through an ASI and 18 * each have the form: 19 * 20 * ------------------------------------------------------------ 21 * | MBZ | CONTEXT | WRITE | PRIV | VALID | MBZ | TagID | MBZ | 22 * ------------------------------------------------------------ 23 * 31 25 24 22 21 20 19 18 16 15 2 1 0 24 * 25 * MBZ: These bits are either unused and/or reserved and should 26 * be written as zeroes. 27 * 28 * CONTEXT: Records the context to which this cache line belongs. 29 * 30 * WRITE: A copy of the writable bit from the mmu pte access bits. 31 * 32 * PRIV: A copy of the privileged bit from the pte access bits. 33 * 34 * VALID: If set, this line is valid, else invalid. 35 * 36 * TagID: Fourteen bits of tag ID. 37 * 38 * Every virtual address is seen by the cache like this: 39 * 40 * ---------------------------------------- 41 * | RESV | TagID | LINE | BYTE-in-LINE | 42 * ---------------------------------------- 43 * 31 30 29 16 15 4 3 0 44 * 45 * RESV: Unused/reserved. 46 * 47 * TagID: Used to match the Tag-ID in that vac tags. 48 * 49 * LINE: Which line within the cache 50 * 51 * BYTE-in-LINE: Which byte within the cache line. 52 */ 53 54/* Sun4c VAC Tags */ 55#define S4CVACTAG_CID 0x01c00000 56#define S4CVACTAG_W 0x00200000 57#define S4CVACTAG_P 0x00100000 58#define S4CVACTAG_V 0x00080000 59#define S4CVACTAG_TID 0x0000fffc 60 61/* Sun4c VAC Virtual Address */ 62/* These aren't used, why bother? (Anton) */ 63 64/* The indexing of cache lines creates a problem. Because the line 65 * field of a virtual address extends past the page offset within 66 * the virtual address it is possible to have what are called 67 * 'bad aliases' which will create inconsistencies. So we must make 68 * sure that within a context that if a physical page is mapped 69 * more than once, that 'extra' line bits are the same. If this is 70 * not the case, and thus is a 'bad alias' we must turn off the 71 * cacheable bit in the pte's of all such pages. 72 */ 73 74#define S4CVAC_BADBITS 0x0000f000 75 76/* The following is true if vaddr1 and vaddr2 would cause 77 * a 'bad alias'. 78 */ 79#define S4CVAC_BADALIAS(vaddr1, vaddr2) \ 80 ((((unsigned long) (vaddr1)) ^ ((unsigned long) (vaddr2))) & \ 81 (S4CVAC_BADBITS)) 82 83/* The following structure describes the characteristics of a sun4c 84 * VAC as probed from the prom during boot time. 85 */ 86struct sun4c_vac_props { 87 unsigned int num_bytes; /* Size of the cache */ 88 unsigned int do_hwflushes; /* Hardware flushing available? */ 89 unsigned int linesize; /* Size of each line in bytes */ 90 unsigned int log2lsize; /* log2(linesize) */ 91 unsigned int on; /* VAC is enabled */ 92}; 93 94extern struct sun4c_vac_props sun4c_vacinfo; 95 96/* sun4c_enable_vac() enables the sun4c virtual address cache. */ 97static inline void sun4c_enable_vac(void) 98{ 99 __asm__ __volatile__("lduba [%0] %1, %%g1\n\t" 100 "or %%g1, %2, %%g1\n\t" 101 "stba %%g1, [%0] %1\n\t" 102 : /* no outputs */ 103 : "r" ((unsigned int) AC_SENABLE), 104 "i" (ASI_CONTROL), "i" (SENABLE_CACHE) 105 : "g1", "memory"); 106 sun4c_vacinfo.on = 1; 107} 108 109/* sun4c_disable_vac() disables the virtual address cache. */ 110static inline void sun4c_disable_vac(void) 111{ 112 __asm__ __volatile__("lduba [%0] %1, %%g1\n\t" 113 "andn %%g1, %2, %%g1\n\t" 114 "stba %%g1, [%0] %1\n\t" 115 : /* no outputs */ 116 : "r" ((unsigned int) AC_SENABLE), 117 "i" (ASI_CONTROL), "i" (SENABLE_CACHE) 118 : "g1", "memory"); 119 sun4c_vacinfo.on = 0; 120} 121 122#endif /* !(_SPARC_VAC_OPS_H) */ 123