1/* 2 * SH7763 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2007 Yoshihiro Shimoda 6 * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12#include <linux/platform_device.h> 13#include <linux/init.h> 14#include <linux/serial.h> 15#include <linux/sh_timer.h> 16#include <linux/io.h> 17#include <linux/serial_sci.h> 18 19static struct plat_sci_port scif0_platform_data = { 20 .mapbase = 0xffe00000, 21 .flags = UPF_BOOT_AUTOCONF, 22 .type = PORT_SCIF, 23 .irqs = { 40, 40, 40, 40 }, 24}; 25 26static struct platform_device scif0_device = { 27 .name = "sh-sci", 28 .id = 0, 29 .dev = { 30 .platform_data = &scif0_platform_data, 31 }, 32}; 33 34static struct plat_sci_port scif1_platform_data = { 35 .mapbase = 0xffe08000, 36 .flags = UPF_BOOT_AUTOCONF, 37 .type = PORT_SCIF, 38 .irqs = { 76, 76, 76, 76 }, 39}; 40 41static struct platform_device scif1_device = { 42 .name = "sh-sci", 43 .id = 1, 44 .dev = { 45 .platform_data = &scif1_platform_data, 46 }, 47}; 48 49static struct plat_sci_port scif2_platform_data = { 50 .mapbase = 0xffe10000, 51 .flags = UPF_BOOT_AUTOCONF, 52 .type = PORT_SCIF, 53 .irqs = { 104, 104, 104, 104 }, 54}; 55 56static struct platform_device scif2_device = { 57 .name = "sh-sci", 58 .id = 2, 59 .dev = { 60 .platform_data = &scif2_platform_data, 61 }, 62}; 63 64static struct resource rtc_resources[] = { 65 [0] = { 66 .start = 0xffe80000, 67 .end = 0xffe80000 + 0x58 - 1, 68 .flags = IORESOURCE_IO, 69 }, 70 [1] = { 71 /* Shared Period/Carry/Alarm IRQ */ 72 .start = 20, 73 .flags = IORESOURCE_IRQ, 74 }, 75}; 76 77static struct platform_device rtc_device = { 78 .name = "sh-rtc", 79 .id = -1, 80 .num_resources = ARRAY_SIZE(rtc_resources), 81 .resource = rtc_resources, 82}; 83 84static struct resource usb_ohci_resources[] = { 85 [0] = { 86 .start = 0xffec8000, 87 .end = 0xffec80ff, 88 .flags = IORESOURCE_MEM, 89 }, 90 [1] = { 91 .start = 83, 92 .end = 83, 93 .flags = IORESOURCE_IRQ, 94 }, 95}; 96 97static u64 usb_ohci_dma_mask = 0xffffffffUL; 98static struct platform_device usb_ohci_device = { 99 .name = "sh_ohci", 100 .id = -1, 101 .dev = { 102 .dma_mask = &usb_ohci_dma_mask, 103 .coherent_dma_mask = 0xffffffff, 104 }, 105 .num_resources = ARRAY_SIZE(usb_ohci_resources), 106 .resource = usb_ohci_resources, 107}; 108 109static struct resource usbf_resources[] = { 110 [0] = { 111 .start = 0xffec0000, 112 .end = 0xffec00ff, 113 .flags = IORESOURCE_MEM, 114 }, 115 [1] = { 116 .start = 84, 117 .end = 84, 118 .flags = IORESOURCE_IRQ, 119 }, 120}; 121 122static struct platform_device usbf_device = { 123 .name = "sh_udc", 124 .id = -1, 125 .dev = { 126 .dma_mask = NULL, 127 .coherent_dma_mask = 0xffffffff, 128 }, 129 .num_resources = ARRAY_SIZE(usbf_resources), 130 .resource = usbf_resources, 131}; 132 133static struct sh_timer_config tmu0_platform_data = { 134 .channel_offset = 0x04, 135 .timer_bit = 0, 136 .clockevent_rating = 200, 137}; 138 139static struct resource tmu0_resources[] = { 140 [0] = { 141 .start = 0xffd80008, 142 .end = 0xffd80013, 143 .flags = IORESOURCE_MEM, 144 }, 145 [1] = { 146 .start = 28, 147 .flags = IORESOURCE_IRQ, 148 }, 149}; 150 151static struct platform_device tmu0_device = { 152 .name = "sh_tmu", 153 .id = 0, 154 .dev = { 155 .platform_data = &tmu0_platform_data, 156 }, 157 .resource = tmu0_resources, 158 .num_resources = ARRAY_SIZE(tmu0_resources), 159}; 160 161static struct sh_timer_config tmu1_platform_data = { 162 .channel_offset = 0x10, 163 .timer_bit = 1, 164 .clocksource_rating = 200, 165}; 166 167static struct resource tmu1_resources[] = { 168 [0] = { 169 .start = 0xffd80014, 170 .end = 0xffd8001f, 171 .flags = IORESOURCE_MEM, 172 }, 173 [1] = { 174 .start = 29, 175 .flags = IORESOURCE_IRQ, 176 }, 177}; 178 179static struct platform_device tmu1_device = { 180 .name = "sh_tmu", 181 .id = 1, 182 .dev = { 183 .platform_data = &tmu1_platform_data, 184 }, 185 .resource = tmu1_resources, 186 .num_resources = ARRAY_SIZE(tmu1_resources), 187}; 188 189static struct sh_timer_config tmu2_platform_data = { 190 .channel_offset = 0x1c, 191 .timer_bit = 2, 192}; 193 194static struct resource tmu2_resources[] = { 195 [0] = { 196 .start = 0xffd80020, 197 .end = 0xffd8002f, 198 .flags = IORESOURCE_MEM, 199 }, 200 [1] = { 201 .start = 30, 202 .flags = IORESOURCE_IRQ, 203 }, 204}; 205 206static struct platform_device tmu2_device = { 207 .name = "sh_tmu", 208 .id = 2, 209 .dev = { 210 .platform_data = &tmu2_platform_data, 211 }, 212 .resource = tmu2_resources, 213 .num_resources = ARRAY_SIZE(tmu2_resources), 214}; 215 216static struct sh_timer_config tmu3_platform_data = { 217 .channel_offset = 0x04, 218 .timer_bit = 0, 219}; 220 221static struct resource tmu3_resources[] = { 222 [0] = { 223 .start = 0xffd88008, 224 .end = 0xffd88013, 225 .flags = IORESOURCE_MEM, 226 }, 227 [1] = { 228 .start = 96, 229 .flags = IORESOURCE_IRQ, 230 }, 231}; 232 233static struct platform_device tmu3_device = { 234 .name = "sh_tmu", 235 .id = 3, 236 .dev = { 237 .platform_data = &tmu3_platform_data, 238 }, 239 .resource = tmu3_resources, 240 .num_resources = ARRAY_SIZE(tmu3_resources), 241}; 242 243static struct sh_timer_config tmu4_platform_data = { 244 .channel_offset = 0x10, 245 .timer_bit = 1, 246}; 247 248static struct resource tmu4_resources[] = { 249 [0] = { 250 .start = 0xffd88014, 251 .end = 0xffd8801f, 252 .flags = IORESOURCE_MEM, 253 }, 254 [1] = { 255 .start = 97, 256 .flags = IORESOURCE_IRQ, 257 }, 258}; 259 260static struct platform_device tmu4_device = { 261 .name = "sh_tmu", 262 .id = 4, 263 .dev = { 264 .platform_data = &tmu4_platform_data, 265 }, 266 .resource = tmu4_resources, 267 .num_resources = ARRAY_SIZE(tmu4_resources), 268}; 269 270static struct sh_timer_config tmu5_platform_data = { 271 .channel_offset = 0x1c, 272 .timer_bit = 2, 273}; 274 275static struct resource tmu5_resources[] = { 276 [0] = { 277 .start = 0xffd88020, 278 .end = 0xffd8802b, 279 .flags = IORESOURCE_MEM, 280 }, 281 [1] = { 282 .start = 98, 283 .flags = IORESOURCE_IRQ, 284 }, 285}; 286 287static struct platform_device tmu5_device = { 288 .name = "sh_tmu", 289 .id = 5, 290 .dev = { 291 .platform_data = &tmu5_platform_data, 292 }, 293 .resource = tmu5_resources, 294 .num_resources = ARRAY_SIZE(tmu5_resources), 295}; 296 297static struct platform_device *sh7763_devices[] __initdata = { 298 &scif0_device, 299 &scif1_device, 300 &scif2_device, 301 &tmu0_device, 302 &tmu1_device, 303 &tmu2_device, 304 &tmu3_device, 305 &tmu4_device, 306 &tmu5_device, 307 &rtc_device, 308 &usb_ohci_device, 309 &usbf_device, 310}; 311 312static int __init sh7763_devices_setup(void) 313{ 314 return platform_add_devices(sh7763_devices, 315 ARRAY_SIZE(sh7763_devices)); 316} 317arch_initcall(sh7763_devices_setup); 318 319static struct platform_device *sh7763_early_devices[] __initdata = { 320 &scif0_device, 321 &scif1_device, 322 &scif2_device, 323 &tmu0_device, 324 &tmu1_device, 325 &tmu2_device, 326 &tmu3_device, 327 &tmu4_device, 328 &tmu5_device, 329}; 330 331void __init plat_early_device_setup(void) 332{ 333 early_platform_add_devices(sh7763_early_devices, 334 ARRAY_SIZE(sh7763_early_devices)); 335} 336 337enum { 338 UNUSED = 0, 339 340 /* interrupt sources */ 341 342 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 343 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 344 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 345 IRL_HHLL, IRL_HHLH, IRL_HHHL, 346 347 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 348 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, 349 HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC, 350 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5, 351 STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2, 352 USBH, USBF, TPU, PCC, MMCIF, SIM, 353 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3, 354 SCIF2, GPIO, 355 356 /* interrupt groups */ 357 358 TMU012, TMU345, 359}; 360 361static struct intc_vect vectors[] __initdata = { 362 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 363 INTC_VECT(RTC, 0x4c0), 364 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580), 365 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0), 366 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600), 367 INTC_VECT(LCDC, 0x620), 368 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 369 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 370 INTC_VECT(DMAC, 0x6c0), 371 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720), 372 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760), 373 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 374 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0), 375 INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920), 376 INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960), 377 INTC_VECT(HAC, 0x980), 378 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 379 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 380 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0), 381 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0), 382 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20), 383 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60), 384 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0), 385 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0), 386 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20), 387 INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80), 388 INTC_VECT(USBF, 0xca0), 389 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0), 390 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20), 391 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60), 392 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), 393 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), 394 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 395 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60), 396 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), 397 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0), 398 INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20), 399 INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60), 400 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0), 401 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0), 402}; 403 404static struct intc_group groups[] __initdata = { 405 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 406 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 407}; 408 409static struct intc_mask_reg mask_registers[] __initdata = { 410 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 411 { 0, 0, 0, 0, 0, 0, GPIO, 0, 412 SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB, 413 PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC, 414 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, 415 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ 416 { 0, 0, 0, 0, 0, 0, SCIF2, USBF, 417 0, 0, STIF1, STIF0, 0, 0, USBH, GETHER, 418 PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1, 419 LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } }, 420}; 421 422static struct intc_prio_reg prio_registers[] __initdata = { 423 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, 424 TMU2, TMU2_TICPI } }, 425 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, 426 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, 427 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } }, 428 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC, 429 PCISERR, PCIINTA } }, 430 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, 431 PCIINTD, PCIC5 } }, 432 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } }, 433 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } }, 434 { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } }, 435 { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } }, 436 { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } }, 437 { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } }, 438 { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } }, 439 { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } }, 440}; 441 442static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups, 443 mask_registers, prio_registers, NULL); 444 445/* Support for external interrupt pins in IRQ mode */ 446static struct intc_vect irq_vectors[] __initdata = { 447 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 448 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 449 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 450 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 451}; 452 453static struct intc_mask_reg irq_mask_registers[] __initdata = { 454 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 455 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 456}; 457 458static struct intc_prio_reg irq_prio_registers[] __initdata = { 459 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 460 IRQ4, IRQ5, IRQ6, IRQ7 } }, 461}; 462 463static struct intc_sense_reg irq_sense_registers[] __initdata = { 464 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 465 IRQ4, IRQ5, IRQ6, IRQ7 } }, 466}; 467 468static struct intc_mask_reg irq_ack_registers[] __initdata = { 469 { 0xffd00024, 0, 32, /* INTREQ */ 470 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 471}; 472 473static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors, 474 NULL, irq_mask_registers, irq_prio_registers, 475 irq_sense_registers, irq_ack_registers); 476 477 478/* External interrupt pins in IRL mode */ 479static struct intc_vect irl_vectors[] __initdata = { 480 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), 481 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), 482 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), 483 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), 484 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), 485 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), 486 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), 487 INTC_VECT(IRL_HHHL, 0x3c0), 488}; 489 490static struct intc_mask_reg irl3210_mask_registers[] __initdata = { 491 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 492 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 493 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 494 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 495 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 496}; 497 498static struct intc_mask_reg irl7654_mask_registers[] __initdata = { 499 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ 500 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 501 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 502 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 503 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 504 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 505}; 506 507static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors, 508 NULL, irl7654_mask_registers, NULL, NULL); 509 510static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors, 511 NULL, irl3210_mask_registers, NULL, NULL); 512 513#define INTC_ICR0 0xffd00000 514#define INTC_INTMSK0 0xffd00044 515#define INTC_INTMSK1 0xffd00048 516#define INTC_INTMSK2 0xffd40080 517#define INTC_INTMSKCLR1 0xffd00068 518#define INTC_INTMSKCLR2 0xffd40084 519 520void __init plat_irq_setup(void) 521{ 522 /* disable IRQ7-0 */ 523 __raw_writel(0xff000000, INTC_INTMSK0); 524 525 /* disable IRL3-0 + IRL7-4 */ 526 __raw_writel(0xc0000000, INTC_INTMSK1); 527 __raw_writel(0xfffefffe, INTC_INTMSK2); 528 529 register_intc_controller(&intc_desc); 530} 531 532void __init plat_irq_setup_pins(int mode) 533{ 534 switch (mode) { 535 case IRQ_MODE_IRQ: 536 /* select IRQ mode for IRL3-0 + IRL7-4 */ 537 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 538 register_intc_controller(&intc_irq_desc); 539 break; 540 case IRQ_MODE_IRL7654: 541 /* enable IRL7-4 but don't provide any masking */ 542 __raw_writel(0x40000000, INTC_INTMSKCLR1); 543 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 544 break; 545 case IRQ_MODE_IRL3210: 546 /* enable IRL0-3 but don't provide any masking */ 547 __raw_writel(0x80000000, INTC_INTMSKCLR1); 548 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 549 break; 550 case IRQ_MODE_IRL7654_MASK: 551 /* enable IRL7-4 and mask using cpu intc controller */ 552 __raw_writel(0x40000000, INTC_INTMSKCLR1); 553 register_intc_controller(&intc_irl7654_desc); 554 break; 555 case IRQ_MODE_IRL3210_MASK: 556 /* enable IRL0-3 and mask using cpu intc controller */ 557 __raw_writel(0x80000000, INTC_INTMSKCLR1); 558 register_intc_controller(&intc_irl3210_desc); 559 break; 560 default: 561 BUG(); 562 } 563} 564