1/* 2 * Based on MPC8560 ADS and arch/ppc tqm85xx ports 3 * 4 * Maintained by Kumar Gala (see MAINTAINERS for contact information) 5 * 6 * Copyright 2008 Freescale Semiconductor Inc. 7 * 8 * Copyright (c) 2005-2006 DENX Software Engineering 9 * Stefan Roese <sr@denx.de> 10 * 11 * Based on original work by 12 * Kumar Gala <kumar.gala@freescale.com> 13 * Copyright 2004 Freescale Semiconductor Inc. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20 21#include <linux/stddef.h> 22#include <linux/kernel.h> 23#include <linux/pci.h> 24#include <linux/kdev_t.h> 25#include <linux/delay.h> 26#include <linux/seq_file.h> 27#include <linux/of_platform.h> 28 29#include <asm/system.h> 30#include <asm/time.h> 31#include <asm/machdep.h> 32#include <asm/pci-bridge.h> 33#include <asm/mpic.h> 34#include <asm/prom.h> 35#include <mm/mmu_decl.h> 36#include <asm/udbg.h> 37 38#include <sysdev/fsl_soc.h> 39#include <sysdev/fsl_pci.h> 40 41#ifdef CONFIG_CPM2 42#include <asm/cpm2.h> 43#include <sysdev/cpm2_pic.h> 44 45static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) 46{ 47 int cascade_irq; 48 49 while ((cascade_irq = cpm2_get_irq()) >= 0) 50 generic_handle_irq(cascade_irq); 51 52 desc->chip->eoi(irq); 53} 54#endif /* CONFIG_CPM2 */ 55 56static void __init tqm85xx_pic_init(void) 57{ 58 struct mpic *mpic; 59 struct resource r; 60 struct device_node *np; 61#ifdef CONFIG_CPM2 62 int irq; 63#endif 64 65 np = of_find_node_by_type(NULL, "open-pic"); 66 if (!np) { 67 printk(KERN_ERR "Could not find open-pic node\n"); 68 return; 69 } 70 71 if (of_address_to_resource(np, 0, &r)) { 72 printk(KERN_ERR "Could not map mpic register space\n"); 73 of_node_put(np); 74 return; 75 } 76 77 mpic = mpic_alloc(np, r.start, 78 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, 79 0, 256, " OpenPIC "); 80 BUG_ON(mpic == NULL); 81 of_node_put(np); 82 83 mpic_init(mpic); 84 85#ifdef CONFIG_CPM2 86 /* Setup CPM2 PIC */ 87 np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic"); 88 if (np == NULL) { 89 printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n"); 90 return; 91 } 92 irq = irq_of_parse_and_map(np, 0); 93 94 if (irq == NO_IRQ) { 95 of_node_put(np); 96 printk(KERN_ERR "PIC init: got no IRQ for cpm cascade\n"); 97 return; 98 } 99 100 cpm2_pic_init(np); 101 of_node_put(np); 102 set_irq_chained_handler(irq, cpm2_cascade); 103#endif 104} 105 106/* 107 * Setup the architecture 108 */ 109static void __init tqm85xx_setup_arch(void) 110{ 111#ifdef CONFIG_PCI 112 struct device_node *np; 113#endif 114 115 if (ppc_md.progress) 116 ppc_md.progress("tqm85xx_setup_arch()", 0); 117 118#ifdef CONFIG_CPM2 119 cpm2_reset(); 120#endif 121 122#ifdef CONFIG_PCI 123 for_each_node_by_type(np, "pci") { 124 if (of_device_is_compatible(np, "fsl,mpc8540-pci") || 125 of_device_is_compatible(np, "fsl,mpc8548-pcie")) { 126 struct resource rsrc; 127 if (!of_address_to_resource(np, 0, &rsrc)) { 128 if ((rsrc.start & 0xfffff) == 0x8000) 129 fsl_add_bridge(np, 1); 130 else 131 fsl_add_bridge(np, 0); 132 } 133 } 134 } 135#endif 136} 137 138static void tqm85xx_show_cpuinfo(struct seq_file *m) 139{ 140 uint pvid, svid, phid1; 141 142 pvid = mfspr(SPRN_PVR); 143 svid = mfspr(SPRN_SVR); 144 145 seq_printf(m, "Vendor\t\t: TQ Components\n"); 146 seq_printf(m, "PVR\t\t: 0x%x\n", pvid); 147 seq_printf(m, "SVR\t\t: 0x%x\n", svid); 148 149 /* Display cpu Pll setting */ 150 phid1 = mfspr(SPRN_HID1); 151 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); 152} 153 154static void __init tqm85xx_ti1520_fixup(struct pci_dev *pdev) 155{ 156 unsigned int val; 157 158 /* Do not do the fixup on other platforms! */ 159 if (!machine_is(tqm85xx)) 160 return; 161 162 dev_info(&pdev->dev, "Using TI 1520 fixup on TQM85xx\n"); 163 164 /* 165 * Enable P2CCLK bit in system control register 166 * to enable CLOCK output to power chip 167 */ 168 pci_read_config_dword(pdev, 0x80, &val); 169 pci_write_config_dword(pdev, 0x80, val | (1 << 27)); 170 171} 172DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520, 173 tqm85xx_ti1520_fixup); 174 175static struct of_device_id __initdata of_bus_ids[] = { 176 { .compatible = "simple-bus", }, 177 { .compatible = "gianfar", }, 178 {}, 179}; 180 181static int __init declare_of_platform_devices(void) 182{ 183 of_platform_bus_probe(NULL, of_bus_ids, NULL); 184 185 return 0; 186} 187machine_device_initcall(tqm85xx, declare_of_platform_devices); 188 189/* 190 * Called very early, device-tree isn't unflattened 191 */ 192static int __init tqm85xx_probe(void) 193{ 194 unsigned long root = of_get_flat_dt_root(); 195 196 if ((of_flat_dt_is_compatible(root, "tqc,tqm8540")) || 197 (of_flat_dt_is_compatible(root, "tqc,tqm8541")) || 198 (of_flat_dt_is_compatible(root, "tqc,tqm8548")) || 199 (of_flat_dt_is_compatible(root, "tqc,tqm8555")) || 200 (of_flat_dt_is_compatible(root, "tqc,tqm8560"))) 201 return 1; 202 203 return 0; 204} 205 206define_machine(tqm85xx) { 207 .name = "TQM85xx", 208 .probe = tqm85xx_probe, 209 .setup_arch = tqm85xx_setup_arch, 210 .init_IRQ = tqm85xx_pic_init, 211 .show_cpuinfo = tqm85xx_show_cpuinfo, 212 .get_irq = mpic_get_irq, 213 .restart = fsl_rstcr_restart, 214 .calibrate_decr = generic_calibrate_decr, 215 .progress = udbg_progress, 216}; 217