1/* 2 * Low-level SLB routines 3 * 4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM 5 * 6 * Based on earlier C version: 7 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com 8 * Copyright (c) 2001 Dave Engebretsen 9 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17#include <asm/processor.h> 18#include <asm/ppc_asm.h> 19#include <asm/asm-offsets.h> 20#include <asm/cputable.h> 21#include <asm/page.h> 22#include <asm/mmu.h> 23#include <asm/pgtable.h> 24#include <asm/firmware.h> 25 26/* void slb_allocate_realmode(unsigned long ea); 27 * 28 * Create an SLB entry for the given EA (user or kernel). 29 * r3 = faulting address, r13 = PACA 30 * r9, r10, r11 are clobbered by this function 31 * No other registers are examined or changed. 32 */ 33_GLOBAL(slb_allocate_realmode) 34 /* r3 = faulting address */ 35 36 srdi r9,r3,60 /* get region */ 37 srdi r10,r3,28 /* get esid */ 38 cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */ 39 40 /* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */ 41 blt cr7,0f /* user or kernel? */ 42 43 /* kernel address: proto-VSID = ESID */ 44 /* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but 45 * this code will generate the protoVSID 0xfffffffff for the 46 * top segment. That's ok, the scramble below will translate 47 * it to VSID 0, which is reserved as a bad VSID - one which 48 * will never have any pages in it. */ 49 50 /* Check if hitting the linear mapping or some other kernel space 51 */ 52 bne cr7,1f 53 54 /* Linear mapping encoding bits, the "li" instruction below will 55 * be patched by the kernel at boot 56 */ 57_GLOBAL(slb_miss_kernel_load_linear) 58 li r11,0 59BEGIN_FTR_SECTION 60 b slb_finish_load 61END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT) 62 b slb_finish_load_1T 63 641: 65#ifdef CONFIG_SPARSEMEM_VMEMMAP 66 /* Check virtual memmap region. To be patches at kernel boot */ 67 cmpldi cr0,r9,0xf 68 bne 1f 69_GLOBAL(slb_miss_kernel_load_vmemmap) 70 li r11,0 71 b 6f 721: 73#endif /* CONFIG_SPARSEMEM_VMEMMAP */ 74 75 /* vmalloc mapping gets the encoding from the PACA as the mapping 76 * can be demoted from 64K -> 4K dynamically on some machines 77 */ 78 clrldi r11,r10,48 79 cmpldi r11,(VMALLOC_SIZE >> 28) - 1 80 bgt 5f 81 lhz r11,PACAVMALLOCSLLP(r13) 82 b 6f 835: 84 /* IO mapping */ 85 _GLOBAL(slb_miss_kernel_load_io) 86 li r11,0 876: 88BEGIN_FTR_SECTION 89 b slb_finish_load 90END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT) 91 b slb_finish_load_1T 92 930: /* user address: proto-VSID = context << 15 | ESID. First check 94 * if the address is within the boundaries of the user region 95 */ 96 srdi. r9,r10,USER_ESID_BITS 97 bne- 8f /* invalid ea bits set */ 98 99 100#ifdef CONFIG_PPC_MM_SLICES 101 cmpldi r10,16 102 103 /* Get the slice index * 4 in r11 and matching slice size mask in r9 */ 104 ld r9,PACALOWSLICESPSIZE(r13) 105 sldi r11,r10,2 106 blt 5f 107 ld r9,PACAHIGHSLICEPSIZE(r13) 108 srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT - 2) 109 andi. r11,r11,0x3c 110 1115: /* Extract the psize and multiply to get an array offset */ 112 srd r9,r9,r11 113 andi. r9,r9,0xf 114 mulli r9,r9,MMUPSIZEDEFSIZE 115 116 /* Now get to the array and obtain the sllp 117 */ 118 ld r11,PACATOC(r13) 119 ld r11,mmu_psize_defs@got(r11) 120 add r11,r11,r9 121 ld r11,MMUPSIZESLLP(r11) 122 ori r11,r11,SLB_VSID_USER 123#else 124 /* paca context sllp already contains the SLB_VSID_USER bits */ 125 lhz r11,PACACONTEXTSLLP(r13) 126#endif /* CONFIG_PPC_MM_SLICES */ 127 128 ld r9,PACACONTEXTID(r13) 129BEGIN_FTR_SECTION 130 cmpldi r10,0x1000 131END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) 132 rldimi r10,r9,USER_ESID_BITS,0 133BEGIN_FTR_SECTION 134 bge slb_finish_load_1T 135END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) 136 b slb_finish_load 137 1388: /* invalid EA */ 139 li r10,0 /* BAD_VSID */ 140 li r11,SLB_VSID_USER /* flags don't much matter */ 141 b slb_finish_load 142 143#ifdef __DISABLED__ 144 145/* void slb_allocate_user(unsigned long ea); 146 * 147 * Create an SLB entry for the given EA (user or kernel). 148 * r3 = faulting address, r13 = PACA 149 * r9, r10, r11 are clobbered by this function 150 * No other registers are examined or changed. 151 * 152 * It is called with translation enabled in order to be able to walk the 153 * page tables. This is not currently used. 154 */ 155_GLOBAL(slb_allocate_user) 156 /* r3 = faulting address */ 157 srdi r10,r3,28 /* get esid */ 158 159 crset 4*cr7+lt /* set "user" flag for later */ 160 161 /* check if we fit in the range covered by the pagetables*/ 162 srdi. r9,r3,PGTABLE_EADDR_SIZE 163 crnot 4*cr0+eq,4*cr0+eq 164 beqlr 165 166 /* now we need to get to the page tables in order to get the page 167 * size encoding from the PMD. In the future, we'll be able to deal 168 * with 1T segments too by getting the encoding from the PGD instead 169 */ 170 ld r9,PACAPGDIR(r13) 171 cmpldi cr0,r9,0 172 beqlr 173 rlwinm r11,r10,8,25,28 174 ldx r9,r9,r11 /* get pgd_t */ 175 cmpldi cr0,r9,0 176 beqlr 177 rlwinm r11,r10,3,17,28 178 ldx r9,r9,r11 /* get pmd_t */ 179 cmpldi cr0,r9,0 180 beqlr 181 182 /* build vsid flags */ 183 andi. r11,r9,SLB_VSID_LLP 184 ori r11,r11,SLB_VSID_USER 185 186 /* get context to calculate proto-VSID */ 187 ld r9,PACACONTEXTID(r13) 188 rldimi r10,r9,USER_ESID_BITS,0 189 190 /* fall through slb_finish_load */ 191 192#endif /* __DISABLED__ */ 193 194 195/* 196 * Finish loading of an SLB entry and return 197 * 198 * r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET 199 */ 200slb_finish_load: 201 ASM_VSID_SCRAMBLE(r10,r9,256M) 202 rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */ 203 204 /* r3 = EA, r11 = VSID data */ 205 /* 206 * Find a slot, round robin. Previously we tried to find a 207 * free slot first but that took too long. Unfortunately we 208 * dont have any LRU information to help us choose a slot. 209 */ 210#ifdef CONFIG_PPC_ISERIES 211BEGIN_FW_FTR_SECTION 212 /* 213 * On iSeries, the "bolted" stack segment can be cast out on 214 * shared processor switch so we need to check for a miss on 215 * it and restore it to the right slot. 216 */ 217 ld r9,PACAKSAVE(r13) 218 clrrdi r9,r9,28 219 clrrdi r3,r3,28 220 li r10,SLB_NUM_BOLTED-1 /* Stack goes in last bolted slot */ 221 cmpld r9,r3 222 beq 3f 223END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 224#endif /* CONFIG_PPC_ISERIES */ 225 2267: ld r10,PACASTABRR(r13) 227 addi r10,r10,1 228 /* This gets soft patched on boot. */ 229_GLOBAL(slb_compare_rr_to_size) 230 cmpldi r10,0 231 232 blt+ 4f 233 li r10,SLB_NUM_BOLTED 234 2354: 236 std r10,PACASTABRR(r13) 237 2383: 239 rldimi r3,r10,0,36 /* r3= EA[0:35] | entry */ 240 oris r10,r3,SLB_ESID_V@h /* r3 |= SLB_ESID_V */ 241 242 /* r3 = ESID data, r11 = VSID data */ 243 244 /* 245 * No need for an isync before or after this slbmte. The exception 246 * we enter with and the rfid we exit with are context synchronizing. 247 */ 248 slbmte r11,r10 249 250 /* we're done for kernel addresses */ 251 crclr 4*cr0+eq /* set result to "success" */ 252 bgelr cr7 253 254 /* Update the slb cache */ 255 lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */ 256 cmpldi r3,SLB_CACHE_ENTRIES 257 bge 1f 258 259 /* still room in the slb cache */ 260 sldi r11,r3,1 /* r11 = offset * sizeof(u16) */ 261 rldicl r10,r10,36,28 /* get low 16 bits of the ESID */ 262 add r11,r11,r13 /* r11 = (u16 *)paca + offset */ 263 sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */ 264 addi r3,r3,1 /* offset++ */ 265 b 2f 2661: /* offset >= SLB_CACHE_ENTRIES */ 267 li r3,SLB_CACHE_ENTRIES+1 2682: 269 sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */ 270 crclr 4*cr0+eq /* set result to "success" */ 271 blr 272 273/* 274 * Finish loading of a 1T SLB entry (for the kernel linear mapping) and return. 275 * We assume legacy iSeries will never have 1T segments. 276 * 277 * r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9 278 */ 279slb_finish_load_1T: 280 srdi r10,r10,40-28 /* get 1T ESID */ 281 ASM_VSID_SCRAMBLE(r10,r9,1T) 282 rldimi r11,r10,SLB_VSID_SHIFT_1T,16 /* combine VSID and flags */ 283 li r10,MMU_SEGSIZE_1T 284 rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */ 285 286 /* r3 = EA, r11 = VSID data */ 287 clrrdi r3,r3,SID_SHIFT_1T /* clear out non-ESID bits */ 288 b 7b 289