1/* 2 * Kernel execution entry point code. 3 * 4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 5 * Initial PowerPC version. 6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Rewritten for PReP 8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 9 * Low-level exception handers, MMU support, and rewrite. 10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 11 * PowerPC 8xx modifications. 12 * Copyright (c) 1998-1999 TiVo, Inc. 13 * PowerPC 403GCX modifications. 14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 15 * PowerPC 403GCX/405GP modifications. 16 * Copyright 2000 MontaVista Software Inc. 17 * PPC405 modifications 18 * PowerPC 403GCX/405GP modifications. 19 * Author: MontaVista Software, Inc. 20 * frank_rowand@mvista.com or source@mvista.com 21 * debbie_chu@mvista.com 22 * Copyright 2002-2004 MontaVista Software, Inc. 23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> 24 * Copyright 2004 Freescale Semiconductor, Inc 25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org> 26 * 27 * This program is free software; you can redistribute it and/or modify it 28 * under the terms of the GNU General Public License as published by the 29 * Free Software Foundation; either version 2 of the License, or (at your 30 * option) any later version. 31 */ 32 33#include <linux/init.h> 34#include <linux/threads.h> 35#include <asm/processor.h> 36#include <asm/page.h> 37#include <asm/mmu.h> 38#include <asm/pgtable.h> 39#include <asm/cputable.h> 40#include <asm/thread_info.h> 41#include <asm/ppc_asm.h> 42#include <asm/asm-offsets.h> 43#include <asm/cache.h> 44#include "head_booke.h" 45 46/* As with the other PowerPC ports, it is expected that when code 47 * execution begins here, the following registers contain valid, yet 48 * optional, information: 49 * 50 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 51 * r4 - Starting address of the init RAM disk 52 * r5 - Ending address of the init RAM disk 53 * r6 - Start of kernel command line string (e.g. "mem=128") 54 * r7 - End of kernel command line string 55 * 56 */ 57 __HEAD 58_ENTRY(_stext); 59_ENTRY(_start); 60 /* 61 * Reserve a word at a fixed location to store the address 62 * of abatron_pteptrs 63 */ 64 nop 65/* 66 * Save parameters we are passed 67 */ 68 mr r31,r3 69 mr r30,r4 70 mr r29,r5 71 mr r28,r6 72 mr r27,r7 73 li r25,0 /* phys kernel start (low) */ 74 li r24,0 /* CPU number */ 75 li r23,0 /* phys kernel start (high) */ 76 77/* We try to not make any assumptions about how the boot loader 78 * setup or used the TLBs. We invalidate all mappings from the 79 * boot loader and load a single entry in TLB1[0] to map the 80 * first 64M of kernel memory. Any boot info passed from the 81 * bootloader needs to live in this first 64M. 82 * 83 * Requirement on bootloader: 84 * - The page we're executing in needs to reside in TLB1 and 85 * have IPROT=1. If not an invalidate broadcast could 86 * evict the entry we're currently executing in. 87 * 88 * r3 = Index of TLB1 were executing in 89 * r4 = Current MSR[IS] 90 * r5 = Index of TLB1 temp mapping 91 * 92 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] 93 * if needed 94 */ 95 96_ENTRY(__early_start) 97 98#define ENTRY_MAPPING_BOOT_SETUP 99#include "fsl_booke_entry_mapping.S" 100#undef ENTRY_MAPPING_BOOT_SETUP 101 102 /* Establish the interrupt vector offsets */ 103 SET_IVOR(0, CriticalInput); 104 SET_IVOR(1, MachineCheck); 105 SET_IVOR(2, DataStorage); 106 SET_IVOR(3, InstructionStorage); 107 SET_IVOR(4, ExternalInput); 108 SET_IVOR(5, Alignment); 109 SET_IVOR(6, Program); 110 SET_IVOR(7, FloatingPointUnavailable); 111 SET_IVOR(8, SystemCall); 112 SET_IVOR(9, AuxillaryProcessorUnavailable); 113 SET_IVOR(10, Decrementer); 114 SET_IVOR(11, FixedIntervalTimer); 115 SET_IVOR(12, WatchdogTimer); 116 SET_IVOR(13, DataTLBError); 117 SET_IVOR(14, InstructionTLBError); 118 SET_IVOR(15, DebugCrit); 119 120 /* Establish the interrupt vector base */ 121 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 122 mtspr SPRN_IVPR,r4 123 124 /* Setup the defaults for TLB entries */ 125 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l 126#ifdef CONFIG_E200 127 oris r2,r2,MAS4_TLBSELD(1)@h 128#endif 129 mtspr SPRN_MAS4, r2 130 131 132#if !defined(CONFIG_BDI_SWITCH) 133 /* 134 * The Abatron BDI JTAG debugger does not tolerate others 135 * mucking with the debug registers. 136 */ 137 lis r2,DBCR0_IDM@h 138 mtspr SPRN_DBCR0,r2 139 isync 140 /* clear any residual debug events */ 141 li r2,-1 142 mtspr SPRN_DBSR,r2 143#endif 144 145#ifdef CONFIG_SMP 146 /* Check to see if we're the second processor, and jump 147 * to the secondary_start code if so 148 */ 149 mfspr r24,SPRN_PIR 150 cmpwi r24,0 151 bne __secondary_start 152#endif 153 154 /* 155 * This is where the main kernel code starts. 156 */ 157 158 /* ptr to current */ 159 lis r2,init_task@h 160 ori r2,r2,init_task@l 161 162 /* ptr to current thread */ 163 addi r4,r2,THREAD /* init task's THREAD */ 164 mtspr SPRN_SPRG_THREAD,r4 165 166 /* stack */ 167 lis r1,init_thread_union@h 168 ori r1,r1,init_thread_union@l 169 li r0,0 170 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 171 172 bl early_init 173 174#ifdef CONFIG_RELOCATABLE 175 lis r3,kernstart_addr@ha 176 la r3,kernstart_addr@l(r3) 177#ifdef CONFIG_PHYS_64BIT 178 stw r23,0(r3) 179 stw r25,4(r3) 180#else 181 stw r25,0(r3) 182#endif 183#endif 184 185/* 186 * Decide what sort of machine this is and initialize the MMU. 187 */ 188 mr r3,r31 189 mr r4,r30 190 mr r5,r29 191 mr r6,r28 192 mr r7,r27 193 bl machine_init 194 bl MMU_init 195 196 /* Setup PTE pointers for the Abatron bdiGDB */ 197 lis r6, swapper_pg_dir@h 198 ori r6, r6, swapper_pg_dir@l 199 lis r5, abatron_pteptrs@h 200 ori r5, r5, abatron_pteptrs@l 201 lis r4, KERNELBASE@h 202 ori r4, r4, KERNELBASE@l 203 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ 204 stw r6, 0(r5) 205 206 /* Let's move on */ 207 lis r4,start_kernel@h 208 ori r4,r4,start_kernel@l 209 lis r3,MSR_KERNEL@h 210 ori r3,r3,MSR_KERNEL@l 211 mtspr SPRN_SRR0,r4 212 mtspr SPRN_SRR1,r3 213 rfi /* change context and jump to start_kernel */ 214 215/* Macros to hide the PTE size differences 216 * 217 * FIND_PTE -- walks the page tables given EA & pgdir pointer 218 * r10 -- EA of fault 219 * r11 -- PGDIR pointer 220 * r12 -- free 221 * label 2: is the bailout case 222 * 223 * if we find the pte (fall through): 224 * r11 is low pte word 225 * r12 is pointer to the pte 226 */ 227#ifdef CONFIG_PTE_64BIT 228#define FIND_PTE \ 229 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ 230 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ 231 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ 232 beq 2f; /* Bail if no table */ \ 233 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ 234 lwz r11, 4(r12); /* Get pte entry */ 235#else 236#define FIND_PTE \ 237 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ 238 lwz r11, 0(r11); /* Get L1 entry */ \ 239 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ 240 beq 2f; /* Bail if no table */ \ 241 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ 242 lwz r11, 0(r12); /* Get Linux PTE */ 243#endif 244 245/* 246 * Interrupt vector entry code 247 * 248 * The Book E MMUs are always on so we don't need to handle 249 * interrupts in real mode as with previous PPC processors. In 250 * this case we handle interrupts in the kernel virtual address 251 * space. 252 * 253 * Interrupt vectors are dynamically placed relative to the 254 * interrupt prefix as determined by the address of interrupt_base. 255 * The interrupt vectors offsets are programmed using the labels 256 * for each interrupt vector entry. 257 * 258 * Interrupt vectors must be aligned on a 16 byte boundary. 259 * We align on a 32 byte cache line boundary for good measure. 260 */ 261 262interrupt_base: 263 /* Critical Input Interrupt */ 264 CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception) 265 266 /* Machine Check Interrupt */ 267#ifdef CONFIG_E200 268 /* no RFMCI, MCSRRs on E200 */ 269 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) 270#else 271 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) 272#endif 273 274 /* Data Storage Interrupt */ 275 START_EXCEPTION(DataStorage) 276 NORMAL_EXCEPTION_PROLOG 277 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ 278 stw r5,_ESR(r11) 279 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ 280 andis. r10,r5,(ESR_ILK|ESR_DLK)@h 281 bne 1f 282 EXC_XFER_EE_LITE(0x0300, handle_page_fault) 2831: 284 addi r3,r1,STACK_FRAME_OVERHEAD 285 EXC_XFER_EE_LITE(0x0300, CacheLockingException) 286 287 /* Instruction Storage Interrupt */ 288 INSTRUCTION_STORAGE_EXCEPTION 289 290 /* External Input Interrupt */ 291 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE) 292 293 /* Alignment Interrupt */ 294 ALIGNMENT_EXCEPTION 295 296 /* Program Interrupt */ 297 PROGRAM_EXCEPTION 298 299 /* Floating Point Unavailable Interrupt */ 300#ifdef CONFIG_PPC_FPU 301 FP_UNAVAILABLE_EXCEPTION 302#else 303#ifdef CONFIG_E200 304 /* E200 treats 'normal' floating point instructions as FP Unavail exception */ 305 EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE) 306#else 307 EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE) 308#endif 309#endif 310 311 /* System Call Interrupt */ 312 START_EXCEPTION(SystemCall) 313 NORMAL_EXCEPTION_PROLOG 314 EXC_XFER_EE_LITE(0x0c00, DoSyscall) 315 316 /* Auxillary Processor Unavailable Interrupt */ 317 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE) 318 319 /* Decrementer Interrupt */ 320 DECREMENTER_EXCEPTION 321 322 /* Fixed Internal Timer Interrupt */ 323 /* TODO: Add FIT support */ 324 EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE) 325 326 /* Watchdog Timer Interrupt */ 327#ifdef CONFIG_BOOKE_WDT 328 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException) 329#else 330 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception) 331#endif 332 333 /* Data TLB Error Interrupt */ 334 START_EXCEPTION(DataTLBError) 335 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 336 mtspr SPRN_SPRG_WSCRATCH1, r11 337 mtspr SPRN_SPRG_WSCRATCH2, r12 338 mtspr SPRN_SPRG_WSCRATCH3, r13 339 mfcr r11 340 mtspr SPRN_SPRG_WSCRATCH4, r11 341 mfspr r10, SPRN_DEAR /* Get faulting address */ 342 343 /* If we are faulting a kernel address, we have to use the 344 * kernel page tables. 345 */ 346 lis r11, PAGE_OFFSET@h 347 cmplw 5, r10, r11 348 blt 5, 3f 349 lis r11, swapper_pg_dir@h 350 ori r11, r11, swapper_pg_dir@l 351 352 mfspr r12,SPRN_MAS1 /* Set TID to 0 */ 353 rlwinm r12,r12,0,16,1 354 mtspr SPRN_MAS1,r12 355 356 b 4f 357 358 /* Get the PGD for the current thread */ 3593: 360 mfspr r11,SPRN_SPRG_THREAD 361 lwz r11,PGDIR(r11) 362 3634: 364 /* Mask of required permission bits. Note that while we 365 * do copy ESR:ST to _PAGE_RW position as trying to write 366 * to an RO page is pretty common, we don't do it with 367 * _PAGE_DIRTY. We could do it, but it's a fairly rare 368 * event so I'd rather take the overhead when it happens 369 * rather than adding an instruction here. We should measure 370 * whether the whole thing is worth it in the first place 371 * as we could avoid loading SPRN_ESR completely in the first 372 * place... 373 * 374 * TODO: Is it worth doing that mfspr & rlwimi in the first 375 * place or can we save a couple of instructions here ? 376 */ 377 mfspr r12,SPRN_ESR 378#ifdef CONFIG_PTE_64BIT 379 li r13,_PAGE_PRESENT 380 oris r13,r13,_PAGE_ACCESSED@h 381#else 382 li r13,_PAGE_PRESENT|_PAGE_ACCESSED 383#endif 384 rlwimi r13,r12,11,29,29 385 386 FIND_PTE 387 andc. r13,r13,r11 /* Check permission */ 388 389#ifdef CONFIG_PTE_64BIT 390#ifdef CONFIG_SMP 391 subf r10,r11,r12 /* create false data dep */ 392 lwzx r13,r11,r10 /* Get upper pte bits */ 393#else 394 lwz r13,0(r12) /* Get upper pte bits */ 395#endif 396#endif 397 398 bne 2f /* Bail if permission/valid mismach */ 399 400 /* Jump to common tlb load */ 401 b finish_tlb_load 4022: 403 /* The bailout. Restore registers to pre-exception conditions 404 * and call the heavyweights to help us out. 405 */ 406 mfspr r11, SPRN_SPRG_RSCRATCH4 407 mtcr r11 408 mfspr r13, SPRN_SPRG_RSCRATCH3 409 mfspr r12, SPRN_SPRG_RSCRATCH2 410 mfspr r11, SPRN_SPRG_RSCRATCH1 411 mfspr r10, SPRN_SPRG_RSCRATCH0 412 b DataStorage 413 414 /* Instruction TLB Error Interrupt */ 415 /* 416 * Nearly the same as above, except we get our 417 * information from different registers and bailout 418 * to a different point. 419 */ 420 START_EXCEPTION(InstructionTLBError) 421 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 422 mtspr SPRN_SPRG_WSCRATCH1, r11 423 mtspr SPRN_SPRG_WSCRATCH2, r12 424 mtspr SPRN_SPRG_WSCRATCH3, r13 425 mfcr r11 426 mtspr SPRN_SPRG_WSCRATCH4, r11 427 mfspr r10, SPRN_SRR0 /* Get faulting address */ 428 429 /* If we are faulting a kernel address, we have to use the 430 * kernel page tables. 431 */ 432 lis r11, PAGE_OFFSET@h 433 cmplw 5, r10, r11 434 blt 5, 3f 435 lis r11, swapper_pg_dir@h 436 ori r11, r11, swapper_pg_dir@l 437 438 mfspr r12,SPRN_MAS1 /* Set TID to 0 */ 439 rlwinm r12,r12,0,16,1 440 mtspr SPRN_MAS1,r12 441 442 /* Make up the required permissions for kernel code */ 443#ifdef CONFIG_PTE_64BIT 444 li r13,_PAGE_PRESENT | _PAGE_BAP_SX 445 oris r13,r13,_PAGE_ACCESSED@h 446#else 447 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 448#endif 449 b 4f 450 451 /* Get the PGD for the current thread */ 4523: 453 mfspr r11,SPRN_SPRG_THREAD 454 lwz r11,PGDIR(r11) 455 456 /* Make up the required permissions for user code */ 457#ifdef CONFIG_PTE_64BIT 458 li r13,_PAGE_PRESENT | _PAGE_BAP_UX 459 oris r13,r13,_PAGE_ACCESSED@h 460#else 461 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 462#endif 463 4644: 465 FIND_PTE 466 andc. r13,r13,r11 /* Check permission */ 467 468#ifdef CONFIG_PTE_64BIT 469#ifdef CONFIG_SMP 470 subf r10,r11,r12 /* create false data dep */ 471 lwzx r13,r11,r10 /* Get upper pte bits */ 472#else 473 lwz r13,0(r12) /* Get upper pte bits */ 474#endif 475#endif 476 477 bne 2f /* Bail if permission mismach */ 478 479 /* Jump to common TLB load point */ 480 b finish_tlb_load 481 4822: 483 /* The bailout. Restore registers to pre-exception conditions 484 * and call the heavyweights to help us out. 485 */ 486 mfspr r11, SPRN_SPRG_RSCRATCH4 487 mtcr r11 488 mfspr r13, SPRN_SPRG_RSCRATCH3 489 mfspr r12, SPRN_SPRG_RSCRATCH2 490 mfspr r11, SPRN_SPRG_RSCRATCH1 491 mfspr r10, SPRN_SPRG_RSCRATCH0 492 b InstructionStorage 493 494#ifdef CONFIG_SPE 495 /* SPE Unavailable */ 496 START_EXCEPTION(SPEUnavailable) 497 NORMAL_EXCEPTION_PROLOG 498 bne load_up_spe 499 addi r3,r1,STACK_FRAME_OVERHEAD 500 EXC_XFER_EE_LITE(0x2010, KernelSPE) 501#else 502 EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE) 503#endif /* CONFIG_SPE */ 504 505 /* SPE Floating Point Data */ 506#ifdef CONFIG_SPE 507 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE); 508 509 /* SPE Floating Point Round */ 510 EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE) 511#else 512 EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE) 513 EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE) 514#endif /* CONFIG_SPE */ 515 516 /* Performance Monitor */ 517 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD) 518 519 EXCEPTION(0x2070, Doorbell, doorbell_exception, EXC_XFER_STD) 520 521 CRITICAL_EXCEPTION(0x2080, CriticalDoorbell, unknown_exception) 522 523 /* Debug Interrupt */ 524 DEBUG_DEBUG_EXCEPTION 525 DEBUG_CRIT_EXCEPTION 526 527/* 528 * Local functions 529 */ 530 531/* 532 * Both the instruction and data TLB miss get to this 533 * point to load the TLB. 534 * r10 - available to use 535 * r11 - TLB (info from Linux PTE) 536 * r12 - available to use 537 * r13 - upper bits of PTE (if PTE_64BIT) or available to use 538 * CR5 - results of addr >= PAGE_OFFSET 539 * MAS0, MAS1 - loaded with proper value when we get here 540 * MAS2, MAS3 - will need additional info from Linux PTE 541 * Upon exit, we reload everything and RFI. 542 */ 543finish_tlb_load: 544 /* 545 * We set execute, because we don't have the granularity to 546 * properly set this at the page level (Linux problem). 547 * Many of these bits are software only. Bits we don't set 548 * here we (properly should) assume have the appropriate value. 549 */ 550 551 mfspr r12, SPRN_MAS2 552#ifdef CONFIG_PTE_64BIT 553 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */ 554#else 555 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ 556#endif 557 mtspr SPRN_MAS2, r12 558 559#ifdef CONFIG_PTE_64BIT 560 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */ 561 andi. r10, r11, _PAGE_DIRTY 562 bne 1f 563 li r10, MAS3_SW | MAS3_UW 564 andc r12, r12, r10 5651: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */ 566 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */ 567 mtspr SPRN_MAS3, r12 568BEGIN_MMU_FTR_SECTION 569 srwi r10, r13, 12 /* grab RPN[12:31] */ 570 mtspr SPRN_MAS7, r10 571END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) 572#else 573 li r10, (_PAGE_EXEC | _PAGE_PRESENT) 574 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */ 575 and r12, r11, r10 576 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ 577 slwi r10, r12, 1 578 or r10, r10, r12 579 iseleq r12, r12, r10 580 rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */ 581 mtspr SPRN_MAS3, r11 582#endif 583#ifdef CONFIG_E200 584 /* Round robin TLB1 entries assignment */ 585 mfspr r12, SPRN_MAS0 586 587 /* Extract TLB1CFG(NENTRY) */ 588 mfspr r11, SPRN_TLB1CFG 589 andi. r11, r11, 0xfff 590 591 /* Extract MAS0(NV) */ 592 andi. r13, r12, 0xfff 593 addi r13, r13, 1 594 cmpw 0, r13, r11 595 addi r12, r12, 1 596 597 /* check if we need to wrap */ 598 blt 7f 599 600 /* wrap back to first free tlbcam entry */ 601 lis r13, tlbcam_index@ha 602 lwz r13, tlbcam_index@l(r13) 603 rlwimi r12, r13, 0, 20, 31 6047: 605 mtspr SPRN_MAS0,r12 606#endif /* CONFIG_E200 */ 607 608 tlbwe 609 610 /* Done...restore registers and get out of here. */ 611 mfspr r11, SPRN_SPRG_RSCRATCH4 612 mtcr r11 613 mfspr r13, SPRN_SPRG_RSCRATCH3 614 mfspr r12, SPRN_SPRG_RSCRATCH2 615 mfspr r11, SPRN_SPRG_RSCRATCH1 616 mfspr r10, SPRN_SPRG_RSCRATCH0 617 rfi /* Force context change */ 618 619#ifdef CONFIG_SPE 620/* Note that the SPE support is closely modeled after the AltiVec 621 * support. Changes to one are likely to be applicable to the 622 * other! */ 623load_up_spe: 624/* 625 * Disable SPE for the task which had SPE previously, 626 * and save its SPE registers in its thread_struct. 627 * Enables SPE for use in the kernel on return. 628 * On SMP we know the SPE units are free, since we give it up every 629 * switch. -- Kumar 630 */ 631 mfmsr r5 632 oris r5,r5,MSR_SPE@h 633 mtmsr r5 /* enable use of SPE now */ 634 isync 635/* 636 * For SMP, we don't do lazy SPE switching because it just gets too 637 * horrendously complex, especially when a task switches from one CPU 638 * to another. Instead we call giveup_spe in switch_to. 639 */ 640#ifndef CONFIG_SMP 641 lis r3,last_task_used_spe@ha 642 lwz r4,last_task_used_spe@l(r3) 643 cmpi 0,r4,0 644 beq 1f 645 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */ 646 SAVE_32EVRS(0,r10,r4) 647 evxor evr10, evr10, evr10 /* clear out evr10 */ 648 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */ 649 li r5,THREAD_ACC 650 evstddx evr10, r4, r5 /* save off accumulator */ 651 lwz r5,PT_REGS(r4) 652 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) 653 lis r10,MSR_SPE@h 654 andc r4,r4,r10 /* disable SPE for previous task */ 655 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) 6561: 657#endif /* !CONFIG_SMP */ 658 /* enable use of SPE after return */ 659 oris r9,r9,MSR_SPE@h 660 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 661 li r4,1 662 li r10,THREAD_ACC 663 stw r4,THREAD_USED_SPE(r5) 664 evlddx evr4,r10,r5 665 evmra evr4,evr4 666 REST_32EVRS(0,r10,r5) 667#ifndef CONFIG_SMP 668 subi r4,r5,THREAD 669 stw r4,last_task_used_spe@l(r3) 670#endif /* !CONFIG_SMP */ 671 /* restore registers and return */ 6722: REST_4GPRS(3, r11) 673 lwz r10,_CCR(r11) 674 REST_GPR(1, r11) 675 mtcr r10 676 lwz r10,_LINK(r11) 677 mtlr r10 678 REST_GPR(10, r11) 679 mtspr SPRN_SRR1,r9 680 mtspr SPRN_SRR0,r12 681 REST_GPR(9, r11) 682 REST_GPR(12, r11) 683 lwz r11,GPR11(r11) 684 rfi 685 686/* 687 * SPE unavailable trap from kernel - print a message, but let 688 * the task use SPE in the kernel until it returns to user mode. 689 */ 690KernelSPE: 691 lwz r3,_MSR(r1) 692 oris r3,r3,MSR_SPE@h 693 stw r3,_MSR(r1) /* enable use of SPE after return */ 694#ifdef CONFIG_PRINTK 695 lis r3,87f@h 696 ori r3,r3,87f@l 697 mr r4,r2 /* current */ 698 lwz r5,_NIP(r1) 699 bl printk 700#endif 701 b ret_from_except 702#ifdef CONFIG_PRINTK 70387: .string "SPE used in kernel (task=%p, pc=%x) \n" 704#endif 705 .align 4,0 706 707#endif /* CONFIG_SPE */ 708 709/* 710 * Global functions 711 */ 712 713/* Adjust or setup IVORs for e200 */ 714_GLOBAL(__setup_e200_ivors) 715 li r3,DebugDebug@l 716 mtspr SPRN_IVOR15,r3 717 li r3,SPEUnavailable@l 718 mtspr SPRN_IVOR32,r3 719 li r3,SPEFloatingPointData@l 720 mtspr SPRN_IVOR33,r3 721 li r3,SPEFloatingPointRound@l 722 mtspr SPRN_IVOR34,r3 723 sync 724 blr 725 726/* Adjust or setup IVORs for e500v1/v2 */ 727_GLOBAL(__setup_e500_ivors) 728 li r3,DebugCrit@l 729 mtspr SPRN_IVOR15,r3 730 li r3,SPEUnavailable@l 731 mtspr SPRN_IVOR32,r3 732 li r3,SPEFloatingPointData@l 733 mtspr SPRN_IVOR33,r3 734 li r3,SPEFloatingPointRound@l 735 mtspr SPRN_IVOR34,r3 736 li r3,PerformanceMonitor@l 737 mtspr SPRN_IVOR35,r3 738 sync 739 blr 740 741/* Adjust or setup IVORs for e500mc */ 742_GLOBAL(__setup_e500mc_ivors) 743 li r3,DebugDebug@l 744 mtspr SPRN_IVOR15,r3 745 li r3,PerformanceMonitor@l 746 mtspr SPRN_IVOR35,r3 747 li r3,Doorbell@l 748 mtspr SPRN_IVOR36,r3 749 li r3,CriticalDoorbell@l 750 mtspr SPRN_IVOR37,r3 751 sync 752 blr 753 754/* 755 * extern void giveup_altivec(struct task_struct *prev) 756 * 757 * The e500 core does not have an AltiVec unit. 758 */ 759_GLOBAL(giveup_altivec) 760 blr 761 762#ifdef CONFIG_SPE 763/* 764 * extern void giveup_spe(struct task_struct *prev) 765 * 766 */ 767_GLOBAL(giveup_spe) 768 mfmsr r5 769 oris r5,r5,MSR_SPE@h 770 mtmsr r5 /* enable use of SPE now */ 771 isync 772 cmpi 0,r3,0 773 beqlr- /* if no previous owner, done */ 774 addi r3,r3,THREAD /* want THREAD of task */ 775 lwz r5,PT_REGS(r3) 776 cmpi 0,r5,0 777 SAVE_32EVRS(0, r4, r3) 778 evxor evr6, evr6, evr6 /* clear out evr6 */ 779 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ 780 li r4,THREAD_ACC 781 evstddx evr6, r4, r3 /* save off accumulator */ 782 mfspr r6,SPRN_SPEFSCR 783 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */ 784 beq 1f 785 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) 786 lis r3,MSR_SPE@h 787 andc r4,r4,r3 /* disable SPE for previous task */ 788 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) 7891: 790#ifndef CONFIG_SMP 791 li r5,0 792 lis r4,last_task_used_spe@ha 793 stw r5,last_task_used_spe@l(r4) 794#endif /* !CONFIG_SMP */ 795 blr 796#endif /* CONFIG_SPE */ 797 798/* 799 * extern void giveup_fpu(struct task_struct *prev) 800 * 801 * Not all FSL Book-E cores have an FPU 802 */ 803#ifndef CONFIG_PPC_FPU 804_GLOBAL(giveup_fpu) 805 blr 806#endif 807 808/* 809 * extern void abort(void) 810 * 811 * At present, this routine just applies a system reset. 812 */ 813_GLOBAL(abort) 814 li r13,0 815 mtspr SPRN_DBCR0,r13 /* disable all debug events */ 816 isync 817 mfmsr r13 818 ori r13,r13,MSR_DE@l /* Enable Debug Events */ 819 mtmsr r13 820 isync 821 mfspr r13,SPRN_DBCR0 822 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h 823 mtspr SPRN_DBCR0,r13 824 isync 825 826_GLOBAL(set_context) 827 828#ifdef CONFIG_BDI_SWITCH 829 /* Context switch the PTE pointer for the Abatron BDI2000. 830 * The PGDIR is the second parameter. 831 */ 832 lis r5, abatron_pteptrs@h 833 ori r5, r5, abatron_pteptrs@l 834 stw r4, 0x4(r5) 835#endif 836 mtspr SPRN_PID,r3 837 isync /* Force context change */ 838 blr 839 840_GLOBAL(flush_dcache_L1) 841 mfspr r3,SPRN_L1CFG0 842 843 rlwinm r5,r3,9,3 /* Extract cache block size */ 844 twlgti r5,1 /* Only 32 and 64 byte cache blocks 845 * are currently defined. 846 */ 847 li r4,32 848 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 849 * log2(number of ways) 850 */ 851 slw r5,r4,r5 /* r5 = cache block size */ 852 853 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 854 mulli r7,r7,13 /* An 8-way cache will require 13 855 * loads per set. 856 */ 857 slw r7,r7,r6 858 859 /* save off HID0 and set DCFA */ 860 mfspr r8,SPRN_HID0 861 ori r9,r8,HID0_DCFA@l 862 mtspr SPRN_HID0,r9 863 isync 864 865 lis r4,KERNELBASE@h 866 mtctr r7 867 8681: lwz r3,0(r4) /* Load... */ 869 add r4,r4,r5 870 bdnz 1b 871 872 msync 873 lis r4,KERNELBASE@h 874 mtctr r7 875 8761: dcbf 0,r4 /* ...and flush. */ 877 add r4,r4,r5 878 bdnz 1b 879 880 /* restore HID0 */ 881 mtspr SPRN_HID0,r8 882 isync 883 884 blr 885 886#ifdef CONFIG_SMP 887/* When we get here, r24 needs to hold the CPU # */ 888 .globl __secondary_start 889__secondary_start: 890 lis r3,__secondary_hold_acknowledge@h 891 ori r3,r3,__secondary_hold_acknowledge@l 892 stw r24,0(r3) 893 894 li r3,0 895 mr r4,r24 /* Why? */ 896 bl call_setup_cpu 897 898 lis r3,tlbcam_index@ha 899 lwz r3,tlbcam_index@l(r3) 900 mtctr r3 901 li r26,0 /* r26 safe? */ 902 903 /* Load each CAM entry */ 9041: mr r3,r26 905 bl loadcam_entry 906 addi r26,r26,1 907 bdnz 1b 908 909 /* get current_thread_info and current */ 910 lis r1,secondary_ti@ha 911 lwz r1,secondary_ti@l(r1) 912 lwz r2,TI_TASK(r1) 913 914 /* stack */ 915 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 916 li r0,0 917 stw r0,0(r1) 918 919 /* ptr to current thread */ 920 addi r4,r2,THREAD /* address of our thread_struct */ 921 mtspr SPRN_SPRG_THREAD,r4 922 923 /* Setup the defaults for TLB entries */ 924 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l 925 mtspr SPRN_MAS4,r4 926 927 /* Jump to start_secondary */ 928 lis r4,MSR_KERNEL@h 929 ori r4,r4,MSR_KERNEL@l 930 lis r3,start_secondary@h 931 ori r3,r3,start_secondary@l 932 mtspr SPRN_SRR0,r3 933 mtspr SPRN_SRR1,r4 934 sync 935 rfi 936 sync 937 938 .globl __secondary_hold_acknowledge 939__secondary_hold_acknowledge: 940 .long -1 941#endif 942 943/* 944 * We put a few things here that have to be page-aligned. This stuff 945 * goes at the beginning of the data segment, which is page-aligned. 946 */ 947 .data 948 .align 12 949 .globl sdata 950sdata: 951 .globl empty_zero_page 952empty_zero_page: 953 .space 4096 954 .globl swapper_pg_dir 955swapper_pg_dir: 956 .space PGD_TABLE_SIZE 957 958/* 959 * Room for two PTE pointers, usually the kernel and current user pointers 960 * to their respective root page table. 961 */ 962abatron_pteptrs: 963 .space 8 964