1/* Freescale Local Bus Controller 2 * 3 * Copyright (c) 2006-2007 Freescale Semiconductor 4 * 5 * Authors: Nick Spence <nick.spence@freescale.com>, 6 * Scott Wood <scottwood@freescale.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23#ifndef __ASM_FSL_LBC_H 24#define __ASM_FSL_LBC_H 25 26#include <linux/compiler.h> 27#include <linux/types.h> 28#include <linux/io.h> 29 30struct fsl_lbc_bank { 31 __be32 br; /**< Base Register */ 32#define BR_BA 0xFFFF8000 33#define BR_BA_SHIFT 15 34#define BR_PS 0x00001800 35#define BR_PS_SHIFT 11 36#define BR_PS_8 0x00000800 /* Port Size 8 bit */ 37#define BR_PS_16 0x00001000 /* Port Size 16 bit */ 38#define BR_PS_32 0x00001800 /* Port Size 32 bit */ 39#define BR_DECC 0x00000600 40#define BR_DECC_SHIFT 9 41#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */ 42#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */ 43#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */ 44#define BR_WP 0x00000100 45#define BR_WP_SHIFT 8 46#define BR_MSEL 0x000000E0 47#define BR_MSEL_SHIFT 5 48#define BR_MS_GPCM 0x00000000 /* GPCM */ 49#define BR_MS_FCM 0x00000020 /* FCM */ 50#define BR_MS_SDRAM 0x00000060 /* SDRAM */ 51#define BR_MS_UPMA 0x00000080 /* UPMA */ 52#define BR_MS_UPMB 0x000000A0 /* UPMB */ 53#define BR_MS_UPMC 0x000000C0 /* UPMC */ 54#define BR_V 0x00000001 55#define BR_V_SHIFT 0 56#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) 57 58 __be32 or; /**< Base Register */ 59#define OR0 0x5004 60#define OR1 0x500C 61#define OR2 0x5014 62#define OR3 0x501C 63#define OR4 0x5024 64#define OR5 0x502C 65#define OR6 0x5034 66#define OR7 0x503C 67 68#define OR_FCM_AM 0xFFFF8000 69#define OR_FCM_AM_SHIFT 15 70#define OR_FCM_BCTLD 0x00001000 71#define OR_FCM_BCTLD_SHIFT 12 72#define OR_FCM_PGS 0x00000400 73#define OR_FCM_PGS_SHIFT 10 74#define OR_FCM_CSCT 0x00000200 75#define OR_FCM_CSCT_SHIFT 9 76#define OR_FCM_CST 0x00000100 77#define OR_FCM_CST_SHIFT 8 78#define OR_FCM_CHT 0x00000080 79#define OR_FCM_CHT_SHIFT 7 80#define OR_FCM_SCY 0x00000070 81#define OR_FCM_SCY_SHIFT 4 82#define OR_FCM_SCY_1 0x00000010 83#define OR_FCM_SCY_2 0x00000020 84#define OR_FCM_SCY_3 0x00000030 85#define OR_FCM_SCY_4 0x00000040 86#define OR_FCM_SCY_5 0x00000050 87#define OR_FCM_SCY_6 0x00000060 88#define OR_FCM_SCY_7 0x00000070 89#define OR_FCM_RST 0x00000008 90#define OR_FCM_RST_SHIFT 3 91#define OR_FCM_TRLX 0x00000004 92#define OR_FCM_TRLX_SHIFT 2 93#define OR_FCM_EHTR 0x00000002 94#define OR_FCM_EHTR_SHIFT 1 95}; 96 97struct fsl_lbc_regs { 98 struct fsl_lbc_bank bank[12]; 99 u8 res0[0x8]; 100 __be32 mar; /**< UPM Address Register */ 101 u8 res1[0x4]; 102 __be32 mamr; /**< UPMA Mode Register */ 103#define MxMR_OP_NO (0 << 28) /**< normal operation */ 104#define MxMR_OP_WA (1 << 28) /**< write array */ 105#define MxMR_OP_RA (2 << 28) /**< read array */ 106#define MxMR_OP_RP (3 << 28) /**< run pattern */ 107#define MxMR_MAD 0x3f /**< machine address */ 108 __be32 mbmr; /**< UPMB Mode Register */ 109 __be32 mcmr; /**< UPMC Mode Register */ 110 u8 res2[0x8]; 111 __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ 112 __be32 mdr; /**< UPM Data Register */ 113 u8 res3[0x4]; 114 __be32 lsor; /**< Special Operation Initiation Register */ 115 __be32 lsdmr; /**< SDRAM Mode Register */ 116 u8 res4[0x8]; 117 __be32 lurt; /**< UPM Refresh Timer */ 118 __be32 lsrt; /**< SDRAM Refresh Timer */ 119 u8 res5[0x8]; 120 __be32 ltesr; /**< Transfer Error Status Register */ 121#define LTESR_BM 0x80000000 122#define LTESR_FCT 0x40000000 123#define LTESR_PAR 0x20000000 124#define LTESR_WP 0x04000000 125#define LTESR_ATMW 0x00800000 126#define LTESR_ATMR 0x00400000 127#define LTESR_CS 0x00080000 128#define LTESR_CC 0x00000001 129#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC) 130 __be32 ltedr; /**< Transfer Error Disable Register */ 131 __be32 lteir; /**< Transfer Error Interrupt Register */ 132 __be32 lteatr; /**< Transfer Error Attributes Register */ 133 __be32 ltear; /**< Transfer Error Address Register */ 134 u8 res6[0xC]; 135 __be32 lbcr; /**< Configuration Register */ 136#define LBCR_LDIS 0x80000000 137#define LBCR_LDIS_SHIFT 31 138#define LBCR_BCTLC 0x00C00000 139#define LBCR_BCTLC_SHIFT 22 140#define LBCR_AHD 0x00200000 141#define LBCR_LPBSE 0x00020000 142#define LBCR_LPBSE_SHIFT 17 143#define LBCR_EPAR 0x00010000 144#define LBCR_EPAR_SHIFT 16 145#define LBCR_BMT 0x0000FF00 146#define LBCR_BMT_SHIFT 8 147#define LBCR_INIT 0x00040000 148 __be32 lcrr; /**< Clock Ratio Register */ 149#define LCRR_DBYP 0x80000000 150#define LCRR_DBYP_SHIFT 31 151#define LCRR_BUFCMDC 0x30000000 152#define LCRR_BUFCMDC_SHIFT 28 153#define LCRR_ECL 0x03000000 154#define LCRR_ECL_SHIFT 24 155#define LCRR_EADC 0x00030000 156#define LCRR_EADC_SHIFT 16 157#define LCRR_CLKDIV 0x0000000F 158#define LCRR_CLKDIV_SHIFT 0 159 u8 res7[0x8]; 160 __be32 fmr; /**< Flash Mode Register */ 161#define FMR_CWTO 0x0000F000 162#define FMR_CWTO_SHIFT 12 163#define FMR_BOOT 0x00000800 164#define FMR_ECCM 0x00000100 165#define FMR_AL 0x00000030 166#define FMR_AL_SHIFT 4 167#define FMR_OP 0x00000003 168#define FMR_OP_SHIFT 0 169 __be32 fir; /**< Flash Instruction Register */ 170#define FIR_OP0 0xF0000000 171#define FIR_OP0_SHIFT 28 172#define FIR_OP1 0x0F000000 173#define FIR_OP1_SHIFT 24 174#define FIR_OP2 0x00F00000 175#define FIR_OP2_SHIFT 20 176#define FIR_OP3 0x000F0000 177#define FIR_OP3_SHIFT 16 178#define FIR_OP4 0x0000F000 179#define FIR_OP4_SHIFT 12 180#define FIR_OP5 0x00000F00 181#define FIR_OP5_SHIFT 8 182#define FIR_OP6 0x000000F0 183#define FIR_OP6_SHIFT 4 184#define FIR_OP7 0x0000000F 185#define FIR_OP7_SHIFT 0 186#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 187#define FIR_OP_CA 0x1 /* Issue current column address */ 188#define FIR_OP_PA 0x2 /* Issue current block+page address */ 189#define FIR_OP_UA 0x3 /* Issue user defined address */ 190#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ 191#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ 192#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ 193#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ 194#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 195#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 196#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 197#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 198#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 199#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 200#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 201#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */ 202 __be32 fcr; /**< Flash Command Register */ 203#define FCR_CMD0 0xFF000000 204#define FCR_CMD0_SHIFT 24 205#define FCR_CMD1 0x00FF0000 206#define FCR_CMD1_SHIFT 16 207#define FCR_CMD2 0x0000FF00 208#define FCR_CMD2_SHIFT 8 209#define FCR_CMD3 0x000000FF 210#define FCR_CMD3_SHIFT 0 211 __be32 fbar; /**< Flash Block Address Register */ 212#define FBAR_BLK 0x00FFFFFF 213 __be32 fpar; /**< Flash Page Address Register */ 214#define FPAR_SP_PI 0x00007C00 215#define FPAR_SP_PI_SHIFT 10 216#define FPAR_SP_MS 0x00000200 217#define FPAR_SP_CI 0x000001FF 218#define FPAR_SP_CI_SHIFT 0 219#define FPAR_LP_PI 0x0003F000 220#define FPAR_LP_PI_SHIFT 12 221#define FPAR_LP_MS 0x00000800 222#define FPAR_LP_CI 0x000007FF 223#define FPAR_LP_CI_SHIFT 0 224 __be32 fbcr; /**< Flash Byte Count Register */ 225#define FBCR_BC 0x00000FFF 226 u8 res11[0x8]; 227 u8 res8[0xF00]; 228}; 229 230/* 231 * FSL UPM routines 232 */ 233struct fsl_upm { 234 __be32 __iomem *mxmr; 235 int width; 236}; 237 238extern int fsl_lbc_find(phys_addr_t addr_base); 239extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm); 240 241/** 242 * fsl_upm_start_pattern - start UPM patterns execution 243 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find 244 * @pat_offset: UPM pattern offset for the command to be executed 245 * 246 * This routine programmes UPM so the next memory access that hits an UPM 247 * will trigger pattern execution, starting at pat_offset. 248 */ 249static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset) 250{ 251 clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset); 252} 253 254/** 255 * fsl_upm_end_pattern - end UPM patterns execution 256 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find 257 * 258 * This routine reverts UPM to normal operation mode. 259 */ 260static inline void fsl_upm_end_pattern(struct fsl_upm *upm) 261{ 262 clrbits32(upm->mxmr, MxMR_OP_RP); 263 264 while (in_be32(upm->mxmr) & MxMR_OP_RP) 265 cpu_relax(); 266} 267 268extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, 269 u32 mar); 270 271#endif /* __ASM_FSL_LBC_H */ 272