1/* 2 * Defines for the MSP interrupt controller. 3 * 4 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. 5 * Author: Carsten Langgaard, carstenl@mips.com 6 * 7 * ######################################################################## 8 * 9 * This program is free software; you can distribute it and/or modify it 10 * under the terms of the GNU General Public License (Version 2) as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 21 * 22 * ######################################################################## 23 */ 24 25#ifndef _MSP_SLP_INT_H 26#define _MSP_SLP_INT_H 27 28/* 29 * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded 30 * hierarchical system. The first level are the direct MIPS interrupts 31 * and are assigned the interrupt range 0-7. The second level is the SLM 32 * interrupt controller and is assigned the range 8-39. The third level 33 * comprises the Peripherial block, the PCI block, the PCI MSI block and 34 * the SLP. The PCI interrupts and the SLP errors are handled by the 35 * relevant subsystems so the core interrupt code needs only concern 36 * itself with the Peripheral block. These are assigned interrupts in 37 * the range 40-71. 38 */ 39 40/* 41 * IRQs directly connected to CPU 42 */ 43#define MSP_MIPS_INTBASE 0 44#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ 45#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ 46#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ 47#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ 48#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */ 49#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */ 50#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */ 51#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */ 52 53/* 54 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4) 55 * These defines should be tied to the register definition for the SLM 56 * interrupt routine. For now, just use hard-coded values. 57 */ 58#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8) 59#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0) 60 /* External interrupt 0 */ 61#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1) 62 /* External interrupt 1 */ 63#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2) 64 /* External interrupt 2 */ 65#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3) 66 /* External interrupt 3 */ 67/* Reserved 4-7 */ 68 69/* 70 ************************************************************************* 71 * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER * 72 * Some MSP produces have this interrupt labelled as Voice and some are * 73 * SEC mbox ... * 74 ************************************************************************* 75 */ 76#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8) 77 /* Cascaded IRQ for Voice Engine*/ 78#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9) 79 /* TDM interrupt */ 80#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10) 81 /* Cascaded IRQ for MAC 0 */ 82#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11) 83 /* Cascaded IRQ for MAC 1 */ 84#define MSP_INT_SEC (MSP_SLP_INTBASE + 12) 85 /* IRQ for security engine */ 86#define MSP_INT_PER (MSP_SLP_INTBASE + 13) 87 /* Peripheral interrupt */ 88#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14) 89 /* SLP timer 0 */ 90#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15) 91 /* SLP timer 1 */ 92#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16) 93 /* SLP timer 2 */ 94#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17) 95 /* Cascaded MIPS timer */ 96#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18) 97 /* Block Copy */ 98#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19) 99 /* UART 0 */ 100#define MSP_INT_PCI (MSP_SLP_INTBASE + 20) 101 /* PCI subsystem */ 102#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21) 103 /* PCI doorbell */ 104#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22) 105 /* PCI Message Signal */ 106#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23) 107 /* PCI Block Copy 0 */ 108#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24) 109 /* PCI Block Copy 1 */ 110#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25) 111 /* SLP error condition */ 112#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26) 113 /* IRQ for MAC2 */ 114/* Reserved 26-31 */ 115 116/* 117 * IRQs cascaded on SLP PER interrupt (MSP_INT_PER) 118 */ 119#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32) 120/* Reserved 0-1 */ 121#define MSP_INT_UART1 (MSP_PER_INTBASE + 2) 122 /* UART 1 */ 123/* Reserved 3-5 */ 124#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6) 125 /* 2-wire */ 126#define MSP_INT_TM0 (MSP_PER_INTBASE + 7) 127 /* Peripheral timer block out 0 */ 128#define MSP_INT_TM1 (MSP_PER_INTBASE + 8) 129 /* Peripheral timer block out 1 */ 130/* Reserved 9 */ 131#define MSP_INT_SPRX (MSP_PER_INTBASE + 10) 132 /* SPI RX complete */ 133#define MSP_INT_SPTX (MSP_PER_INTBASE + 11) 134 /* SPI TX complete */ 135#define MSP_INT_GPIO (MSP_PER_INTBASE + 12) 136 /* GPIO */ 137#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13) 138 /* Peripheral error */ 139/* Reserved 14-31 */ 140 141#endif /* !_MSP_SLP_INT_H */ 142