1/* 2 * Copyright (c) 2000-2006 PMC-Sierra INC. 3 * 4 * This program is free software; you can redistribute it 5 * and/or modify it under the terms of the GNU General 6 * Public License as published by the Free Software 7 * Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be 11 * useful, but WITHOUT ANY WARRANTY; without even the implied 12 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 13 * PURPOSE. See the GNU General Public License for more 14 * details. 15 * 16 * You should have received a copy of the GNU General Public 17 * License along with this program; if not, write to the Free 18 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 19 * 02139, USA. 20 * 21 * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND 22 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS 23 * SOFTWARE. 24 */ 25 26#ifndef _MSP_PCI_H_ 27#define _MSP_PCI_H_ 28 29#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220)) 30 31/* 32 * It is convenient to program the OATRAN register so that 33 * Athena virtual address space and PCI address space are 34 * the same. This is not a requirement, just a convenience. 35 * 36 * The only hard restrictions on the value of OATRAN is that 37 * OATRAN must not be programmed to allow translated memory 38 * addresses to fall within the lowest 512MB of 39 * PCI address space. This region is hardcoded 40 * for use as Athena PCI Host Controller target 41 * access memory space to the Athena's SDRAM. 42 * 43 * Note that OATRAN applies only to memory accesses, not 44 * to I/O accesses. 45 * 46 * To program OATRAN to make Athena virtual address space 47 * and PCI address space have the same values, OATRAN 48 * is to be programmed to 0xB8000000. The top seven 49 * bits of the value mimic the seven bits clipped off 50 * by the PCI Host controller. 51 * 52 * With OATRAN at the said value, when the CPU does 53 * an access to its virtual address at, say 0xB900_5000, 54 * the address appearing on the PCI bus will be 55 * 0xB900_5000. 56 * - Michael Penner 57 */ 58#define MSP_PCI_OATRAN 0xB8000000UL 59 60#define MSP_PCI_SPACE_BASE (MSP_PCI_OATRAN + 0x1002000UL) 61#define MSP_PCI_SPACE_SIZE (0x3000000UL - 0x2000) 62#define MSP_PCI_SPACE_END \ 63 (MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1) 64#define MSP_PCI_IOSPACE_BASE (MSP_PCI_OATRAN + 0x1001000UL) 65#define MSP_PCI_IOSPACE_SIZE 0x1000 66#define MSP_PCI_IOSPACE_END \ 67 (MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1) 68 69/* IRQ for PCI status interrupts */ 70#define PCI_STAT_IRQ 20 71 72#define QFLUSH_REG_1 0xB7F40000 73 74typedef volatile unsigned int pcireg; 75typedef void * volatile ppcireg; 76 77struct pci_block_copy 78{ 79 pcireg unused1; /* +0x00 */ 80 pcireg unused2; /* +0x04 */ 81 ppcireg unused3; /* +0x08 */ 82 ppcireg unused4; /* +0x0C */ 83 pcireg unused5; /* +0x10 */ 84 pcireg unused6; /* +0x14 */ 85 pcireg unused7; /* +0x18 */ 86 ppcireg unused8; /* +0x1C */ 87 ppcireg unused9; /* +0x20 */ 88 pcireg unusedA; /* +0x24 */ 89 ppcireg unusedB; /* +0x28 */ 90 ppcireg unusedC; /* +0x2C */ 91}; 92 93enum 94{ 95 config_device_vendor, /* 0 */ 96 config_status_command, /* 1 */ 97 config_class_revision, /* 2 */ 98 config_BIST_header_latency_cache, /* 3 */ 99 config_BAR0, /* 4 */ 100 config_BAR1, /* 5 */ 101 config_BAR2, /* 6 */ 102 config_not_used7, /* 7 */ 103 config_not_used8, /* 8 */ 104 config_not_used9, /* 9 */ 105 config_CIS, /* 10 */ 106 config_subsystem, /* 11 */ 107 config_not_used12, /* 12 */ 108 config_capabilities, /* 13 */ 109 config_not_used14, /* 14 */ 110 config_lat_grant_irq, /* 15 */ 111 config_message_control,/* 16 */ 112 config_message_addr, /* 17 */ 113 config_message_data, /* 18 */ 114 config_VPD_addr, /* 19 */ 115 config_VPD_data, /* 20 */ 116 config_maxregs /* 21 - number of registers */ 117}; 118 119struct msp_pci_regs 120{ 121 pcireg hop_unused_00; /* +0x00 */ 122 pcireg hop_unused_04; /* +0x04 */ 123 pcireg hop_unused_08; /* +0x08 */ 124 pcireg hop_unused_0C; /* +0x0C */ 125 pcireg hop_unused_10; /* +0x10 */ 126 pcireg hop_unused_14; /* +0x14 */ 127 pcireg hop_unused_18; /* +0x18 */ 128 pcireg hop_unused_1C; /* +0x1C */ 129 pcireg hop_unused_20; /* +0x20 */ 130 pcireg hop_unused_24; /* +0x24 */ 131 pcireg hop_unused_28; /* +0x28 */ 132 pcireg hop_unused_2C; /* +0x2C */ 133 pcireg hop_unused_30; /* +0x30 */ 134 pcireg hop_unused_34; /* +0x34 */ 135 pcireg if_control; /* +0x38 */ 136 pcireg oatran; /* +0x3C */ 137 pcireg reset_ctl; /* +0x40 */ 138 pcireg config_addr; /* +0x44 */ 139 pcireg hop_unused_48; /* +0x48 */ 140 pcireg msg_signaled_int_status; /* +0x4C */ 141 pcireg msg_signaled_int_mask; /* +0x50 */ 142 pcireg if_status; /* +0x54 */ 143 pcireg if_mask; /* +0x58 */ 144 pcireg hop_unused_5C; /* +0x5C */ 145 pcireg hop_unused_60; /* +0x60 */ 146 pcireg hop_unused_64; /* +0x64 */ 147 pcireg hop_unused_68; /* +0x68 */ 148 pcireg hop_unused_6C; /* +0x6C */ 149 pcireg hop_unused_70; /* +0x70 */ 150 151 struct pci_block_copy pci_bc[2] __attribute__((aligned(64))); 152 153 pcireg error_hdr1; /* +0xE0 */ 154 pcireg error_hdr2; /* +0xE4 */ 155 156 pcireg config[config_maxregs] __attribute__((aligned(256))); 157 158}; 159 160#define BPCI_CFGADDR_BUSNUM_SHF 16 161#define BPCI_CFGADDR_FUNCTNUM_SHF 8 162#define BPCI_CFGADDR_REGNUM_SHF 2 163#define BPCI_CFGADDR_ENABLE (1<<31) 164 165#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */ 166#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */ 167#define BPCI_IFCONTROL_CTO_SHF 12 /* Shift count for CTO bits */ 168#define BPCI_IFCONTROL_SE (1<<5) /* Enable exceptions on errors */ 169#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */ 170#define BPCI_IFCONTROL_CAP (1<<3) /* Enable capabilities */ 171#define BPCI_IFCONTROL_MMC_SHF 0 /* Shift count for MMC bits */ 172 173#define BPCI_IFSTATUS_MGT (1<<8) /* Master Grant timeout */ 174#define BPCI_IFSTATUS_MTT (1<<9) /* Master TRDY timeout */ 175#define BPCI_IFSTATUS_MRT (1<<10) /* Master retry timeout */ 176#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */ 177#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */ 178#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */ 179#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */ 180#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */ 181#define BPCI_IFSTATUS_RTO (1<<18) /* Retry time out */ 182#define BPCI_IFSTATUS_SER (1<<19) /* System error */ 183#define BPCI_IFSTATUS_PER (1<<20) /* Parity error */ 184#define BPCI_IFSTATUS_LCA (1<<21) /* Local CPU abort */ 185#define BPCI_IFSTATUS_MEM (1<<22) /* Memory prot. violation */ 186#define BPCI_IFSTATUS_ARB (1<<23) /* Arbiter timed out */ 187#define BPCI_IFSTATUS_STA (1<<27) /* Signaled target abort */ 188#define BPCI_IFSTATUS_TA (1<<28) /* Target abort */ 189#define BPCI_IFSTATUS_MA (1<<29) /* Master abort */ 190#define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */ 191#define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */ 192 193#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */ 194#define BPCI_RESETCTL_RT (1<<4) /* Release time */ 195#define BPCI_RESETCTL_CT (1<<8) /* Config time */ 196#define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */ 197#define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */ 198#define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */ 199 200extern struct msp_pci_regs msp_pci_regs 201 __attribute__((section(".register"))); 202extern unsigned long msp_pci_config_space 203 __attribute__((section(".register"))); 204 205#endif /* !_MSP_PCI_H_ */ 206