1/* 2 * Defines for the MSP interrupt controller. 3 * 4 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. 5 * Author: Carsten Langgaard, carstenl@mips.com 6 * 7 * ######################################################################## 8 * 9 * This program is free software; you can distribute it and/or modify it 10 * under the terms of the GNU General Public License (Version 2) as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 21 * 22 * ######################################################################## 23 */ 24 25#ifndef _MSP_CIC_INT_H 26#define _MSP_CIC_INT_H 27 28/* 29 * The PMC-Sierra CIC interrupts are all centrally managed by the 30 * CIC sub-system. 31 * We attempt to keep the interrupt numbers as consistent as possible 32 * across all of the MSP devices, but some differences will creep in ... 33 * The interrupts which are directly forwarded to the MIPS core interrupts 34 * are assigned interrupts in the range 0-7, interrupts cascaded through 35 * the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4 36 * (MSP_INT_CIC). Currently we don't really distinguish between VPE1 37 * and VPE0 (or thread contexts for that matter). Will have to fix. 38 * The PER interrupts are assigned interrupts in the range 40-71. 39*/ 40 41 42/* 43 * IRQs directly forwarded to the CPU 44 */ 45#define MSP_MIPS_INTBASE 0 46#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ 47#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ 48#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ 49#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ 50#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */ 51#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */ 52#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */ 53#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */ 54 55/* 56 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4) 57 * These defines should be tied to the register definitions for the CIC 58 * interrupt routine. For now, just use hard-coded values. 59 */ 60#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8) 61#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0) 62 /* External interrupt 0 */ 63#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1) 64 /* External interrupt 1 */ 65#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2) 66 /* External interrupt 2 */ 67#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3) 68 /* External interrupt 3 */ 69#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4) 70 /* CPU interface interrupt */ 71#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5) 72 /* External interrupt 4 */ 73#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6) 74 /* Cascaded IRQ for USB */ 75#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7) 76 /* Sec engine mailbox IRQ */ 77#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8) 78 /* External interrupt 5 */ 79#define MSP_INT_TDM (MSP_CIC_INTBASE + 9) 80 /* TDM interrupt */ 81#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10) 82 /* Cascaded IRQ for MAC 0 */ 83#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11) 84 /* Cascaded IRQ for MAC 1 */ 85#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12) 86 /* Cascaded IRQ for sec engine */ 87#define MSP_INT_PER (MSP_CIC_INTBASE + 13) 88 /* Peripheral interrupt */ 89#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14) 90 /* SLP timer 0 */ 91#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15) 92 /* SLP timer 1 */ 93#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16) 94 /* SLP timer 2 */ 95#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17) 96 /* VPE0 MIPS timer */ 97#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18) 98 /* Block Copy */ 99#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19) 100 /* UART 0 */ 101#define MSP_INT_PCI (MSP_CIC_INTBASE + 20) 102 /* PCI subsystem */ 103#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21) 104 /* External interrupt 5 */ 105#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22) 106 /* PCI Message Signal */ 107#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23) 108 /* Cascaded ADSL2+ SAR IRQ */ 109#define MSP_INT_DSL (MSP_CIC_INTBASE + 24) 110 /* ADSL2+ IRQ */ 111#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25) 112 /* SLP error condition */ 113#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26) 114 /* VPE1 MIPS timer */ 115#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27) 116 /* VPE0 Performance counter */ 117#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28) 118 /* VPE1 Performance counter */ 119#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29) 120 /* External interrupt 5 */ 121#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30) 122 /* VPE0 Software interrupt */ 123#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31) 124 /* VPE0 Software interrupt */ 125 126/* 127 * IRQs cascaded on CIC PER interrupt (MSP_INT_PER) 128 */ 129#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32) 130/* Reserved 0-1 */ 131#define MSP_INT_UART1 (MSP_PER_INTBASE + 2) 132 /* UART 1 */ 133/* Reserved 3-5 */ 134#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6) 135 /* 2-wire */ 136#define MSP_INT_TM0 (MSP_PER_INTBASE + 7) 137 /* Peripheral timer block out 0 */ 138#define MSP_INT_TM1 (MSP_PER_INTBASE + 8) 139 /* Peripheral timer block out 1 */ 140/* Reserved 9 */ 141#define MSP_INT_SPRX (MSP_PER_INTBASE + 10) 142 /* SPI RX complete */ 143#define MSP_INT_SPTX (MSP_PER_INTBASE + 11) 144 /* SPI TX complete */ 145#define MSP_INT_GPIO (MSP_PER_INTBASE + 12) 146 /* GPIO */ 147#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13) 148 /* Peripheral error */ 149/* Reserved 14-31 */ 150 151#endif /* !_MSP_CIC_INT_H */ 152