1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_GPIO_DEFS_H__ 29#define __CVMX_GPIO_DEFS_H__ 30 31#define CVMX_GPIO_BIT_CFGX(offset) \ 32 CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8)) 33#define CVMX_GPIO_BOOT_ENA \ 34 CVMX_ADD_IO_SEG(0x00010700000008A8ull) 35#define CVMX_GPIO_CLK_GENX(offset) \ 36 CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8)) 37#define CVMX_GPIO_DBG_ENA \ 38 CVMX_ADD_IO_SEG(0x00010700000008A0ull) 39#define CVMX_GPIO_INT_CLR \ 40 CVMX_ADD_IO_SEG(0x0001070000000898ull) 41#define CVMX_GPIO_RX_DAT \ 42 CVMX_ADD_IO_SEG(0x0001070000000880ull) 43#define CVMX_GPIO_TX_CLR \ 44 CVMX_ADD_IO_SEG(0x0001070000000890ull) 45#define CVMX_GPIO_TX_SET \ 46 CVMX_ADD_IO_SEG(0x0001070000000888ull) 47#define CVMX_GPIO_XBIT_CFGX(offset) \ 48 CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16) 49 50union cvmx_gpio_bit_cfgx { 51 uint64_t u64; 52 struct cvmx_gpio_bit_cfgx_s { 53 uint64_t reserved_15_63:49; 54 uint64_t clk_gen:1; 55 uint64_t clk_sel:2; 56 uint64_t fil_sel:4; 57 uint64_t fil_cnt:4; 58 uint64_t int_type:1; 59 uint64_t int_en:1; 60 uint64_t rx_xor:1; 61 uint64_t tx_oe:1; 62 } s; 63 struct cvmx_gpio_bit_cfgx_cn30xx { 64 uint64_t reserved_12_63:52; 65 uint64_t fil_sel:4; 66 uint64_t fil_cnt:4; 67 uint64_t int_type:1; 68 uint64_t int_en:1; 69 uint64_t rx_xor:1; 70 uint64_t tx_oe:1; 71 } cn30xx; 72 struct cvmx_gpio_bit_cfgx_cn30xx cn31xx; 73 struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; 74 struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; 75 struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; 76 struct cvmx_gpio_bit_cfgx_s cn52xx; 77 struct cvmx_gpio_bit_cfgx_s cn52xxp1; 78 struct cvmx_gpio_bit_cfgx_s cn56xx; 79 struct cvmx_gpio_bit_cfgx_s cn56xxp1; 80 struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; 81 struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; 82}; 83 84union cvmx_gpio_boot_ena { 85 uint64_t u64; 86 struct cvmx_gpio_boot_ena_s { 87 uint64_t reserved_12_63:52; 88 uint64_t boot_ena:4; 89 uint64_t reserved_0_7:8; 90 } s; 91 struct cvmx_gpio_boot_ena_s cn30xx; 92 struct cvmx_gpio_boot_ena_s cn31xx; 93 struct cvmx_gpio_boot_ena_s cn50xx; 94}; 95 96union cvmx_gpio_clk_genx { 97 uint64_t u64; 98 struct cvmx_gpio_clk_genx_s { 99 uint64_t reserved_32_63:32; 100 uint64_t n:32; 101 } s; 102 struct cvmx_gpio_clk_genx_s cn52xx; 103 struct cvmx_gpio_clk_genx_s cn52xxp1; 104 struct cvmx_gpio_clk_genx_s cn56xx; 105 struct cvmx_gpio_clk_genx_s cn56xxp1; 106}; 107 108union cvmx_gpio_dbg_ena { 109 uint64_t u64; 110 struct cvmx_gpio_dbg_ena_s { 111 uint64_t reserved_21_63:43; 112 uint64_t dbg_ena:21; 113 } s; 114 struct cvmx_gpio_dbg_ena_s cn30xx; 115 struct cvmx_gpio_dbg_ena_s cn31xx; 116 struct cvmx_gpio_dbg_ena_s cn50xx; 117}; 118 119union cvmx_gpio_int_clr { 120 uint64_t u64; 121 struct cvmx_gpio_int_clr_s { 122 uint64_t reserved_16_63:48; 123 uint64_t type:16; 124 } s; 125 struct cvmx_gpio_int_clr_s cn30xx; 126 struct cvmx_gpio_int_clr_s cn31xx; 127 struct cvmx_gpio_int_clr_s cn38xx; 128 struct cvmx_gpio_int_clr_s cn38xxp2; 129 struct cvmx_gpio_int_clr_s cn50xx; 130 struct cvmx_gpio_int_clr_s cn52xx; 131 struct cvmx_gpio_int_clr_s cn52xxp1; 132 struct cvmx_gpio_int_clr_s cn56xx; 133 struct cvmx_gpio_int_clr_s cn56xxp1; 134 struct cvmx_gpio_int_clr_s cn58xx; 135 struct cvmx_gpio_int_clr_s cn58xxp1; 136}; 137 138union cvmx_gpio_rx_dat { 139 uint64_t u64; 140 struct cvmx_gpio_rx_dat_s { 141 uint64_t reserved_24_63:40; 142 uint64_t dat:24; 143 } s; 144 struct cvmx_gpio_rx_dat_s cn30xx; 145 struct cvmx_gpio_rx_dat_s cn31xx; 146 struct cvmx_gpio_rx_dat_cn38xx { 147 uint64_t reserved_16_63:48; 148 uint64_t dat:16; 149 } cn38xx; 150 struct cvmx_gpio_rx_dat_cn38xx cn38xxp2; 151 struct cvmx_gpio_rx_dat_s cn50xx; 152 struct cvmx_gpio_rx_dat_cn38xx cn52xx; 153 struct cvmx_gpio_rx_dat_cn38xx cn52xxp1; 154 struct cvmx_gpio_rx_dat_cn38xx cn56xx; 155 struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; 156 struct cvmx_gpio_rx_dat_cn38xx cn58xx; 157 struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; 158}; 159 160union cvmx_gpio_tx_clr { 161 uint64_t u64; 162 struct cvmx_gpio_tx_clr_s { 163 uint64_t reserved_24_63:40; 164 uint64_t clr:24; 165 } s; 166 struct cvmx_gpio_tx_clr_s cn30xx; 167 struct cvmx_gpio_tx_clr_s cn31xx; 168 struct cvmx_gpio_tx_clr_cn38xx { 169 uint64_t reserved_16_63:48; 170 uint64_t clr:16; 171 } cn38xx; 172 struct cvmx_gpio_tx_clr_cn38xx cn38xxp2; 173 struct cvmx_gpio_tx_clr_s cn50xx; 174 struct cvmx_gpio_tx_clr_cn38xx cn52xx; 175 struct cvmx_gpio_tx_clr_cn38xx cn52xxp1; 176 struct cvmx_gpio_tx_clr_cn38xx cn56xx; 177 struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; 178 struct cvmx_gpio_tx_clr_cn38xx cn58xx; 179 struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; 180}; 181 182union cvmx_gpio_tx_set { 183 uint64_t u64; 184 struct cvmx_gpio_tx_set_s { 185 uint64_t reserved_24_63:40; 186 uint64_t set:24; 187 } s; 188 struct cvmx_gpio_tx_set_s cn30xx; 189 struct cvmx_gpio_tx_set_s cn31xx; 190 struct cvmx_gpio_tx_set_cn38xx { 191 uint64_t reserved_16_63:48; 192 uint64_t set:16; 193 } cn38xx; 194 struct cvmx_gpio_tx_set_cn38xx cn38xxp2; 195 struct cvmx_gpio_tx_set_s cn50xx; 196 struct cvmx_gpio_tx_set_cn38xx cn52xx; 197 struct cvmx_gpio_tx_set_cn38xx cn52xxp1; 198 struct cvmx_gpio_tx_set_cn38xx cn56xx; 199 struct cvmx_gpio_tx_set_cn38xx cn56xxp1; 200 struct cvmx_gpio_tx_set_cn38xx cn58xx; 201 struct cvmx_gpio_tx_set_cn38xx cn58xxp1; 202}; 203 204union cvmx_gpio_xbit_cfgx { 205 uint64_t u64; 206 struct cvmx_gpio_xbit_cfgx_s { 207 uint64_t reserved_12_63:52; 208 uint64_t fil_sel:4; 209 uint64_t fil_cnt:4; 210 uint64_t reserved_2_3:2; 211 uint64_t rx_xor:1; 212 uint64_t tx_oe:1; 213 } s; 214 struct cvmx_gpio_xbit_cfgx_s cn30xx; 215 struct cvmx_gpio_xbit_cfgx_s cn31xx; 216 struct cvmx_gpio_xbit_cfgx_s cn50xx; 217}; 218 219#endif 220