1/***************************************************************************/ 2 3/* 4 * linux/arch/m68knommu/platform/5206e/config.c 5 * 6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) 7 */ 8 9/***************************************************************************/ 10 11#include <linux/kernel.h> 12#include <linux/param.h> 13#include <linux/init.h> 14#include <linux/io.h> 15#include <asm/machdep.h> 16#include <asm/coldfire.h> 17#include <asm/mcfsim.h> 18#include <asm/mcfuart.h> 19#include <asm/mcfdma.h> 20 21/***************************************************************************/ 22 23static struct mcf_platform_uart m5206e_uart_platform[] = { 24 { 25 .mapbase = MCF_MBAR + MCFUART_BASE1, 26 .irq = 73, 27 }, 28 { 29 .mapbase = MCF_MBAR + MCFUART_BASE2, 30 .irq = 74, 31 }, 32 { }, 33}; 34 35static struct platform_device m5206e_uart = { 36 .name = "mcfuart", 37 .id = 0, 38 .dev.platform_data = m5206e_uart_platform, 39}; 40 41static struct platform_device *m5206e_devices[] __initdata = { 42 &m5206e_uart, 43}; 44 45/***************************************************************************/ 46 47static void __init m5206e_uart_init_line(int line, int irq) 48{ 49 if (line == 0) { 50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); 52 mcf_mapirq2imr(irq, MCFINTC_UART0); 53 } else if (line == 1) { 54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); 56 mcf_mapirq2imr(irq, MCFINTC_UART1); 57 } 58} 59 60static void __init m5206e_uarts_init(void) 61{ 62 const int nrlines = ARRAY_SIZE(m5206e_uart_platform); 63 int line; 64 65 for (line = 0; (line < nrlines); line++) 66 m5206e_uart_init_line(line, m5206e_uart_platform[line].irq); 67} 68 69/***************************************************************************/ 70 71static void __init m5206e_timers_init(void) 72{ 73 /* Timer1 is always used as system timer */ 74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, 75 MCF_MBAR + MCFSIM_TIMER1ICR); 76 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); 77 78#ifdef CONFIG_HIGHPROFILE 79 /* Timer2 is to be used as a high speed profile timer */ 80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, 81 MCF_MBAR + MCFSIM_TIMER2ICR); 82 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); 83#endif 84} 85 86/***************************************************************************/ 87 88void m5206e_cpu_reset(void) 89{ 90 local_irq_disable(); 91 /* Set watchdog to soft reset, and enabled */ 92 __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR); 93 for (;;) 94 /* wait for watchdog to timeout */; 95} 96 97/***************************************************************************/ 98 99void __init config_BSP(char *commandp, int size) 100{ 101#if defined(CONFIG_NETtel) 102 /* Copy command line from FLASH to local buffer... */ 103 memcpy(commandp, (char *) 0xf0004000, size); 104 commandp[size-1] = 0; 105#endif /* CONFIG_NETtel */ 106 107 mach_reset = m5206e_cpu_reset; 108 m5206e_timers_init(); 109 m5206e_uarts_init(); 110 111 /* Only support the external interrupts on their primary level */ 112 mcf_mapirq2imr(25, MCFINTC_EINT1); 113 mcf_mapirq2imr(28, MCFINTC_EINT4); 114 mcf_mapirq2imr(31, MCFINTC_EINT7); 115} 116 117/***************************************************************************/ 118 119static int __init init_BSP(void) 120{ 121 platform_add_devices(m5206e_devices, ARRAY_SIZE(m5206e_devices)); 122 return 0; 123} 124 125arch_initcall(init_BSP); 126 127/***************************************************************************/ 128