1 2/* 3 * 68360 Communication Processor Module. 4 * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> (mc68360) after: 5 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> (mpc8xx) 6 * 7 * This file contains structures and information for the communication 8 * processor channels. Some CPM control and status is available 9 * through the 68360 internal memory map. See include/asm/360_immap.h for details. 10 * This file is not a complete map of all of the 360 QUICC's capabilities 11 * 12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 13 * bytes of the DP RAM and relocates the I2C parameter area to the 14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors 15 * or other use. 16 */ 17#ifndef __CPM_360__ 18#define __CPM_360__ 19 20 21/* CPM Command register masks: */ 22#define CPM_CR_RST ((ushort)0x8000) 23#define CPM_CR_OPCODE ((ushort)0x0f00) 24#define CPM_CR_CHAN ((ushort)0x00f0) 25#define CPM_CR_FLG ((ushort)0x0001) 26 27/* CPM Command set (opcodes): */ 28#define CPM_CR_INIT_TRX ((ushort)0x0000) 29#define CPM_CR_INIT_RX ((ushort)0x0001) 30#define CPM_CR_INIT_TX ((ushort)0x0002) 31#define CPM_CR_HUNT_MODE ((ushort)0x0003) 32#define CPM_CR_STOP_TX ((ushort)0x0004) 33#define CPM_CR_GRSTOP_TX ((ushort)0x0005) 34#define CPM_CR_RESTART_TX ((ushort)0x0006) 35#define CPM_CR_CLOSE_RXBD ((ushort)0x0007) 36#define CPM_CR_SET_GADDR ((ushort)0x0008) 37#define CPM_CR_GCI_TIMEOUT ((ushort)0x0009) 38#define CPM_CR_GCI_ABORT ((ushort)0x000a) 39#define CPM_CR_RESET_BCS ((ushort)0x000a) 40 41/* CPM Channel numbers. */ 42#define CPM_CR_CH_SCC1 ((ushort)0x0000) 43#define CPM_CR_CH_SCC2 ((ushort)0x0004) 44#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */ 45#define CPM_CR_CH_TMR ((ushort)0x0005) 46#define CPM_CR_CH_SCC3 ((ushort)0x0008) 47#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */ 48#define CPM_CR_CH_IDMA1 ((ushort)0x0009) 49#define CPM_CR_CH_SCC4 ((ushort)0x000c) 50#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */ 51#define CPM_CR_CH_IDMA2 ((ushort)0x000d) 52 53 54#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) 55 56#if 1 /* mleslie: I dinna think we have any such restrictions on 57 * DP RAM aboard the 360 board - see the MC68360UM p.3-3 */ 58 59/* The dual ported RAM is multi-functional. Some areas can be (and are 60 * being) used for microcode. There is an area that can only be used 61 * as data ram for buffer descriptors, which is all we use right now. 62 * Currently the first 512 and last 256 bytes are used for microcode. 63 */ 64/* mleslie: The uCquicc board is using no extra microcode in DPRAM */ 65#define CPM_DATAONLY_BASE ((uint)0x0000) 66#define CPM_DATAONLY_SIZE ((uint)0x0800) 67#define CPM_DP_NOSPACE ((uint)0x7fffffff) 68 69#endif 70 71 72/* Export the base address of the communication processor registers 73 * and dual port ram. */ 74/* extern cpm360_t *cpmp; */ /* Pointer to comm processor */ 75extern QUICC *pquicc; 76uint m360_cpm_dpalloc(uint size); 77/* void *m360_cpm_hostalloc(uint size); */ 78void m360_cpm_setbrg(uint brg, uint rate); 79 80 81 82/* rx bd status/control bits */ 83#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ 84#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */ 85#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 86#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */ 87 88#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */ 89#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */ 90 91#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 92#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */ 93 94#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */ 95#define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */ 96 97#define BD_SC_BR ((ushort)0x0020) /* Break received */ 98#define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */ 99 100#define BD_SC_FR ((ushort)0x0010) /* Framing error */ 101#define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */ 102 103#define BD_SC_PR ((ushort)0x0008) /* Parity error */ 104#define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */ 105 106#define BD_SC_OV ((ushort)0x0002) /* Overrun */ 107#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ 108 109/* tx bd status/control bits (as differ from rx bd) */ 110#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 111#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ 112#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 113#define BD_SC_UN ((ushort)0x0002) /* Underrun */ 114 115 116 117 118/* Parameter RAM offsets. */ 119 120 121 122/* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM. 123 * In 2.0, we use a more structured C struct map of DPRAM, and so 124 * instead, we need only a parameter ram `slot' */ 125 126#define PRSLOT_SCC1 0 127#define PRSLOT_SCC2 1 128#define PRSLOT_SCC3 2 129#define PRSLOT_SMC1 2 130#define PRSLOT_SCC4 3 131#define PRSLOT_SMC2 3 132 133 134/* #define PROFF_SCC1 ((uint)0x0000) */ 135/* #define PROFF_SCC2 ((uint)0x0100) */ 136/* #define PROFF_SCC3 ((uint)0x0200) */ 137/* #define PROFF_SMC1 ((uint)0x0280) */ 138/* #define PROFF_SCC4 ((uint)0x0300) */ 139/* #define PROFF_SMC2 ((uint)0x0380) */ 140 141 142/* Define enough so I can at least use the serial port as a UART. 143 * The MBX uses SMC1 as the host serial port. 144 */ 145typedef struct smc_uart { 146 ushort smc_rbase; /* Rx Buffer descriptor base address */ 147 ushort smc_tbase; /* Tx Buffer descriptor base address */ 148 u_char smc_rfcr; /* Rx function code */ 149 u_char smc_tfcr; /* Tx function code */ 150 ushort smc_mrblr; /* Max receive buffer length */ 151 uint smc_rstate; /* Internal */ 152 uint smc_idp; /* Internal */ 153 ushort smc_rbptr; /* Internal */ 154 ushort smc_ibc; /* Internal */ 155 uint smc_rxtmp; /* Internal */ 156 uint smc_tstate; /* Internal */ 157 uint smc_tdp; /* Internal */ 158 ushort smc_tbptr; /* Internal */ 159 ushort smc_tbc; /* Internal */ 160 uint smc_txtmp; /* Internal */ 161 ushort smc_maxidl; /* Maximum idle characters */ 162 ushort smc_tmpidl; /* Temporary idle counter */ 163 ushort smc_brklen; /* Last received break length */ 164 ushort smc_brkec; /* rcv'd break condition counter */ 165 ushort smc_brkcr; /* xmt break count register */ 166 ushort smc_rmask; /* Temporary bit mask */ 167} smc_uart_t; 168 169/* Function code bits. 170*/ 171#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ 172 173/* SMC uart mode register. 174*/ 175#define SMCMR_REN ((ushort)0x0001) 176#define SMCMR_TEN ((ushort)0x0002) 177#define SMCMR_DM ((ushort)0x000c) 178#define SMCMR_SM_GCI ((ushort)0x0000) 179#define SMCMR_SM_UART ((ushort)0x0020) 180#define SMCMR_SM_TRANS ((ushort)0x0030) 181#define SMCMR_SM_MASK ((ushort)0x0030) 182#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ 183#define SMCMR_REVD SMCMR_PM_EVEN 184#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ 185#define SMCMR_BS SMCMR_PEN 186#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ 187#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ 188#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 189 190/* SMC2 as Centronics parallel printer. It is half duplex, in that 191 * it can only receive or transmit. The parameter ram values for 192 * each direction are either unique or properly overlap, so we can 193 * include them in one structure. 194 */ 195typedef struct smc_centronics { 196 ushort scent_rbase; 197 ushort scent_tbase; 198 u_char scent_cfcr; 199 u_char scent_smask; 200 ushort scent_mrblr; 201 uint scent_rstate; 202 uint scent_r_ptr; 203 ushort scent_rbptr; 204 ushort scent_r_cnt; 205 uint scent_rtemp; 206 uint scent_tstate; 207 uint scent_t_ptr; 208 ushort scent_tbptr; 209 ushort scent_t_cnt; 210 uint scent_ttemp; 211 ushort scent_max_sl; 212 ushort scent_sl_cnt; 213 ushort scent_character1; 214 ushort scent_character2; 215 ushort scent_character3; 216 ushort scent_character4; 217 ushort scent_character5; 218 ushort scent_character6; 219 ushort scent_character7; 220 ushort scent_character8; 221 ushort scent_rccm; 222 ushort scent_rccr; 223} smc_cent_t; 224 225/* Centronics Status Mask Register. 226*/ 227#define SMC_CENT_F ((u_char)0x08) 228#define SMC_CENT_PE ((u_char)0x04) 229#define SMC_CENT_S ((u_char)0x02) 230 231/* SMC Event and Mask register. 232*/ 233#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ 234#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ 235#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ 236#define SMCM_BSY ((unsigned char)0x04) 237#define SMCM_TX ((unsigned char)0x02) 238#define SMCM_RX ((unsigned char)0x01) 239 240/* Baud rate generators. 241*/ 242#define CPM_BRG_RST ((uint)0x00020000) 243#define CPM_BRG_EN ((uint)0x00010000) 244#define CPM_BRG_EXTC_INT ((uint)0x00000000) 245#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) 246#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) 247#define CPM_BRG_ATB ((uint)0x00002000) 248#define CPM_BRG_CD_MASK ((uint)0x00001ffe) 249#define CPM_BRG_DIV16 ((uint)0x00000001) 250 251/* SCCs. 252*/ 253#define SCC_GSMRH_IRP ((uint)0x00040000) 254#define SCC_GSMRH_GDE ((uint)0x00010000) 255#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) 256#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) 257#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) 258#define SCC_GSMRH_REVD ((uint)0x00002000) 259#define SCC_GSMRH_TRX ((uint)0x00001000) 260#define SCC_GSMRH_TTX ((uint)0x00000800) 261#define SCC_GSMRH_CDP ((uint)0x00000400) 262#define SCC_GSMRH_CTSP ((uint)0x00000200) 263#define SCC_GSMRH_CDS ((uint)0x00000100) 264#define SCC_GSMRH_CTSS ((uint)0x00000080) 265#define SCC_GSMRH_TFL ((uint)0x00000040) 266#define SCC_GSMRH_RFW ((uint)0x00000020) 267#define SCC_GSMRH_TXSY ((uint)0x00000010) 268#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) 269#define SCC_GSMRH_SYNL8 ((uint)0x00000008) 270#define SCC_GSMRH_SYNL4 ((uint)0x00000004) 271#define SCC_GSMRH_RTSM ((uint)0x00000002) 272#define SCC_GSMRH_RSYN ((uint)0x00000001) 273 274#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ 275#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) 276#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) 277#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) 278#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) 279#define SCC_GSMRL_TCI ((uint)0x10000000) 280#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) 281#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) 282#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) 283#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) 284#define SCC_GSMRL_RINV ((uint)0x02000000) 285#define SCC_GSMRL_TINV ((uint)0x01000000) 286#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) 287#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) 288#define SCC_GSMRL_TPL_48 ((uint)0x00800000) 289#define SCC_GSMRL_TPL_32 ((uint)0x00600000) 290#define SCC_GSMRL_TPL_16 ((uint)0x00400000) 291#define SCC_GSMRL_TPL_8 ((uint)0x00200000) 292#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) 293#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) 294#define SCC_GSMRL_TPP_01 ((uint)0x00100000) 295#define SCC_GSMRL_TPP_10 ((uint)0x00080000) 296#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) 297#define SCC_GSMRL_TEND ((uint)0x00040000) 298#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) 299#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) 300#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) 301#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) 302#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) 303#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) 304#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) 305#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) 306#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) 307#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) 308#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) 309#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) 310#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) 311#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) 312#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) 313#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) 314#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) 315#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) 316#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ 317#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) 318#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) 319#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) 320#define SCC_GSMRL_ENR ((uint)0x00000020) 321#define SCC_GSMRL_ENT ((uint)0x00000010) 322#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) 323#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) 324#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) 325#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) 326#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) 327#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) 328#define SCC_GSMRL_MODE_UART ((uint)0x00000004) 329#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) 330#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) 331#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) 332 333#define SCC_TODR_TOD ((ushort)0x8000) 334 335/* SCC Event and Mask register. 336*/ 337#define SCCM_TXE ((unsigned char)0x10) 338#define SCCM_BSY ((unsigned char)0x04) 339#define SCCM_TX ((unsigned char)0x02) 340#define SCCM_RX ((unsigned char)0x01) 341 342typedef struct scc_param { 343 ushort scc_rbase; /* Rx Buffer descriptor base address */ 344 ushort scc_tbase; /* Tx Buffer descriptor base address */ 345 u_char scc_rfcr; /* Rx function code */ 346 u_char scc_tfcr; /* Tx function code */ 347 ushort scc_mrblr; /* Max receive buffer length */ 348 uint scc_rstate; /* Internal */ 349 uint scc_idp; /* Internal */ 350 ushort scc_rbptr; /* Internal */ 351 ushort scc_ibc; /* Internal */ 352 uint scc_rxtmp; /* Internal */ 353 uint scc_tstate; /* Internal */ 354 uint scc_tdp; /* Internal */ 355 ushort scc_tbptr; /* Internal */ 356 ushort scc_tbc; /* Internal */ 357 uint scc_txtmp; /* Internal */ 358 uint scc_rcrc; /* Internal */ 359 uint scc_tcrc; /* Internal */ 360} sccp_t; 361 362 363/* Function code bits. 364 */ 365#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ 366#define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */ 367 368/* CPM Ethernet through SCC1. 369 */ 370typedef struct scc_enet { 371 sccp_t sen_genscc; 372 uint sen_cpres; /* Preset CRC */ 373 uint sen_cmask; /* Constant mask for CRC */ 374 uint sen_crcec; /* CRC Error counter */ 375 uint sen_alec; /* alignment error counter */ 376 uint sen_disfc; /* discard frame counter */ 377 ushort sen_pads; /* Tx short frame pad character */ 378 ushort sen_retlim; /* Retry limit threshold */ 379 ushort sen_retcnt; /* Retry limit counter */ 380 ushort sen_maxflr; /* maximum frame length register */ 381 ushort sen_minflr; /* minimum frame length register */ 382 ushort sen_maxd1; /* maximum DMA1 length */ 383 ushort sen_maxd2; /* maximum DMA2 length */ 384 ushort sen_maxd; /* Rx max DMA */ 385 ushort sen_dmacnt; /* Rx DMA counter */ 386 ushort sen_maxb; /* Max BD byte count */ 387 ushort sen_gaddr1; /* Group address filter */ 388 ushort sen_gaddr2; 389 ushort sen_gaddr3; 390 ushort sen_gaddr4; 391 uint sen_tbuf0data0; /* Save area 0 - current frame */ 392 uint sen_tbuf0data1; /* Save area 1 - current frame */ 393 uint sen_tbuf0rba; /* Internal */ 394 uint sen_tbuf0crc; /* Internal */ 395 ushort sen_tbuf0bcnt; /* Internal */ 396 ushort sen_paddrh; /* physical address (MSB) */ 397 ushort sen_paddrm; 398 ushort sen_paddrl; /* physical address (LSB) */ 399 ushort sen_pper; /* persistence */ 400 ushort sen_rfbdptr; /* Rx first BD pointer */ 401 ushort sen_tfbdptr; /* Tx first BD pointer */ 402 ushort sen_tlbdptr; /* Tx last BD pointer */ 403 uint sen_tbuf1data0; /* Save area 0 - current frame */ 404 uint sen_tbuf1data1; /* Save area 1 - current frame */ 405 uint sen_tbuf1rba; /* Internal */ 406 uint sen_tbuf1crc; /* Internal */ 407 ushort sen_tbuf1bcnt; /* Internal */ 408 ushort sen_txlen; /* Tx Frame length counter */ 409 ushort sen_iaddr1; /* Individual address filter */ 410 ushort sen_iaddr2; 411 ushort sen_iaddr3; 412 ushort sen_iaddr4; 413 ushort sen_boffcnt; /* Backoff counter */ 414 415 /* NOTE: Some versions of the manual have the following items 416 * incorrectly documented. Below is the proper order. 417 */ 418 ushort sen_taddrh; /* temp address (MSB) */ 419 ushort sen_taddrm; 420 ushort sen_taddrl; /* temp address (LSB) */ 421} scc_enet_t; 422 423 424 425#if defined(CONFIG_UCQUICC) 426/* uCquicc has the following signals connected to Ethernet: 427 * 68360 - lxt905 428 * PA0/RXD1 - rxd 429 * PA1/TXD1 - txd 430 * PA8/CLK1 - tclk 431 * PA9/CLK2 - rclk 432 * PC0/!RTS1 - t_en 433 * PC1/!CTS1 - col 434 * PC5/!CD1 - cd 435 */ 436#define PA_ENET_RXD PA_RXD1 437#define PA_ENET_TXD PA_TXD1 438#define PA_ENET_TCLK PA_CLK1 439#define PA_ENET_RCLK PA_CLK2 440#define PC_ENET_TENA PC_RTS1 441#define PC_ENET_CLSN PC_CTS1 442#define PC_ENET_RENA PC_CD1 443 444/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to 445 * SCC1. 446 */ 447#define SICR_ENET_MASK ((uint)0x000000ff) 448#define SICR_ENET_CLKRT ((uint)0x0000002c) 449 450#endif /* config_ucquicc */ 451 452 453#ifdef MBX 454/* Bits in parallel I/O port registers that have to be set/cleared 455 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique 456 * to the MBX860 board. Any two of the four available clocks could be 457 * used, and the MPC860 cookbook manual has an example using different 458 * clock pins. 459 */ 460#define PA_ENET_RXD ((ushort)0x0001) 461#define PA_ENET_TXD ((ushort)0x0002) 462#define PA_ENET_TCLK ((ushort)0x0200) 463#define PA_ENET_RCLK ((ushort)0x0800) 464#define PC_ENET_TENA ((ushort)0x0001) 465#define PC_ENET_CLSN ((ushort)0x0010) 466#define PC_ENET_RENA ((ushort)0x0020) 467 468/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 469 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 470 */ 471#define SICR_ENET_MASK ((uint)0x000000ff) 472#define SICR_ENET_CLKRT ((uint)0x0000003d) 473#endif 474 475#ifdef CONFIG_RPXLITE 476/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of 477 * this may be unique to the RPX-Lite configuration. 478 * Note TENA is on Port B. 479 */ 480#define PA_ENET_RXD ((ushort)0x0004) 481#define PA_ENET_TXD ((ushort)0x0008) 482#define PA_ENET_TCLK ((ushort)0x0200) 483#define PA_ENET_RCLK ((ushort)0x0800) 484#define PB_ENET_TENA ((uint)0x00002000) 485#define PC_ENET_CLSN ((ushort)0x0040) 486#define PC_ENET_RENA ((ushort)0x0080) 487 488#define SICR_ENET_MASK ((uint)0x0000ff00) 489#define SICR_ENET_CLKRT ((uint)0x00003d00) 490#endif 491 492#ifdef CONFIG_BSEIP 493/* This ENET stuff is for the MPC823 with ethernet on SCC2. 494 * This is unique to the BSE ip-Engine board. 495 */ 496#define PA_ENET_RXD ((ushort)0x0004) 497#define PA_ENET_TXD ((ushort)0x0008) 498#define PA_ENET_TCLK ((ushort)0x0100) 499#define PA_ENET_RCLK ((ushort)0x0200) 500#define PB_ENET_TENA ((uint)0x00002000) 501#define PC_ENET_CLSN ((ushort)0x0040) 502#define PC_ENET_RENA ((ushort)0x0080) 503 504/* BSE uses port B and C bits for PHY control also. 505*/ 506#define PB_BSE_POWERUP ((uint)0x00000004) 507#define PB_BSE_FDXDIS ((uint)0x00008000) 508#define PC_BSE_LOOPBACK ((ushort)0x0800) 509 510#define SICR_ENET_MASK ((uint)0x0000ff00) 511#define SICR_ENET_CLKRT ((uint)0x00002c00) 512#endif 513 514/* SCC Event register as used by Ethernet. 515*/ 516#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 517#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 518#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ 519#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ 520#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 521#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 522 523/* SCC Mode Register (PMSR) as used by Ethernet. 524*/ 525#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */ 526#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */ 527#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */ 528#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */ 529#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ 530#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */ 531#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ 532#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */ 533#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */ 534#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */ 535#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */ 536#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */ 537#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */ 538 539/* Buffer descriptor control/status used by Ethernet receive. 540*/ 541#define BD_ENET_RX_EMPTY ((ushort)0x8000) 542#define BD_ENET_RX_WRAP ((ushort)0x2000) 543#define BD_ENET_RX_INTR ((ushort)0x1000) 544#define BD_ENET_RX_LAST ((ushort)0x0800) 545#define BD_ENET_RX_FIRST ((ushort)0x0400) 546#define BD_ENET_RX_MISS ((ushort)0x0100) 547#define BD_ENET_RX_LG ((ushort)0x0020) 548#define BD_ENET_RX_NO ((ushort)0x0010) 549#define BD_ENET_RX_SH ((ushort)0x0008) 550#define BD_ENET_RX_CR ((ushort)0x0004) 551#define BD_ENET_RX_OV ((ushort)0x0002) 552#define BD_ENET_RX_CL ((ushort)0x0001) 553#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 554 555/* Buffer descriptor control/status used by Ethernet transmit. 556*/ 557#define BD_ENET_TX_READY ((ushort)0x8000) 558#define BD_ENET_TX_PAD ((ushort)0x4000) 559#define BD_ENET_TX_WRAP ((ushort)0x2000) 560#define BD_ENET_TX_INTR ((ushort)0x1000) 561#define BD_ENET_TX_LAST ((ushort)0x0800) 562#define BD_ENET_TX_TC ((ushort)0x0400) 563#define BD_ENET_TX_DEF ((ushort)0x0200) 564#define BD_ENET_TX_HB ((ushort)0x0100) 565#define BD_ENET_TX_LC ((ushort)0x0080) 566#define BD_ENET_TX_RL ((ushort)0x0040) 567#define BD_ENET_TX_RCMASK ((ushort)0x003c) 568#define BD_ENET_TX_UN ((ushort)0x0002) 569#define BD_ENET_TX_CSL ((ushort)0x0001) 570#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 571 572/* SCC as UART 573*/ 574typedef struct scc_uart { 575 sccp_t scc_genscc; 576 uint scc_res1; /* Reserved */ 577 uint scc_res2; /* Reserved */ 578 ushort scc_maxidl; /* Maximum idle chars */ 579 ushort scc_idlc; /* temp idle counter */ 580 ushort scc_brkcr; /* Break count register */ 581 ushort scc_parec; /* receive parity error counter */ 582 ushort scc_frmec; /* receive framing error counter */ 583 ushort scc_nosec; /* receive noise counter */ 584 ushort scc_brkec; /* receive break condition counter */ 585 ushort scc_brkln; /* last received break length */ 586 ushort scc_uaddr1; /* UART address character 1 */ 587 ushort scc_uaddr2; /* UART address character 2 */ 588 ushort scc_rtemp; /* Temp storage */ 589 ushort scc_toseq; /* Transmit out of sequence char */ 590 ushort scc_char1; /* control character 1 */ 591 ushort scc_char2; /* control character 2 */ 592 ushort scc_char3; /* control character 3 */ 593 ushort scc_char4; /* control character 4 */ 594 ushort scc_char5; /* control character 5 */ 595 ushort scc_char6; /* control character 6 */ 596 ushort scc_char7; /* control character 7 */ 597 ushort scc_char8; /* control character 8 */ 598 ushort scc_rccm; /* receive control character mask */ 599 ushort scc_rccr; /* receive control character register */ 600 ushort scc_rlbc; /* receive last break character */ 601} scc_uart_t; 602 603/* SCC Event and Mask registers when it is used as a UART. 604*/ 605#define UART_SCCM_GLR ((ushort)0x1000) 606#define UART_SCCM_GLT ((ushort)0x0800) 607#define UART_SCCM_AB ((ushort)0x0200) 608#define UART_SCCM_IDL ((ushort)0x0100) 609#define UART_SCCM_GRA ((ushort)0x0080) 610#define UART_SCCM_BRKE ((ushort)0x0040) 611#define UART_SCCM_BRKS ((ushort)0x0020) 612#define UART_SCCM_CCR ((ushort)0x0008) 613#define UART_SCCM_BSY ((ushort)0x0004) 614#define UART_SCCM_TX ((ushort)0x0002) 615#define UART_SCCM_RX ((ushort)0x0001) 616 617/* The SCC PMSR when used as a UART. 618*/ 619#define SCU_PMSR_FLC ((ushort)0x8000) 620#define SCU_PMSR_SL ((ushort)0x4000) 621#define SCU_PMSR_CL ((ushort)0x3000) 622#define SCU_PMSR_UM ((ushort)0x0c00) 623#define SCU_PMSR_FRZ ((ushort)0x0200) 624#define SCU_PMSR_RZS ((ushort)0x0100) 625#define SCU_PMSR_SYN ((ushort)0x0080) 626#define SCU_PMSR_DRT ((ushort)0x0040) 627#define SCU_PMSR_PEN ((ushort)0x0010) 628#define SCU_PMSR_RPM ((ushort)0x000c) 629#define SCU_PMSR_REVP ((ushort)0x0008) 630#define SCU_PMSR_TPM ((ushort)0x0003) 631#define SCU_PMSR_TEVP ((ushort)0x0003) 632 633/* CPM Transparent mode SCC. 634 */ 635typedef struct scc_trans { 636 sccp_t st_genscc; 637 uint st_cpres; /* Preset CRC */ 638 uint st_cmask; /* Constant mask for CRC */ 639} scc_trans_t; 640 641#define BD_SCC_TX_LAST ((ushort)0x0800) 642 643 644 645/* CPM interrupts. There are nearly 32 interrupts generated by CPM 646 * channels or devices. All of these are presented to the PPC core 647 * as a single interrupt. The CPM interrupt handler dispatches its 648 * own handlers, in a similar fashion to the PPC core handler. We 649 * use the table as defined in the manuals (i.e. no special high 650 * priority and SCC1 == SCCa, etc...). 651 */ 652/* #define CPMVEC_NR 32 */ 653/* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */ 654/* #define CPMVEC_SCC1 ((ushort)0x1e) */ 655/* #define CPMVEC_SCC2 ((ushort)0x1d) */ 656/* #define CPMVEC_SCC3 ((ushort)0x1c) */ 657/* #define CPMVEC_SCC4 ((ushort)0x1b) */ 658/* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */ 659/* #define CPMVEC_TIMER1 ((ushort)0x19) */ 660/* #define CPMVEC_PIO_PC13 ((ushort)0x18) */ 661/* #define CPMVEC_PIO_PC12 ((ushort)0x17) */ 662/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */ 663/* #define CPMVEC_IDMA1 ((ushort)0x15) */ 664/* #define CPMVEC_IDMA2 ((ushort)0x14) */ 665/* #define CPMVEC_TIMER2 ((ushort)0x12) */ 666/* #define CPMVEC_RISCTIMER ((ushort)0x11) */ 667/* #define CPMVEC_I2C ((ushort)0x10) */ 668/* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */ 669/* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */ 670/* #define CPMVEC_TIMER3 ((ushort)0x0c) */ 671/* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */ 672/* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */ 673/* #define CPMVEC_PIO_PC7 ((ushort)0x09) */ 674/* #define CPMVEC_TIMER4 ((ushort)0x07) */ 675/* #define CPMVEC_PIO_PC6 ((ushort)0x06) */ 676/* #define CPMVEC_SPI ((ushort)0x05) */ 677/* #define CPMVEC_SMC1 ((ushort)0x04) */ 678/* #define CPMVEC_SMC2 ((ushort)0x03) */ 679/* #define CPMVEC_PIO_PC5 ((ushort)0x02) */ 680/* #define CPMVEC_PIO_PC4 ((ushort)0x01) */ 681/* #define CPMVEC_ERROR ((ushort)0x00) */ 682 683extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); 684 685/* CPM interrupt configuration vector. 686*/ 687#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ 688#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 689#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ 690#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ 691#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ 692#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 693#define CICR_IEN ((uint)0x00000080) /* Int. enable */ 694#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 695#endif /* __CPM_360__ */ 696