1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003-2006 Silicon Graphics, Inc. All Rights Reserved. 7 */ 8 9#include <linux/types.h> 10#include <linux/interrupt.h> 11#include <linux/slab.h> 12#include <linux/pci.h> 13#include <asm/sn/sn_sal.h> 14#include <asm/sn/addrs.h> 15#include <asm/sn/io.h> 16#include <asm/sn/pcidev.h> 17#include <asm/sn/pcibus_provider_defs.h> 18#include <asm/sn/tioce_provider.h> 19 20/* 21 * 1/26/2006 22 * 23 * WAR for SGI PV 944642. For revA TIOCE, need to use the following recipe 24 * (taken from the above PV) before and after accessing tioce internal MMR's 25 * to avoid tioce lockups. 26 * 27 * The recipe as taken from the PV: 28 * 29 * if(mmr address < 0x45000) { 30 * if(mmr address == 0 or 0x80) 31 * mmr wrt or read address 0xc0 32 * else if(mmr address == 0x148 or 0x200) 33 * mmr wrt or read address 0x28 34 * else 35 * mmr wrt or read address 0x158 36 * 37 * do desired mmr access (rd or wrt) 38 * 39 * if(mmr address == 0x100) 40 * mmr wrt or read address 0x38 41 * mmr wrt or read address 0xb050 42 * } else 43 * do desired mmr access 44 * 45 * According to hw, we can use reads instead of writes to the above address 46 * 47 * Note this WAR can only to be used for accessing internal MMR's in the 48 * TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff. This includes the 49 * "Local CE Registers and Memories" and "PCI Compatible Config Space" address 50 * spaces from table 2-1 of the "CE Programmer's Reference Overview" document. 51 * 52 * All registers defined in struct tioce will meet that criteria. 53 */ 54 55static void inline 56tioce_mmr_war_pre(struct tioce_kernel *kern, void __iomem *mmr_addr) 57{ 58 u64 mmr_base; 59 u64 mmr_offset; 60 61 if (kern->ce_common->ce_rev != TIOCE_REV_A) 62 return; 63 64 mmr_base = kern->ce_common->ce_pcibus.bs_base; 65 mmr_offset = (unsigned long)mmr_addr - mmr_base; 66 67 if (mmr_offset < 0x45000) { 68 u64 mmr_war_offset; 69 70 if (mmr_offset == 0 || mmr_offset == 0x80) 71 mmr_war_offset = 0xc0; 72 else if (mmr_offset == 0x148 || mmr_offset == 0x200) 73 mmr_war_offset = 0x28; 74 else 75 mmr_war_offset = 0x158; 76 77 readq_relaxed((void __iomem *)(mmr_base + mmr_war_offset)); 78 } 79} 80 81static void inline 82tioce_mmr_war_post(struct tioce_kernel *kern, void __iomem *mmr_addr) 83{ 84 u64 mmr_base; 85 u64 mmr_offset; 86 87 if (kern->ce_common->ce_rev != TIOCE_REV_A) 88 return; 89 90 mmr_base = kern->ce_common->ce_pcibus.bs_base; 91 mmr_offset = (unsigned long)mmr_addr - mmr_base; 92 93 if (mmr_offset < 0x45000) { 94 if (mmr_offset == 0x100) 95 readq_relaxed((void __iomem *)(mmr_base + 0x38)); 96 readq_relaxed((void __iomem *)(mmr_base + 0xb050)); 97 } 98} 99 100/* load mmr contents into a variable */ 101#define tioce_mmr_load(kern, mmrp, varp) do {\ 102 tioce_mmr_war_pre(kern, mmrp); \ 103 *(varp) = readq_relaxed(mmrp); \ 104 tioce_mmr_war_post(kern, mmrp); \ 105} while (0) 106 107/* store variable contents into mmr */ 108#define tioce_mmr_store(kern, mmrp, varp) do {\ 109 tioce_mmr_war_pre(kern, mmrp); \ 110 writeq(*varp, mmrp); \ 111 tioce_mmr_war_post(kern, mmrp); \ 112} while (0) 113 114/* store immediate value into mmr */ 115#define tioce_mmr_storei(kern, mmrp, val) do {\ 116 tioce_mmr_war_pre(kern, mmrp); \ 117 writeq(val, mmrp); \ 118 tioce_mmr_war_post(kern, mmrp); \ 119} while (0) 120 121/* set bits (immediate value) into mmr */ 122#define tioce_mmr_seti(kern, mmrp, bits) do {\ 123 u64 tmp; \ 124 tioce_mmr_load(kern, mmrp, &tmp); \ 125 tmp |= (bits); \ 126 tioce_mmr_store(kern, mmrp, &tmp); \ 127} while (0) 128 129/* clear bits (immediate value) into mmr */ 130#define tioce_mmr_clri(kern, mmrp, bits) do { \ 131 u64 tmp; \ 132 tioce_mmr_load(kern, mmrp, &tmp); \ 133 tmp &= ~(bits); \ 134 tioce_mmr_store(kern, mmrp, &tmp); \ 135} while (0) 136 137/** 138 * Bus address ranges for the 5 flavors of TIOCE DMA 139 */ 140 141#define TIOCE_D64_MIN 0x8000000000000000UL 142#define TIOCE_D64_MAX 0xffffffffffffffffUL 143#define TIOCE_D64_ADDR(a) ((a) >= TIOCE_D64_MIN) 144 145#define TIOCE_D32_MIN 0x0000000080000000UL 146#define TIOCE_D32_MAX 0x00000000ffffffffUL 147#define TIOCE_D32_ADDR(a) ((a) >= TIOCE_D32_MIN && (a) <= TIOCE_D32_MAX) 148 149#define TIOCE_M32_MIN 0x0000000000000000UL 150#define TIOCE_M32_MAX 0x000000007fffffffUL 151#define TIOCE_M32_ADDR(a) ((a) >= TIOCE_M32_MIN && (a) <= TIOCE_M32_MAX) 152 153#define TIOCE_M40_MIN 0x0000004000000000UL 154#define TIOCE_M40_MAX 0x0000007fffffffffUL 155#define TIOCE_M40_ADDR(a) ((a) >= TIOCE_M40_MIN && (a) <= TIOCE_M40_MAX) 156 157#define TIOCE_M40S_MIN 0x0000008000000000UL 158#define TIOCE_M40S_MAX 0x000000ffffffffffUL 159#define TIOCE_M40S_ADDR(a) ((a) >= TIOCE_M40S_MIN && (a) <= TIOCE_M40S_MAX) 160 161/* 162 * ATE manipulation macros. 163 */ 164 165#define ATE_PAGESHIFT(ps) (__ffs(ps)) 166#define ATE_PAGEMASK(ps) ((ps)-1) 167 168#define ATE_PAGE(x, ps) ((x) >> ATE_PAGESHIFT(ps)) 169#define ATE_NPAGES(start, len, pagesize) \ 170 (ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1) 171 172#define ATE_VALID(ate) ((ate) & (1UL << 63)) 173#define ATE_MAKE(addr, ps, msi) \ 174 (((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63) | ((msi)?(1UL << 62):0)) 175 176/* 177 * Flavors of ate-based mapping supported by tioce_alloc_map() 178 */ 179 180#define TIOCE_ATE_M32 1 181#define TIOCE_ATE_M40 2 182#define TIOCE_ATE_M40S 3 183 184#define KB(x) ((u64)(x) << 10) 185#define MB(x) ((u64)(x) << 20) 186#define GB(x) ((u64)(x) << 30) 187 188/** 189 * tioce_dma_d64 - create a DMA mapping using 64-bit direct mode 190 * @ct_addr: system coretalk address 191 * 192 * Map @ct_addr into 64-bit CE bus space. No device context is necessary 193 * and no CE mapping are consumed. 194 * 195 * Bits 53:0 come from the coretalk address. The remaining bits are set as 196 * follows: 197 * 198 * 63 - must be 1 to indicate d64 mode to CE hardware 199 * 62 - barrier bit ... controlled with tioce_dma_barrier() 200 * 61 - msi bit ... specified through dma_flags 201 * 60:54 - reserved, MBZ 202 */ 203static u64 204tioce_dma_d64(unsigned long ct_addr, int dma_flags) 205{ 206 u64 bus_addr; 207 208 bus_addr = ct_addr | (1UL << 63); 209 if (dma_flags & SN_DMA_MSI) 210 bus_addr |= (1UL << 61); 211 212 return bus_addr; 213} 214 215/** 216 * pcidev_to_tioce - return misc ce related pointers given a pci_dev 217 * @pci_dev: pci device context 218 * @base: ptr to store struct tioce_mmr * for the CE holding this device 219 * @kernel: ptr to store struct tioce_kernel * for the CE holding this device 220 * @port: ptr to store the CE port number that this device is on 221 * 222 * Return pointers to various CE-related structures for the CE upstream of 223 * @pci_dev. 224 */ 225static inline void 226pcidev_to_tioce(struct pci_dev *pdev, struct tioce __iomem **base, 227 struct tioce_kernel **kernel, int *port) 228{ 229 struct pcidev_info *pcidev_info; 230 struct tioce_common *ce_common; 231 struct tioce_kernel *ce_kernel; 232 233 pcidev_info = SN_PCIDEV_INFO(pdev); 234 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; 235 ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private; 236 237 if (base) 238 *base = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base; 239 if (kernel) 240 *kernel = ce_kernel; 241 242 /* 243 * we use port as a zero-based value internally, even though the 244 * documentation is 1-based. 245 */ 246 if (port) 247 *port = 248 (pdev->bus->number < ce_kernel->ce_port1_secondary) ? 0 : 1; 249} 250 251/** 252 * tioce_alloc_map - Given a coretalk address, map it to pcie bus address 253 * space using one of the various ATE-based address modes. 254 * @ce_kern: tioce context 255 * @type: map mode to use 256 * @port: 0-based port that the requesting device is downstream of 257 * @ct_addr: the coretalk address to map 258 * @len: number of bytes to map 259 * 260 * Given the addressing type, set up various parameters that define the 261 * ATE pool to use. Search for a contiguous block of entries to cover the 262 * length, and if enough resources exist, fill in the ATEs and construct a 263 * tioce_dmamap struct to track the mapping. 264 */ 265static u64 266tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port, 267 u64 ct_addr, int len, int dma_flags) 268{ 269 int i; 270 int j; 271 int first; 272 int last; 273 int entries; 274 int nates; 275 u64 pagesize; 276 int msi_capable, msi_wanted; 277 u64 *ate_shadow; 278 u64 __iomem *ate_reg; 279 u64 addr; 280 struct tioce __iomem *ce_mmr; 281 u64 bus_base; 282 struct tioce_dmamap *map; 283 284 ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base; 285 286 switch (type) { 287 case TIOCE_ATE_M32: 288 /* 289 * The first 64 entries of the ate3240 pool are dedicated to 290 * super-page (TIOCE_ATE_M40S) mode. 291 */ 292 first = 64; 293 entries = TIOCE_NUM_M3240_ATES - 64; 294 ate_shadow = ce_kern->ce_ate3240_shadow; 295 ate_reg = ce_mmr->ce_ure_ate3240; 296 pagesize = ce_kern->ce_ate3240_pagesize; 297 bus_base = TIOCE_M32_MIN; 298 msi_capable = 1; 299 break; 300 case TIOCE_ATE_M40: 301 first = 0; 302 entries = TIOCE_NUM_M40_ATES; 303 ate_shadow = ce_kern->ce_ate40_shadow; 304 ate_reg = ce_mmr->ce_ure_ate40; 305 pagesize = MB(64); 306 bus_base = TIOCE_M40_MIN; 307 msi_capable = 0; 308 break; 309 case TIOCE_ATE_M40S: 310 /* 311 * ate3240 entries 0-31 are dedicated to port1 super-page 312 * mappings. ate3240 entries 32-63 are dedicated to port2. 313 */ 314 first = port * 32; 315 entries = 32; 316 ate_shadow = ce_kern->ce_ate3240_shadow; 317 ate_reg = ce_mmr->ce_ure_ate3240; 318 pagesize = GB(16); 319 bus_base = TIOCE_M40S_MIN; 320 msi_capable = 0; 321 break; 322 default: 323 return 0; 324 } 325 326 msi_wanted = dma_flags & SN_DMA_MSI; 327 if (msi_wanted && !msi_capable) 328 return 0; 329 330 nates = ATE_NPAGES(ct_addr, len, pagesize); 331 if (nates > entries) 332 return 0; 333 334 last = first + entries - nates; 335 for (i = first; i <= last; i++) { 336 if (ATE_VALID(ate_shadow[i])) 337 continue; 338 339 for (j = i; j < i + nates; j++) 340 if (ATE_VALID(ate_shadow[j])) 341 break; 342 343 if (j >= i + nates) 344 break; 345 } 346 347 if (i > last) 348 return 0; 349 350 map = kzalloc(sizeof(struct tioce_dmamap), GFP_ATOMIC); 351 if (!map) 352 return 0; 353 354 addr = ct_addr; 355 for (j = 0; j < nates; j++) { 356 u64 ate; 357 358 ate = ATE_MAKE(addr, pagesize, msi_wanted); 359 ate_shadow[i + j] = ate; 360 tioce_mmr_storei(ce_kern, &ate_reg[i + j], ate); 361 addr += pagesize; 362 } 363 364 map->refcnt = 1; 365 map->nbytes = nates * pagesize; 366 map->ct_start = ct_addr & ~ATE_PAGEMASK(pagesize); 367 map->pci_start = bus_base + (i * pagesize); 368 map->ate_hw = &ate_reg[i]; 369 map->ate_shadow = &ate_shadow[i]; 370 map->ate_count = nates; 371 372 list_add(&map->ce_dmamap_list, &ce_kern->ce_dmamap_list); 373 374 return (map->pci_start + (ct_addr - map->ct_start)); 375} 376 377/** 378 * tioce_dma_d32 - create a DMA mapping using 32-bit direct mode 379 * @pdev: linux pci_dev representing the function 380 * @paddr: system physical address 381 * 382 * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info. 383 */ 384static u64 385tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr, int dma_flags) 386{ 387 int dma_ok; 388 int port; 389 struct tioce __iomem *ce_mmr; 390 struct tioce_kernel *ce_kern; 391 u64 ct_upper; 392 u64 ct_lower; 393 dma_addr_t bus_addr; 394 395 if (dma_flags & SN_DMA_MSI) 396 return 0; 397 398 ct_upper = ct_addr & ~0x3fffffffUL; 399 ct_lower = ct_addr & 0x3fffffffUL; 400 401 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port); 402 403 if (ce_kern->ce_port[port].dirmap_refcnt == 0) { 404 u64 tmp; 405 406 ce_kern->ce_port[port].dirmap_shadow = ct_upper; 407 tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port], 408 ct_upper); 409 tmp = ce_mmr->ce_ure_dir_map[port]; 410 dma_ok = 1; 411 } else 412 dma_ok = (ce_kern->ce_port[port].dirmap_shadow == ct_upper); 413 414 if (dma_ok) { 415 ce_kern->ce_port[port].dirmap_refcnt++; 416 bus_addr = TIOCE_D32_MIN + ct_lower; 417 } else 418 bus_addr = 0; 419 420 return bus_addr; 421} 422 423/** 424 * tioce_dma_barrier - swizzle a TIOCE bus address to include or exclude 425 * the barrier bit. 426 * @bus_addr: bus address to swizzle 427 * 428 * Given a TIOCE bus address, set the appropriate bit to indicate barrier 429 * attributes. 430 */ 431static u64 432tioce_dma_barrier(u64 bus_addr, int on) 433{ 434 u64 barrier_bit; 435 436 /* barrier not supported in M40/M40S mode */ 437 if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr)) 438 return bus_addr; 439 440 if (TIOCE_D64_ADDR(bus_addr)) 441 barrier_bit = (1UL << 62); 442 else /* must be m32 or d32 */ 443 barrier_bit = (1UL << 30); 444 445 return (on) ? (bus_addr | barrier_bit) : (bus_addr & ~barrier_bit); 446} 447 448/** 449 * tioce_dma_unmap - release CE mapping resources 450 * @pdev: linux pci_dev representing the function 451 * @bus_addr: bus address returned by an earlier tioce_dma_map 452 * @dir: mapping direction (unused) 453 * 454 * Locate mapping resources associated with @bus_addr and release them. 455 * For mappings created using the direct modes there are no resources 456 * to release. 457 */ 458void 459tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir) 460{ 461 int i; 462 int port; 463 struct tioce_kernel *ce_kern; 464 struct tioce __iomem *ce_mmr; 465 unsigned long flags; 466 467 bus_addr = tioce_dma_barrier(bus_addr, 0); 468 pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port); 469 470 /* nothing to do for D64 */ 471 472 if (TIOCE_D64_ADDR(bus_addr)) 473 return; 474 475 spin_lock_irqsave(&ce_kern->ce_lock, flags); 476 477 if (TIOCE_D32_ADDR(bus_addr)) { 478 if (--ce_kern->ce_port[port].dirmap_refcnt == 0) { 479 ce_kern->ce_port[port].dirmap_shadow = 0; 480 tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port], 481 0); 482 } 483 } else { 484 struct tioce_dmamap *map; 485 486 list_for_each_entry(map, &ce_kern->ce_dmamap_list, 487 ce_dmamap_list) { 488 u64 last; 489 490 last = map->pci_start + map->nbytes - 1; 491 if (bus_addr >= map->pci_start && bus_addr <= last) 492 break; 493 } 494 495 if (&map->ce_dmamap_list == &ce_kern->ce_dmamap_list) { 496 printk(KERN_WARNING 497 "%s: %s - no map found for bus_addr 0x%llx\n", 498 __func__, pci_name(pdev), bus_addr); 499 } else if (--map->refcnt == 0) { 500 for (i = 0; i < map->ate_count; i++) { 501 map->ate_shadow[i] = 0; 502 tioce_mmr_storei(ce_kern, &map->ate_hw[i], 0); 503 } 504 505 list_del(&map->ce_dmamap_list); 506 kfree(map); 507 } 508 } 509 510 spin_unlock_irqrestore(&ce_kern->ce_lock, flags); 511} 512 513/** 514 * tioce_do_dma_map - map pages for PCI DMA 515 * @pdev: linux pci_dev representing the function 516 * @paddr: host physical address to map 517 * @byte_count: bytes to map 518 * 519 * This is the main wrapper for mapping host physical pages to CE PCI space. 520 * The mapping mode used is based on the device's dma_mask. 521 */ 522static u64 523tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count, 524 int barrier, int dma_flags) 525{ 526 unsigned long flags; 527 u64 ct_addr; 528 u64 mapaddr = 0; 529 struct tioce_kernel *ce_kern; 530 struct tioce_dmamap *map; 531 int port; 532 u64 dma_mask; 533 534 dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask; 535 536 /* cards must be able to address at least 31 bits */ 537 if (dma_mask < 0x7fffffffUL) 538 return 0; 539 540 if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS) 541 ct_addr = PHYS_TO_TIODMA(paddr); 542 else 543 ct_addr = paddr; 544 545 /* 546 * If the device can generate 64 bit addresses, create a D64 map. 547 */ 548 if (dma_mask == ~0UL) { 549 mapaddr = tioce_dma_d64(ct_addr, dma_flags); 550 if (mapaddr) 551 goto dma_map_done; 552 } 553 554 pcidev_to_tioce(pdev, NULL, &ce_kern, &port); 555 556 spin_lock_irqsave(&ce_kern->ce_lock, flags); 557 558 /* 559 * D64 didn't work ... See if we have an existing map that covers 560 * this address range. Must account for devices dma_mask here since 561 * an existing map might have been done in a mode using more pci 562 * address bits than this device can support. 563 */ 564 list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) { 565 u64 last; 566 567 last = map->ct_start + map->nbytes - 1; 568 if (ct_addr >= map->ct_start && 569 ct_addr + byte_count - 1 <= last && 570 map->pci_start <= dma_mask) { 571 map->refcnt++; 572 mapaddr = map->pci_start + (ct_addr - map->ct_start); 573 break; 574 } 575 } 576 577 /* 578 * If we don't have a map yet, and the card can generate 40 579 * bit addresses, try the M40/M40S modes. Note these modes do not 580 * support a barrier bit, so if we need a consistent map these 581 * won't work. 582 */ 583 if (!mapaddr && !barrier && dma_mask >= 0xffffffffffUL) { 584 /* 585 * We have two options for 40-bit mappings: 16GB "super" ATEs 586 * and 64MB "regular" ATEs. We'll try both if needed for a 587 * given mapping but which one we try first depends on the 588 * size. For requests >64MB, prefer to use a super page with 589 * regular as the fallback. Otherwise, try in the reverse order. 590 */ 591 592 if (byte_count > MB(64)) { 593 mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40S, 594 port, ct_addr, byte_count, 595 dma_flags); 596 if (!mapaddr) 597 mapaddr = 598 tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1, 599 ct_addr, byte_count, 600 dma_flags); 601 } else { 602 mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1, 603 ct_addr, byte_count, 604 dma_flags); 605 if (!mapaddr) 606 mapaddr = 607 tioce_alloc_map(ce_kern, TIOCE_ATE_M40S, 608 port, ct_addr, byte_count, 609 dma_flags); 610 } 611 } 612 613 /* 614 * 32-bit direct is the next mode to try 615 */ 616 if (!mapaddr && dma_mask >= 0xffffffffUL) 617 mapaddr = tioce_dma_d32(pdev, ct_addr, dma_flags); 618 619 /* 620 * Last resort, try 32-bit ATE-based map. 621 */ 622 if (!mapaddr) 623 mapaddr = 624 tioce_alloc_map(ce_kern, TIOCE_ATE_M32, -1, ct_addr, 625 byte_count, dma_flags); 626 627 spin_unlock_irqrestore(&ce_kern->ce_lock, flags); 628 629dma_map_done: 630 if (mapaddr && barrier) 631 mapaddr = tioce_dma_barrier(mapaddr, 1); 632 633 return mapaddr; 634} 635 636/** 637 * tioce_dma - standard pci dma map interface 638 * @pdev: pci device requesting the map 639 * @paddr: system physical address to map into pci space 640 * @byte_count: # bytes to map 641 * 642 * Simply call tioce_do_dma_map() to create a map with the barrier bit clear 643 * in the address. 644 */ 645static u64 646tioce_dma(struct pci_dev *pdev, unsigned long paddr, size_t byte_count, int dma_flags) 647{ 648 return tioce_do_dma_map(pdev, paddr, byte_count, 0, dma_flags); 649} 650 651/** 652 * tioce_dma_consistent - consistent pci dma map interface 653 * @pdev: pci device requesting the map 654 * @paddr: system physical address to map into pci space 655 * @byte_count: # bytes to map 656 * 657 * Simply call tioce_do_dma_map() to create a map with the barrier bit set 658 * in the address. 659 */ 660static u64 661tioce_dma_consistent(struct pci_dev *pdev, unsigned long paddr, size_t byte_count, int dma_flags) 662{ 663 return tioce_do_dma_map(pdev, paddr, byte_count, 1, dma_flags); 664} 665 666/** 667 * tioce_error_intr_handler - SGI TIO CE error interrupt handler 668 * @irq: unused 669 * @arg: pointer to tioce_common struct for the given CE 670 * 671 * Handle a CE error interrupt. Simply a wrapper around a SAL call which 672 * defers processing to the SGI prom. 673 */ 674static irqreturn_t 675tioce_error_intr_handler(int irq, void *arg) 676{ 677 struct tioce_common *soft = arg; 678 struct ia64_sal_retval ret_stuff; 679 ret_stuff.status = 0; 680 ret_stuff.v0 = 0; 681 682 SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_ERROR_INTERRUPT, 683 soft->ce_pcibus.bs_persist_segment, 684 soft->ce_pcibus.bs_persist_busnum, 0, 0, 0, 0, 0); 685 686 if (ret_stuff.v0) 687 panic("tioce_error_intr_handler: Fatal TIOCE error"); 688 689 return IRQ_HANDLED; 690} 691 692/** 693 * tioce_reserve_m32 - reserve M32 ATEs for the indicated address range 694 * @tioce_kernel: TIOCE context to reserve ATEs for 695 * @base: starting bus address to reserve 696 * @limit: last bus address to reserve 697 * 698 * If base/limit falls within the range of bus space mapped through the 699 * M32 space, reserve the resources corresponding to the range. 700 */ 701static void 702tioce_reserve_m32(struct tioce_kernel *ce_kern, u64 base, u64 limit) 703{ 704 int ate_index, last_ate, ps; 705 struct tioce __iomem *ce_mmr; 706 707 ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base; 708 ps = ce_kern->ce_ate3240_pagesize; 709 ate_index = ATE_PAGE(base, ps); 710 last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1; 711 712 if (ate_index < 64) 713 ate_index = 64; 714 715 if (last_ate >= TIOCE_NUM_M3240_ATES) 716 last_ate = TIOCE_NUM_M3240_ATES - 1; 717 718 while (ate_index <= last_ate) { 719 u64 ate; 720 721 ate = ATE_MAKE(0xdeadbeef, ps, 0); 722 ce_kern->ce_ate3240_shadow[ate_index] = ate; 723 tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_ate3240[ate_index], 724 ate); 725 ate_index++; 726 } 727} 728 729/** 730 * tioce_kern_init - init kernel structures related to a given TIOCE 731 * @tioce_common: ptr to a cached tioce_common struct that originated in prom 732 */ 733static struct tioce_kernel * 734tioce_kern_init(struct tioce_common *tioce_common) 735{ 736 int i; 737 int ps; 738 int dev; 739 u32 tmp; 740 unsigned int seg, bus; 741 struct tioce __iomem *tioce_mmr; 742 struct tioce_kernel *tioce_kern; 743 744 tioce_kern = kzalloc(sizeof(struct tioce_kernel), GFP_KERNEL); 745 if (!tioce_kern) { 746 return NULL; 747 } 748 749 tioce_kern->ce_common = tioce_common; 750 spin_lock_init(&tioce_kern->ce_lock); 751 INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list); 752 tioce_common->ce_kernel_private = (u64) tioce_kern; 753 754 /* 755 * Determine the secondary bus number of the port2 logical PPB. 756 * This is used to decide whether a given pci device resides on 757 * port1 or port2. Note: We don't have enough plumbing set up 758 * here to use pci_read_config_xxx() so use raw_pci_read(). 759 */ 760 761 seg = tioce_common->ce_pcibus.bs_persist_segment; 762 bus = tioce_common->ce_pcibus.bs_persist_busnum; 763 764 raw_pci_read(seg, bus, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1,&tmp); 765 tioce_kern->ce_port1_secondary = (u8) tmp; 766 767 /* 768 * Set PMU pagesize to the largest size available, and zero out 769 * the ATEs. 770 */ 771 772 tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base; 773 tioce_mmr_clri(tioce_kern, &tioce_mmr->ce_ure_page_map, 774 CE_URE_PAGESIZE_MASK); 775 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_ure_page_map, 776 CE_URE_256K_PAGESIZE); 777 ps = tioce_kern->ce_ate3240_pagesize = KB(256); 778 779 for (i = 0; i < TIOCE_NUM_M40_ATES; i++) { 780 tioce_kern->ce_ate40_shadow[i] = 0; 781 tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate40[i], 0); 782 } 783 784 for (i = 0; i < TIOCE_NUM_M3240_ATES; i++) { 785 tioce_kern->ce_ate3240_shadow[i] = 0; 786 tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate3240[i], 0); 787 } 788 789 /* 790 * Reserve ATEs corresponding to reserved address ranges. These 791 * include: 792 * 793 * Memory space covered by each PPB mem base/limit register 794 * Memory space covered by each PPB prefetch base/limit register 795 * 796 * These bus ranges are for pio (downstream) traffic only, and so 797 * cannot be used for DMA. 798 */ 799 800 for (dev = 1; dev <= 2; dev++) { 801 u64 base, limit; 802 803 /* mem base/limit */ 804 805 raw_pci_read(seg, bus, PCI_DEVFN(dev, 0), 806 PCI_MEMORY_BASE, 2, &tmp); 807 base = (u64)tmp << 16; 808 809 raw_pci_read(seg, bus, PCI_DEVFN(dev, 0), 810 PCI_MEMORY_LIMIT, 2, &tmp); 811 limit = (u64)tmp << 16; 812 limit |= 0xfffffUL; 813 814 if (base < limit) 815 tioce_reserve_m32(tioce_kern, base, limit); 816 817 /* 818 * prefetch mem base/limit. The tioce ppb's have 64-bit 819 * decoders, so read the upper portions w/o checking the 820 * attributes. 821 */ 822 823 raw_pci_read(seg, bus, PCI_DEVFN(dev, 0), 824 PCI_PREF_MEMORY_BASE, 2, &tmp); 825 base = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16; 826 827 raw_pci_read(seg, bus, PCI_DEVFN(dev, 0), 828 PCI_PREF_BASE_UPPER32, 4, &tmp); 829 base |= (u64)tmp << 32; 830 831 raw_pci_read(seg, bus, PCI_DEVFN(dev, 0), 832 PCI_PREF_MEMORY_LIMIT, 2, &tmp); 833 834 limit = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16; 835 limit |= 0xfffffUL; 836 837 raw_pci_read(seg, bus, PCI_DEVFN(dev, 0), 838 PCI_PREF_LIMIT_UPPER32, 4, &tmp); 839 limit |= (u64)tmp << 32; 840 841 if ((base < limit) && TIOCE_M32_ADDR(base)) 842 tioce_reserve_m32(tioce_kern, base, limit); 843 } 844 845 return tioce_kern; 846} 847 848static void 849tioce_force_interrupt(struct sn_irq_info *sn_irq_info) 850{ 851 struct pcidev_info *pcidev_info; 852 struct tioce_common *ce_common; 853 struct tioce_kernel *ce_kern; 854 struct tioce __iomem *ce_mmr; 855 u64 force_int_val; 856 857 if (!sn_irq_info->irq_bridge) 858 return; 859 860 if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_TIOCE) 861 return; 862 863 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; 864 if (!pcidev_info) 865 return; 866 867 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; 868 ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base; 869 ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private; 870 871 if (ce_common->ce_rev == TIOCE_REV_A) { 872 u64 int_bit_mask = (1ULL << sn_irq_info->irq_int_bit); 873 u64 status; 874 875 tioce_mmr_load(ce_kern, &ce_mmr->ce_adm_int_status, &status); 876 if (status & int_bit_mask) { 877 u64 force_irq = (1 << 8) | sn_irq_info->irq_irq; 878 u64 ctalk = sn_irq_info->irq_xtalkaddr; 879 u64 nasid, offset; 880 881 nasid = (ctalk & CTALK_NASID_MASK) >> CTALK_NASID_SHFT; 882 offset = (ctalk & CTALK_NODE_OFFSET); 883 HUB_S(TIO_IOSPACE_ADDR(nasid, offset), force_irq); 884 } 885 886 return; 887 } 888 889 /* 890 * irq_int_bit is originally set up by prom, and holds the interrupt 891 * bit shift (not mask) as defined by the bit definitions in the 892 * ce_adm_int mmr. These shifts are not the same for the 893 * ce_adm_force_int register, so do an explicit mapping here to make 894 * things clearer. 895 */ 896 897 switch (sn_irq_info->irq_int_bit) { 898 case CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT: 899 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT; 900 break; 901 case CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT: 902 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT; 903 break; 904 case CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT: 905 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT; 906 break; 907 case CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT: 908 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT; 909 break; 910 case CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT: 911 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT; 912 break; 913 case CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT: 914 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT; 915 break; 916 case CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT: 917 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT; 918 break; 919 case CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT: 920 force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT; 921 break; 922 default: 923 return; 924 } 925 tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_force_int, force_int_val); 926} 927 928/** 929 * tioce_target_interrupt - implement set_irq_affinity for tioce resident 930 * functions. Note: only applies to line interrupts, not MSI's. 931 * 932 * @sn_irq_info: SN IRQ context 933 * 934 * Given an sn_irq_info, set the associated CE device's interrupt destination 935 * register. Since the interrupt destination registers are on a per-ce-slot 936 * basis, this will retarget line interrupts for all functions downstream of 937 * the slot. 938 */ 939static void 940tioce_target_interrupt(struct sn_irq_info *sn_irq_info) 941{ 942 struct pcidev_info *pcidev_info; 943 struct tioce_common *ce_common; 944 struct tioce_kernel *ce_kern; 945 struct tioce __iomem *ce_mmr; 946 int bit; 947 u64 vector; 948 949 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; 950 if (!pcidev_info) 951 return; 952 953 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; 954 ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base; 955 ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private; 956 957 bit = sn_irq_info->irq_int_bit; 958 959 tioce_mmr_seti(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit)); 960 vector = (u64)sn_irq_info->irq_irq << INTR_VECTOR_SHFT; 961 vector |= sn_irq_info->irq_xtalkaddr; 962 tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_int_dest[bit], vector); 963 tioce_mmr_clri(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit)); 964 965 tioce_force_interrupt(sn_irq_info); 966} 967 968/** 969 * tioce_bus_fixup - perform final PCI fixup for a TIO CE bus 970 * @prom_bussoft: Common prom/kernel struct representing the bus 971 * 972 * Replicates the tioce_common pointed to by @prom_bussoft in kernel 973 * space. Allocates and initializes a kernel-only area for a given CE, 974 * and sets up an irq for handling CE error interrupts. 975 * 976 * On successful setup, returns the kernel version of tioce_common back to 977 * the caller. 978 */ 979static void * 980tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller) 981{ 982 struct tioce_common *tioce_common; 983 struct tioce_kernel *tioce_kern; 984 struct tioce __iomem *tioce_mmr; 985 986 /* 987 * Allocate kernel bus soft and copy from prom. 988 */ 989 990 tioce_common = kzalloc(sizeof(struct tioce_common), GFP_KERNEL); 991 if (!tioce_common) 992 return NULL; 993 994 memcpy(tioce_common, prom_bussoft, sizeof(struct tioce_common)); 995 tioce_common->ce_pcibus.bs_base = (unsigned long) 996 ioremap(REGION_OFFSET(tioce_common->ce_pcibus.bs_base), 997 sizeof(struct tioce_common)); 998 999 tioce_kern = tioce_kern_init(tioce_common); 1000 if (tioce_kern == NULL) { 1001 kfree(tioce_common); 1002 return NULL; 1003 } 1004 1005 /* 1006 * Clear out any transient errors before registering the error 1007 * interrupt handler. 1008 */ 1009 1010 tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base; 1011 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_int_status_alias, ~0ULL); 1012 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_error_summary_alias, 1013 ~0ULL); 1014 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_dre_comp_err_addr, 0ULL); 1015 1016 if (request_irq(SGI_PCIASIC_ERROR, 1017 tioce_error_intr_handler, 1018 IRQF_SHARED, "TIOCE error", (void *)tioce_common)) 1019 printk(KERN_WARNING 1020 "%s: Unable to get irq %d. " 1021 "Error interrupts won't be routed for " 1022 "TIOCE bus %04x:%02x\n", 1023 __func__, SGI_PCIASIC_ERROR, 1024 tioce_common->ce_pcibus.bs_persist_segment, 1025 tioce_common->ce_pcibus.bs_persist_busnum); 1026 1027 sn_set_err_irq_affinity(SGI_PCIASIC_ERROR); 1028 return tioce_common; 1029} 1030 1031static struct sn_pcibus_provider tioce_pci_interfaces = { 1032 .dma_map = tioce_dma, 1033 .dma_map_consistent = tioce_dma_consistent, 1034 .dma_unmap = tioce_dma_unmap, 1035 .bus_fixup = tioce_bus_fixup, 1036 .force_interrupt = tioce_force_interrupt, 1037 .target_interrupt = tioce_target_interrupt 1038}; 1039 1040/** 1041 * tioce_init_provider - init SN PCI provider ops for TIO CE 1042 */ 1043int 1044tioce_init_provider(void) 1045{ 1046 sn_pci_provider[PCIIO_ASIC_TYPE_TIOCE] = &tioce_pci_interfaces; 1047 return 0; 1048} 1049