1/* pci-vdk.c: MB93090-MB00 (VDK) PCI support 2 * 3 * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12#include <linux/types.h> 13#include <linux/kernel.h> 14#include <linux/sched.h> 15#include <linux/pci.h> 16#include <linux/init.h> 17#include <linux/ioport.h> 18#include <linux/delay.h> 19 20#include <asm/segment.h> 21#include <asm/io.h> 22#include <asm/mb-regs.h> 23#include <asm/mb86943a.h> 24#include "pci-frv.h" 25 26unsigned int __nongpreldata pci_probe = 1; 27 28int __nongpreldata pcibios_last_bus = -1; 29struct pci_bus *__nongpreldata pci_root_bus; 30struct pci_ops *__nongpreldata pci_root_ops; 31 32/* 33 * The accessible PCI window does not cover the entire CPU address space, but 34 * there are devices we want to access outside of that window, so we need to 35 * insert specific PCI bus resources instead of using the platform-level bus 36 * resources directly for the PCI root bus. 37 * 38 * These are configured and inserted by pcibios_init() and are attached to the 39 * root bus by pcibios_fixup_bus(). 40 */ 41static struct resource pci_ioport_resource = { 42 .name = "PCI IO", 43 .start = 0, 44 .end = IO_SPACE_LIMIT, 45 .flags = IORESOURCE_IO, 46}; 47 48static struct resource pci_iomem_resource = { 49 .name = "PCI mem", 50 .start = 0, 51 .end = -1, 52 .flags = IORESOURCE_MEM, 53}; 54 55/* 56 * Functions for accessing PCI configuration space 57 */ 58 59#define CONFIG_CMD(bus, dev, where) \ 60 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) 61 62#define __set_PciCfgAddr(A) writel((A), (volatile void __iomem *) __region_CS1 + 0x80) 63 64#define __get_PciCfgDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 3)) 65#define __get_PciCfgDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 2)) 66#define __get_PciCfgDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x88) 67 68#define __set_PciCfgDataB(A,V) \ 69 writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3))) 70 71#define __set_PciCfgDataW(A,V) \ 72 writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2))) 73 74#define __set_PciCfgDataL(A,V) \ 75 writel((V), (volatile void __iomem *) __region_CS1 + 0x88) 76 77#define __get_PciBridgeDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x800 + (A)) 78#define __get_PciBridgeDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x800 + (A)) 79#define __get_PciBridgeDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x800 + (A)) 80 81#define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A)) 82#define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A)) 83#define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A)) 84 85static inline int __query(const struct pci_dev *dev) 86{ 87// return dev->bus->number==0 && (dev->devfn==PCI_DEVFN(0,0)); 88// return dev->bus->number==1; 89// return dev->bus->number==0 && 90// (dev->devfn==PCI_DEVFN(2,0) || dev->devfn==PCI_DEVFN(3,0)); 91 return 0; 92} 93 94/*****************************************************************************/ 95/* 96 * 97 */ 98static int pci_frv_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, 99 u32 *val) 100{ 101 u32 _value; 102 103 if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { 104 _value = __get_PciBridgeDataL(where & ~3); 105 } 106 else { 107 __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where)); 108 _value = __get_PciCfgDataL(where & ~3); 109 } 110 111 switch (size) { 112 case 1: 113 _value = _value >> ((where & 3) * 8); 114 break; 115 116 case 2: 117 _value = _value >> ((where & 2) * 8); 118 break; 119 120 case 4: 121 break; 122 123 default: 124 BUG(); 125 } 126 127 *val = _value; 128 return PCIBIOS_SUCCESSFUL; 129} 130 131static int pci_frv_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, 132 u32 value) 133{ 134 switch (size) { 135 case 1: 136 if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { 137 __set_PciBridgeDataB(where, value); 138 } 139 else { 140 __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where)); 141 __set_PciCfgDataB(where, value); 142 } 143 break; 144 145 case 2: 146 if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { 147 __set_PciBridgeDataW(where, value); 148 } 149 else { 150 __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where)); 151 __set_PciCfgDataW(where, value); 152 } 153 break; 154 155 case 4: 156 if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { 157 __set_PciBridgeDataL(where, value); 158 } 159 else { 160 __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where)); 161 __set_PciCfgDataL(where, value); 162 } 163 break; 164 165 default: 166 BUG(); 167 } 168 169 return PCIBIOS_SUCCESSFUL; 170} 171 172static struct pci_ops pci_direct_frv = { 173 pci_frv_read_config, 174 pci_frv_write_config, 175}; 176 177/* 178 * Before we decide to use direct hardware access mechanisms, we try to do some 179 * trivial checks to ensure it at least _seems_ to be working -- we just test 180 * whether bus 00 contains a host bridge (this is similar to checking 181 * techniques used in XFree86, but ours should be more reliable since we 182 * attempt to make use of direct access hints provided by the PCI BIOS). 183 * 184 * This should be close to trivial, but it isn't, because there are buggy 185 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. 186 */ 187static int __init pci_sanity_check(struct pci_ops *o) 188{ 189 struct pci_bus bus; /* Fake bus and device */ 190 u32 id; 191 192 bus.number = 0; 193 194 if (o->read(&bus, 0, PCI_VENDOR_ID, 4, &id) == PCIBIOS_SUCCESSFUL) { 195 printk("PCI: VDK Bridge device:vendor: %08x\n", id); 196 if (id == 0x200e10cf) 197 return 1; 198 } 199 200 printk("PCI: VDK Bridge: Sanity check failed\n"); 201 return 0; 202} 203 204static struct pci_ops * __init pci_check_direct(void) 205{ 206 unsigned long flags; 207 208 local_irq_save(flags); 209 210 /* check if access works */ 211 if (pci_sanity_check(&pci_direct_frv)) { 212 local_irq_restore(flags); 213 printk("PCI: Using configuration frv\n"); 214// request_mem_region(0xBE040000, 256, "FRV bridge"); 215// request_mem_region(0xBFFFFFF4, 12, "PCI frv"); 216 return &pci_direct_frv; 217 } 218 219 local_irq_restore(flags); 220 return NULL; 221} 222 223/* 224 * Discover remaining PCI buses in case there are peer host bridges. 225 * We use the number of last PCI bus provided by the PCI BIOS. 226 */ 227static void __init pcibios_fixup_peer_bridges(void) 228{ 229 struct pci_bus bus; 230 struct pci_dev dev; 231 int n; 232 u16 l; 233 234 if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff) 235 return; 236 printk("PCI: Peer bridge fixup\n"); 237 for (n=0; n <= pcibios_last_bus; n++) { 238 if (pci_find_bus(0, n)) 239 continue; 240 bus.number = n; 241 bus.ops = pci_root_ops; 242 dev.bus = &bus; 243 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8) 244 if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) && 245 l != 0x0000 && l != 0xffff) { 246 printk("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l); 247 printk("PCI: Discovered peer bus %02x\n", n); 248 pci_scan_bus(n, pci_root_ops, NULL); 249 break; 250 } 251 } 252} 253 254/* 255 * Exceptions for specific devices. Usually work-arounds for fatal design flaws. 256 */ 257 258static void __init pci_fixup_umc_ide(struct pci_dev *d) 259{ 260 /* 261 * UM8886BF IDE controller sets region type bits incorrectly, 262 * therefore they look like memory despite of them being I/O. 263 */ 264 int i; 265 266 printk("PCI: Fixing base address flags for device %s\n", pci_name(d)); 267 for(i=0; i<4; i++) 268 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; 269} 270 271static void __init pci_fixup_ide_bases(struct pci_dev *d) 272{ 273 int i; 274 275 /* 276 * PCI IDE controllers use non-standard I/O port decoding, respect it. 277 */ 278 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) 279 return; 280 printk("PCI: IDE base address fixup for %s\n", pci_name(d)); 281 for(i=0; i<4; i++) { 282 struct resource *r = &d->resource[i]; 283 if ((r->start & ~0x80) == 0x374) { 284 r->start |= 2; 285 r->end = r->start; 286 } 287 } 288} 289 290static void __init pci_fixup_ide_trash(struct pci_dev *d) 291{ 292 int i; 293 294 /* 295 * There exist PCI IDE controllers which have utter garbage 296 * in first four base registers. Ignore that. 297 */ 298 printk("PCI: IDE base address trash cleared for %s\n", pci_name(d)); 299 for(i=0; i<4; i++) 300 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0; 301} 302 303static void __devinit pci_fixup_latency(struct pci_dev *d) 304{ 305 /* 306 * SiS 5597 and 5598 chipsets require latency timer set to 307 * at most 32 to avoid lockups. 308 */ 309 DBG("PCI: Setting max latency to 32\n"); 310 pcibios_max_latency = 32; 311} 312 313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide); 314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash); 315DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency); 316DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency); 317DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); 318 319/* 320 * Called after each bus is probed, but before its children 321 * are examined. 322 */ 323 324void __init pcibios_fixup_bus(struct pci_bus *bus) 325{ 326 327 if (bus->number == 0) { 328 bus->resource[0] = &pci_ioport_resource; 329 bus->resource[1] = &pci_iomem_resource; 330 } 331 332 pci_read_bridge_bases(bus); 333 334 if (bus->number == 0) { 335 struct list_head *ln; 336 struct pci_dev *dev; 337 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) { 338 dev = pci_dev_b(ln); 339 if (dev->devfn == 0) { 340 dev->resource[0].start = 0; 341 dev->resource[0].end = 0; 342 } 343 } 344 } 345} 346 347/* 348 * Initialization. Try all known PCI access methods. Note that we support 349 * using both PCI BIOS and direct access: in such cases, we use I/O ports 350 * to access config space, but we still keep BIOS order of cards to be 351 * compatible with 2.0.X. This should go away some day. 352 */ 353 354int __init pcibios_init(void) 355{ 356 struct pci_ops *dir = NULL; 357 358 if (!mb93090_mb00_detected) 359 return -ENXIO; 360 361 __reg_MB86943_sl_ctl |= MB86943_SL_CTL_DRCT_MASTER_SWAP | MB86943_SL_CTL_DRCT_SLAVE_SWAP; 362 363 __reg_MB86943_ecs_base(1) = ((__region_CS2 + 0x01000000) >> 9) | 0x08000000; 364 __reg_MB86943_ecs_base(2) = ((__region_CS2 + 0x00000000) >> 9) | 0x08000000; 365 366 *(volatile uint32_t *) (__region_CS1 + 0x848) = 0xe0000000; 367 *(volatile uint32_t *) (__region_CS1 + 0x8b8) = 0x00000000; 368 369 __reg_MB86943_sl_pci_io_base = (__region_CS2 + 0x04000000) >> 9; 370 __reg_MB86943_sl_pci_mem_base = (__region_CS2 + 0x08000000) >> 9; 371 __reg_MB86943_pci_sl_io_base = __region_CS2 + 0x04000000; 372 __reg_MB86943_pci_sl_mem_base = __region_CS2 + 0x08000000; 373 mb(); 374 375 /* enable PCI arbitration */ 376 __reg_MB86943_pci_arbiter = MB86943_PCIARB_EN; 377 378 pci_ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00; 379 pci_ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff; 380 pci_ioport_resource.end += pci_ioport_resource.start; 381 382 printk("PCI IO window: %08llx-%08llx\n", 383 (unsigned long long) pci_ioport_resource.start, 384 (unsigned long long) pci_ioport_resource.end); 385 386 pci_iomem_resource.start = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00; 387 pci_iomem_resource.end = (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff; 388 pci_iomem_resource.end += pci_iomem_resource.start; 389 390 /* Reserve somewhere to write to flush posted writes. This is used by 391 * __flush_PCI_writes() from asm/io.h to force the write FIFO in the 392 * CPU-PCI bridge to flush as this doesn't happen automatically when a 393 * read is performed on the MB93090 development kit motherboard. 394 */ 395 pci_iomem_resource.start += 0x400; 396 397 printk("PCI MEM window: %08llx-%08llx\n", 398 (unsigned long long) pci_iomem_resource.start, 399 (unsigned long long) pci_iomem_resource.end); 400 printk("PCI DMA memory: %08lx-%08lx\n", 401 dma_coherent_mem_start, dma_coherent_mem_end); 402 403 if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0) 404 panic("Unable to insert PCI IOMEM resource\n"); 405 if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0) 406 panic("Unable to insert PCI IOPORT resource\n"); 407 408 if (!pci_probe) 409 return -ENXIO; 410 411 dir = pci_check_direct(); 412 if (dir) 413 pci_root_ops = dir; 414 else { 415 printk("PCI: No PCI bus detected\n"); 416 return -ENXIO; 417 } 418 419 printk("PCI: Probing PCI hardware\n"); 420 pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL); 421 422 pcibios_irq_init(); 423 pcibios_fixup_peer_bridges(); 424 pcibios_fixup_irqs(); 425 pcibios_resource_survey(); 426 427 return 0; 428} 429 430arch_initcall(pcibios_init); 431 432char * __init pcibios_setup(char *str) 433{ 434 if (!strcmp(str, "off")) { 435 pci_probe = 0; 436 return NULL; 437 } else if (!strncmp(str, "lastbus=", 8)) { 438 pcibios_last_bus = simple_strtol(str+8, NULL, 0); 439 return NULL; 440 } 441 return str; 442} 443 444int pcibios_enable_device(struct pci_dev *dev, int mask) 445{ 446 int err; 447 448 if ((err = pci_enable_resources(dev, mask)) < 0) 449 return err; 450 if (!dev->msi_enabled) 451 pcibios_enable_irq(dev); 452 return 0; 453} 454