1#ifndef __iop_sw_spu_defs_h 2#define __iop_sw_spu_defs_h 3 4/* 5 * This file is autogenerated from 6 * file: iop_sw_spu.r 7 * 8 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r 9 * Any changes here will be lost. 10 * 11 * -*- buffer-read-only: t -*- 12 */ 13/* Main access macros */ 14#ifndef REG_RD 15#define REG_RD( scope, inst, reg ) \ 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 18#endif 19 20#ifndef REG_WR 21#define REG_WR( scope, inst, reg, val ) \ 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 24#endif 25 26#ifndef REG_RD_VECT 27#define REG_RD_VECT( scope, inst, reg, index ) \ 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) 31#endif 32 33#ifndef REG_WR_VECT 34#define REG_WR_VECT( scope, inst, reg, index, val ) \ 35 REG_WRITE( reg_##scope##_##reg, \ 36 (inst) + REG_WR_ADDR_##scope##_##reg + \ 37 (index) * STRIDE_##scope##_##reg, (val) ) 38#endif 39 40#ifndef REG_RD_INT 41#define REG_RD_INT( scope, inst, reg ) \ 42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 43#endif 44 45#ifndef REG_WR_INT 46#define REG_WR_INT( scope, inst, reg, val ) \ 47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 48#endif 49 50#ifndef REG_RD_INT_VECT 51#define REG_RD_INT_VECT( scope, inst, reg, index ) \ 52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 53 (index) * STRIDE_##scope##_##reg ) 54#endif 55 56#ifndef REG_WR_INT_VECT 57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 59 (index) * STRIDE_##scope##_##reg, (val) ) 60#endif 61 62#ifndef REG_TYPE_CONV 63#define REG_TYPE_CONV( type, orgtype, val ) \ 64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 65#endif 66 67#ifndef reg_page_size 68#define reg_page_size 8192 69#endif 70 71#ifndef REG_ADDR 72#define REG_ADDR( scope, inst, reg ) \ 73 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 74#endif 75 76#ifndef REG_ADDR_VECT 77#define REG_ADDR_VECT( scope, inst, reg, index ) \ 78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 79 (index) * STRIDE_##scope##_##reg ) 80#endif 81 82/* C-code for register scope iop_sw_spu */ 83 84/* Register r_mpu_trace, scope iop_sw_spu, type r */ 85typedef unsigned int reg_iop_sw_spu_r_mpu_trace; 86#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0 87 88/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ 89typedef struct { 90 unsigned int keep_owner : 1; 91 unsigned int cmd : 2; 92 unsigned int size : 3; 93 unsigned int wr_spu_mem : 1; 94 unsigned int dummy1 : 25; 95} reg_iop_sw_spu_rw_mc_ctrl; 96#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4 97#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4 98 99/* Register rw_mc_data, scope iop_sw_spu, type rw */ 100typedef struct { 101 unsigned int val : 32; 102} reg_iop_sw_spu_rw_mc_data; 103#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8 104#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8 105 106/* Register rw_mc_addr, scope iop_sw_spu, type rw */ 107typedef unsigned int reg_iop_sw_spu_rw_mc_addr; 108#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12 109#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12 110 111/* Register rs_mc_data, scope iop_sw_spu, type rs */ 112typedef unsigned int reg_iop_sw_spu_rs_mc_data; 113#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16 114 115/* Register r_mc_data, scope iop_sw_spu, type r */ 116typedef unsigned int reg_iop_sw_spu_r_mc_data; 117#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20 118 119/* Register r_mc_stat, scope iop_sw_spu, type r */ 120typedef struct { 121 unsigned int busy_cpu : 1; 122 unsigned int busy_mpu : 1; 123 unsigned int busy_spu : 1; 124 unsigned int owned_by_cpu : 1; 125 unsigned int owned_by_mpu : 1; 126 unsigned int owned_by_spu : 1; 127 unsigned int dummy1 : 26; 128} reg_iop_sw_spu_r_mc_stat; 129#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24 130 131/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ 132typedef struct { 133 unsigned int byte0 : 8; 134 unsigned int byte1 : 8; 135 unsigned int byte2 : 8; 136 unsigned int byte3 : 8; 137} reg_iop_sw_spu_rw_bus_clr_mask; 138#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28 139#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28 140 141/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ 142typedef struct { 143 unsigned int byte0 : 8; 144 unsigned int byte1 : 8; 145 unsigned int byte2 : 8; 146 unsigned int byte3 : 8; 147} reg_iop_sw_spu_rw_bus_set_mask; 148#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32 149#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32 150 151/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ 152typedef struct { 153 unsigned int byte0 : 1; 154 unsigned int byte1 : 1; 155 unsigned int byte2 : 1; 156 unsigned int byte3 : 1; 157 unsigned int dummy1 : 28; 158} reg_iop_sw_spu_rw_bus_oe_clr_mask; 159#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 160#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 161 162/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ 163typedef struct { 164 unsigned int byte0 : 1; 165 unsigned int byte1 : 1; 166 unsigned int byte2 : 1; 167 unsigned int byte3 : 1; 168 unsigned int dummy1 : 28; 169} reg_iop_sw_spu_rw_bus_oe_set_mask; 170#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 171#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 172 173/* Register r_bus_in, scope iop_sw_spu, type r */ 174typedef unsigned int reg_iop_sw_spu_r_bus_in; 175#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44 176 177/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ 178typedef struct { 179 unsigned int val : 32; 180} reg_iop_sw_spu_rw_gio_clr_mask; 181#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48 182#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48 183 184/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ 185typedef struct { 186 unsigned int val : 32; 187} reg_iop_sw_spu_rw_gio_set_mask; 188#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52 189#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52 190 191/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ 192typedef struct { 193 unsigned int val : 32; 194} reg_iop_sw_spu_rw_gio_oe_clr_mask; 195#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 196#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 197 198/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ 199typedef struct { 200 unsigned int val : 32; 201} reg_iop_sw_spu_rw_gio_oe_set_mask; 202#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 203#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 204 205/* Register r_gio_in, scope iop_sw_spu, type r */ 206typedef unsigned int reg_iop_sw_spu_r_gio_in; 207#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64 208 209/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ 210typedef struct { 211 unsigned int byte0 : 8; 212 unsigned int byte1 : 8; 213 unsigned int dummy1 : 16; 214} reg_iop_sw_spu_rw_bus_clr_mask_lo; 215#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 216#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 217 218/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ 219typedef struct { 220 unsigned int byte2 : 8; 221 unsigned int byte3 : 8; 222 unsigned int dummy1 : 16; 223} reg_iop_sw_spu_rw_bus_clr_mask_hi; 224#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 225#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 226 227/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ 228typedef struct { 229 unsigned int byte0 : 8; 230 unsigned int byte1 : 8; 231 unsigned int dummy1 : 16; 232} reg_iop_sw_spu_rw_bus_set_mask_lo; 233#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 234#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 235 236/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ 237typedef struct { 238 unsigned int byte2 : 8; 239 unsigned int byte3 : 8; 240 unsigned int dummy1 : 16; 241} reg_iop_sw_spu_rw_bus_set_mask_hi; 242#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 243#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 244 245/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ 246typedef struct { 247 unsigned int val : 16; 248 unsigned int dummy1 : 16; 249} reg_iop_sw_spu_rw_gio_clr_mask_lo; 250#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 251#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 252 253/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ 254typedef struct { 255 unsigned int val : 16; 256 unsigned int dummy1 : 16; 257} reg_iop_sw_spu_rw_gio_clr_mask_hi; 258#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 259#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 260 261/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ 262typedef struct { 263 unsigned int val : 16; 264 unsigned int dummy1 : 16; 265} reg_iop_sw_spu_rw_gio_set_mask_lo; 266#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 267#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 268 269/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ 270typedef struct { 271 unsigned int val : 16; 272 unsigned int dummy1 : 16; 273} reg_iop_sw_spu_rw_gio_set_mask_hi; 274#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 275#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 276 277/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ 278typedef struct { 279 unsigned int val : 16; 280 unsigned int dummy1 : 16; 281} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; 282#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 283#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 284 285/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ 286typedef struct { 287 unsigned int val : 16; 288 unsigned int dummy1 : 16; 289} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; 290#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 291#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 292 293/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ 294typedef struct { 295 unsigned int val : 16; 296 unsigned int dummy1 : 16; 297} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; 298#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 299#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 300 301/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ 302typedef struct { 303 unsigned int val : 16; 304 unsigned int dummy1 : 16; 305} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; 306#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 307#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 308 309/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ 310typedef struct { 311 unsigned int intr0 : 1; 312 unsigned int intr1 : 1; 313 unsigned int intr2 : 1; 314 unsigned int intr3 : 1; 315 unsigned int intr4 : 1; 316 unsigned int intr5 : 1; 317 unsigned int intr6 : 1; 318 unsigned int intr7 : 1; 319 unsigned int intr8 : 1; 320 unsigned int intr9 : 1; 321 unsigned int intr10 : 1; 322 unsigned int intr11 : 1; 323 unsigned int intr12 : 1; 324 unsigned int intr13 : 1; 325 unsigned int intr14 : 1; 326 unsigned int intr15 : 1; 327 unsigned int dummy1 : 16; 328} reg_iop_sw_spu_rw_cpu_intr; 329#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116 330#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116 331 332/* Register r_cpu_intr, scope iop_sw_spu, type r */ 333typedef struct { 334 unsigned int intr0 : 1; 335 unsigned int intr1 : 1; 336 unsigned int intr2 : 1; 337 unsigned int intr3 : 1; 338 unsigned int intr4 : 1; 339 unsigned int intr5 : 1; 340 unsigned int intr6 : 1; 341 unsigned int intr7 : 1; 342 unsigned int intr8 : 1; 343 unsigned int intr9 : 1; 344 unsigned int intr10 : 1; 345 unsigned int intr11 : 1; 346 unsigned int intr12 : 1; 347 unsigned int intr13 : 1; 348 unsigned int intr14 : 1; 349 unsigned int intr15 : 1; 350 unsigned int dummy1 : 16; 351} reg_iop_sw_spu_r_cpu_intr; 352#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120 353 354/* Register r_hw_intr, scope iop_sw_spu, type r */ 355typedef struct { 356 unsigned int trigger_grp0 : 1; 357 unsigned int trigger_grp1 : 1; 358 unsigned int trigger_grp2 : 1; 359 unsigned int trigger_grp3 : 1; 360 unsigned int trigger_grp4 : 1; 361 unsigned int trigger_grp5 : 1; 362 unsigned int trigger_grp6 : 1; 363 unsigned int trigger_grp7 : 1; 364 unsigned int timer_grp0 : 1; 365 unsigned int timer_grp1 : 1; 366 unsigned int fifo_out : 1; 367 unsigned int fifo_out_extra : 1; 368 unsigned int fifo_in : 1; 369 unsigned int fifo_in_extra : 1; 370 unsigned int dmc_out : 1; 371 unsigned int dmc_in : 1; 372 unsigned int dummy1 : 16; 373} reg_iop_sw_spu_r_hw_intr; 374#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124 375 376/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ 377typedef struct { 378 unsigned int intr0 : 1; 379 unsigned int intr1 : 1; 380 unsigned int intr2 : 1; 381 unsigned int intr3 : 1; 382 unsigned int intr4 : 1; 383 unsigned int intr5 : 1; 384 unsigned int intr6 : 1; 385 unsigned int intr7 : 1; 386 unsigned int intr8 : 1; 387 unsigned int intr9 : 1; 388 unsigned int intr10 : 1; 389 unsigned int intr11 : 1; 390 unsigned int intr12 : 1; 391 unsigned int intr13 : 1; 392 unsigned int intr14 : 1; 393 unsigned int intr15 : 1; 394 unsigned int dummy1 : 16; 395} reg_iop_sw_spu_rw_mpu_intr; 396#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128 397#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128 398 399/* Register r_mpu_intr, scope iop_sw_spu, type r */ 400typedef struct { 401 unsigned int intr0 : 1; 402 unsigned int intr1 : 1; 403 unsigned int intr2 : 1; 404 unsigned int intr3 : 1; 405 unsigned int intr4 : 1; 406 unsigned int intr5 : 1; 407 unsigned int intr6 : 1; 408 unsigned int intr7 : 1; 409 unsigned int intr8 : 1; 410 unsigned int intr9 : 1; 411 unsigned int intr10 : 1; 412 unsigned int intr11 : 1; 413 unsigned int intr12 : 1; 414 unsigned int intr13 : 1; 415 unsigned int intr14 : 1; 416 unsigned int intr15 : 1; 417 unsigned int dummy1 : 16; 418} reg_iop_sw_spu_r_mpu_intr; 419#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132 420 421 422/* Constants */ 423enum { 424 regk_iop_sw_spu_copy = 0x00000000, 425 regk_iop_sw_spu_no = 0x00000000, 426 regk_iop_sw_spu_nop = 0x00000000, 427 regk_iop_sw_spu_rd = 0x00000002, 428 regk_iop_sw_spu_reg_copy = 0x00000001, 429 regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, 430 regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, 431 regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000, 432 regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, 433 regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, 434 regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, 435 regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, 436 regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, 437 regk_iop_sw_spu_set = 0x00000001, 438 regk_iop_sw_spu_wr = 0x00000003, 439 regk_iop_sw_spu_yes = 0x00000001 440}; 441#endif /* __iop_sw_spu_defs_h */ 442