1/* 2 * DO NOT EDIT THIS FILE 3 * This file is under version control at 4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ 5 * and can be replaced with that version at any time 6 * DO NOT EDIT THIS FILE 7 * 8 * Copyright 2004-2010 Analog Devices Inc. 9 * Licensed under the ADI BSD license. 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 11 */ 12 13/* This file should be up to date with: 14 * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List 15 */ 16 17#ifndef _MACH_ANOMALY_H_ 18#define _MACH_ANOMALY_H_ 19 20/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ 21#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 22# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 23#endif 24 25/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 26#define ANOMALY_05000074 (1) 27/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ 28#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) 29/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ 30#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) 31/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ 32#define ANOMALY_05000120 (1) 33/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 34#define ANOMALY_05000122 (1) 35/* Erroneous Exception when Enabling Cache */ 36#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) 37/* SIGNBITS Instruction Not Functional under Certain Conditions */ 38#define ANOMALY_05000127 (1) 39/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ 40#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) 41/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ 42#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) 43/* Stall in multi-unit DMA operations */ 44#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) 45/* Allowing the SPORT RX FIFO to fill will cause an overflow */ 46#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) 47/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ 48#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) 49/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ 50#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) 51/* DMA and TESTSET conflict when both are accessing external memory */ 52#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) 53/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ 54#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) 55/* MDMA may lose the first few words of a descriptor chain */ 56#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) 57/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ 58#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) 59/* IMDMA S1/D1 Channel May Stall */ 60#define ANOMALY_05000149 (1) 61/* DMA engine may lose data due to incorrect handshaking */ 62#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) 63/* DMA stalls when all three controllers read data from the same source */ 64#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) 65/* Execution stall when executing in L2 and doing external accesses */ 66#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) 67/* Frame Delay in SPORT Multichannel Mode */ 68#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) 69/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ 70#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) 71/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ 72#define ANOMALY_05000156 (__SILICON_REVISION__ < 4) 73/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ 74#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) 75/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ 76#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) 77/* A read from external memory may return a wrong value with data cache enabled */ 78#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) 79/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ 80#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) 81/* DMEM_CONTROL<12> is not set on Reset */ 82#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) 83/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ 84#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) 85/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ 86#define ANOMALY_05000166 (1) 87/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ 88#define ANOMALY_05000167 (1) 89/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ 90#define ANOMALY_05000168 (__SILICON_REVISION__ < 5) 91/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ 92#define ANOMALY_05000169 (__SILICON_REVISION__ < 5) 93/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ 94#define ANOMALY_05000171 (__SILICON_REVISION__ < 5) 95/* DSPID register values incorrect */ 96#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) 97/* DMA vs Core accesses to external memory */ 98#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) 99/* Cache Fill Buffer Data lost */ 100#define ANOMALY_05000174 (__SILICON_REVISION__ < 5) 101/* Overlapping Sequencer and Memory Stalls */ 102#define ANOMALY_05000175 (__SILICON_REVISION__ < 5) 103/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ 104#define ANOMALY_05000176 (__SILICON_REVISION__ < 5) 105/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ 106#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) 107/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ 108#define ANOMALY_05000180 (1) 109/* Disabling the PPI Resets the PPI Configuration Registers */ 110#define ANOMALY_05000181 (__SILICON_REVISION__ < 5) 111/* Internal Memory DMA Does Not Operate at Full Speed */ 112#define ANOMALY_05000182 (1) 113/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ 114#define ANOMALY_05000184 (__SILICON_REVISION__ < 5) 115/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ 116#define ANOMALY_05000185 (__SILICON_REVISION__ < 5) 117/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */ 118#define ANOMALY_05000186 (__SILICON_REVISION__ < 5) 119/* IMDMA Corrupted Data after a Halt */ 120#define ANOMALY_05000187 (1) 121/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ 122#define ANOMALY_05000188 (__SILICON_REVISION__ < 5) 123/* False Protection Exceptions when Speculative Fetch Is Cancelled */ 124#define ANOMALY_05000189 (__SILICON_REVISION__ < 5) 125/* PPI Not Functional at Core Voltage < 1Volt */ 126#define ANOMALY_05000190 (1) 127/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ 128#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) 129/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ 130#define ANOMALY_05000193 (__SILICON_REVISION__ < 5) 131/* Restarting SPORT in Specific Modes May Cause Data Corruption */ 132#define ANOMALY_05000194 (__SILICON_REVISION__ < 5) 133/* Failing MMR Accesses when Preceding Memory Read Stalls */ 134#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) 135/* Current DMA Address Shows Wrong Value During Carry Fix */ 136#define ANOMALY_05000199 (__SILICON_REVISION__ < 5) 137/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ 138#define ANOMALY_05000200 (__SILICON_REVISION__ < 5) 139/* Possible Infinite Stall with Specific Dual-DAG Situation */ 140#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) 141/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ 142#define ANOMALY_05000204 (__SILICON_REVISION__ < 5) 143/* Specific Sequence that Can Cause DMA Error or DMA Stopping */ 144#define ANOMALY_05000205 (__SILICON_REVISION__ < 5) 145/* Recovery from "Brown-Out" Condition */ 146#define ANOMALY_05000207 (__SILICON_REVISION__ < 5) 147/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ 148#define ANOMALY_05000208 (1) 149/* Speed Path in Computational Unit Affects Certain Instructions */ 150#define ANOMALY_05000209 (__SILICON_REVISION__ < 5) 151/* UART TX Interrupt Masked Erroneously */ 152#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) 153/* NMI Event at Boot Time Results in Unpredictable State */ 154#define ANOMALY_05000219 (__SILICON_REVISION__ < 5) 155/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ 156#define ANOMALY_05000220 (__SILICON_REVISION__ < 4) 157/* Incorrect Pulse-Width of UART Start Bit */ 158#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) 159/* Scratchpad Memory Bank Reads May Return Incorrect Data */ 160#define ANOMALY_05000227 (__SILICON_REVISION__ < 5) 161/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ 162#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) 163/* UART STB Bit Incorrectly Affects Receiver Setting */ 164#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) 165/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */ 166#define ANOMALY_05000232 (__SILICON_REVISION__ < 5) 167/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ 168#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) 169/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ 170#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) 171/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 172#define ANOMALY_05000245 (__SILICON_REVISION__ < 5) 173/* TESTSET Operation Forces Stall on the Other Core */ 174#define ANOMALY_05000248 (__SILICON_REVISION__ < 5) 175/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ 176#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) 177/* Exception Not Generated for MMR Accesses in Reserved Region */ 178#define ANOMALY_05000251 (__SILICON_REVISION__ < 5) 179/* Maximum External Clock Speed for Timers */ 180#define ANOMALY_05000253 (__SILICON_REVISION__ < 5) 181/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ 182#define ANOMALY_05000254 (__SILICON_REVISION__ > 3) 183/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ 184#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) 185/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ 186#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) 187/* ICPLB_STATUS MMR Register May Be Corrupted */ 188#define ANOMALY_05000260 (__SILICON_REVISION__ < 5) 189/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ 190#define ANOMALY_05000261 (__SILICON_REVISION__ < 5) 191/* Stores To Data Cache May Be Lost */ 192#define ANOMALY_05000262 (__SILICON_REVISION__ < 5) 193/* Hardware Loop Corrupted When Taking an ICPLB Exception */ 194#define ANOMALY_05000263 (__SILICON_REVISION__ < 5) 195/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ 196#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) 197/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 198#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) 199/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */ 200#define ANOMALY_05000266 (__SILICON_REVISION__ > 3) 201/* IMDMA May Corrupt Data under Certain Conditions */ 202#define ANOMALY_05000267 (1) 203/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ 204#define ANOMALY_05000269 (1) 205/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ 206#define ANOMALY_05000270 (1) 207/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 208#define ANOMALY_05000272 (1) 209/* Data Cache Write Back to External Synchronous Memory May Be Lost */ 210#define ANOMALY_05000274 (1) 211/* PPI Timing and Sampling Information Updates */ 212#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) 213/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ 214#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) 215/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ 216#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) 217/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 218#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) 219/* False Hardware Error Exception when ISR Context Is Not Restored */ 220/* Temporarily walk around for bug 5423 till this issue is confirmed by 221 * official anomaly document. It looks 05000281 still exists on bf561 222 * v0.5. 223 */ 224#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5) 225/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ 226#define ANOMALY_05000283 (1) 227/* Reads Will Receive Incorrect Data under Certain Conditions */ 228#define ANOMALY_05000287 (__SILICON_REVISION__ < 5) 229/* SPORTs May Receive Bad Data If FIFOs Fill Up */ 230#define ANOMALY_05000288 (__SILICON_REVISION__ < 5) 231/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ 232#define ANOMALY_05000301 (1) 233/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ 234#define ANOMALY_05000302 (1) 235/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ 236#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 237/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 238#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) 239/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 240#define ANOMALY_05000310 (1) 241/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 242#define ANOMALY_05000312 (1) 243/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ 244#define ANOMALY_05000313 (1) 245/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ 246#define ANOMALY_05000315 (1) 247/* PF2 Output Remains Asserted after SPI Master Boot */ 248#define ANOMALY_05000320 (__SILICON_REVISION__ > 3) 249/* Erroneous GPIO Flag Pin Operations under Specific Sequences */ 250#define ANOMALY_05000323 (1) 251/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */ 252#define ANOMALY_05000326 (__SILICON_REVISION__ > 3) 253/* 24-Bit SPI Boot Mode Is Not Functional */ 254#define ANOMALY_05000331 (__SILICON_REVISION__ < 5) 255/* Slave SPI Boot Mode Is Not Functional */ 256#define ANOMALY_05000332 (__SILICON_REVISION__ < 5) 257/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */ 258#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) 259/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */ 260#define ANOMALY_05000339 (__SILICON_REVISION__ < 5) 261/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ 262#define ANOMALY_05000343 (__SILICON_REVISION__ < 5) 263/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 264#define ANOMALY_05000357 (1) 265/* Conflicting Column Address Widths Causes SDRAM Errors */ 266#define ANOMALY_05000362 (1) 267/* UART Break Signal Issues */ 268#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) 269/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 270#define ANOMALY_05000366 (1) 271/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 272#define ANOMALY_05000371 (1) 273/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ 274#define ANOMALY_05000402 (__SILICON_REVISION__ == 4) 275/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 276#define ANOMALY_05000403 (1) 277/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ 278#define ANOMALY_05000412 (1) 279/* Speculative Fetches Can Cause Undesired External FIFO Operations */ 280#define ANOMALY_05000416 (1) 281/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ 282#define ANOMALY_05000425 (1) 283/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ 284#define ANOMALY_05000426 (1) 285/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */ 286#define ANOMALY_05000428 (__SILICON_REVISION__ > 3) 287/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 288#define ANOMALY_05000443 (1) 289/* False Hardware Error when RETI Points to Invalid Memory */ 290#define ANOMALY_05000461 (1) 291/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 292#define ANOMALY_05000473 (1) 293/* Possible Lockup Condition whem Modifying PLL from External Memory */ 294#define ANOMALY_05000475 (__SILICON_REVISION__ < 4) 295/* TESTSET Instruction Cannot Be Interrupted */ 296#define ANOMALY_05000477 (1) 297/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 298#define ANOMALY_05000481 (1) 299/* IFLUSH sucks at life */ 300#define ANOMALY_05000491 (1) 301 302/* Anomalies that don't exist on this proc */ 303#define ANOMALY_05000119 (0) 304#define ANOMALY_05000158 (0) 305#define ANOMALY_05000183 (0) 306#define ANOMALY_05000233 (0) 307#define ANOMALY_05000234 (0) 308#define ANOMALY_05000273 (0) 309#define ANOMALY_05000311 (0) 310#define ANOMALY_05000353 (1) 311#define ANOMALY_05000364 (0) 312#define ANOMALY_05000380 (0) 313#define ANOMALY_05000386 (1) 314#define ANOMALY_05000389 (0) 315#define ANOMALY_05000400 (0) 316#define ANOMALY_05000430 (0) 317#define ANOMALY_05000432 (0) 318#define ANOMALY_05000435 (0) 319#define ANOMALY_05000447 (0) 320#define ANOMALY_05000448 (0) 321#define ANOMALY_05000456 (0) 322#define ANOMALY_05000450 (0) 323#define ANOMALY_05000465 (0) 324#define ANOMALY_05000467 (0) 325#define ANOMALY_05000474 (0) 326#define ANOMALY_05000485 (0) 327 328#endif 329