1/* 2 * DO NOT EDIT THIS FILE 3 * This file is under version control at 4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ 5 * and can be replaced with that version at any time 6 * DO NOT EDIT THIS FILE 7 * 8 * Copyright 2004-2010 Analog Devices Inc. 9 * Licensed under the ADI BSD license. 10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd 11 */ 12 13/* This file should be up to date with: 14 * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List 15 */ 16 17#ifndef _MACH_ANOMALY_H_ 18#define _MACH_ANOMALY_H_ 19 20/* We do not support 0.1 silicon - sorry */ 21#if __SILICON_REVISION__ < 2 22# error will not work on BF537 silicon version 0.0 or 0.1 23#endif 24 25#if defined(__ADSPBF534__) 26# define ANOMALY_BF534 1 27#else 28# define ANOMALY_BF534 0 29#endif 30#if defined(__ADSPBF536__) 31# define ANOMALY_BF536 1 32#else 33# define ANOMALY_BF536 0 34#endif 35#if defined(__ADSPBF537__) 36# define ANOMALY_BF537 1 37#else 38# define ANOMALY_BF537 0 39#endif 40 41/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 42#define ANOMALY_05000074 (1) 43/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 44#define ANOMALY_05000119 (1) 45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 46#define ANOMALY_05000122 (1) 47/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ 48#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) 49/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ 50#define ANOMALY_05000180 (1) 51/* Instruction Cache Is Not Functional */ 52#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) 53/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ 54#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) 55/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 56#define ANOMALY_05000245 (1) 57/* Buffered CLKIN Output Is Disabled by Default */ 58#define ANOMALY_05000247 (1) 59/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ 60#define ANOMALY_05000250 (__SILICON_REVISION__ < 3) 61/* EMAC TX DMA Error After an Early Frame Abort */ 62#define ANOMALY_05000252 (__SILICON_REVISION__ < 3) 63/* Maximum External Clock Speed for Timers */ 64#define ANOMALY_05000253 (__SILICON_REVISION__ < 3) 65/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ 66#define ANOMALY_05000254 (__SILICON_REVISION__ > 2) 67/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ 68#define ANOMALY_05000255 (__SILICON_REVISION__ < 3) 69/* EMAC MDIO Input Latched on Wrong MDC Edge */ 70#define ANOMALY_05000256 (__SILICON_REVISION__ < 3) 71/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ 72#define ANOMALY_05000257 (__SILICON_REVISION__ < 3) 73/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ 74#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2) 75/* ICPLB_STATUS MMR Register May Be Corrupted */ 76#define ANOMALY_05000260 (__SILICON_REVISION__ == 2) 77/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ 78#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) 79/* Stores To Data Cache May Be Lost */ 80#define ANOMALY_05000262 (__SILICON_REVISION__ < 3) 81/* Hardware Loop Corrupted When Taking an ICPLB Exception */ 82#define ANOMALY_05000263 (__SILICON_REVISION__ == 2) 83/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ 84#define ANOMALY_05000264 (__SILICON_REVISION__ < 3) 85/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 86#define ANOMALY_05000265 (1) 87/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */ 88#define ANOMALY_05000268 (__SILICON_REVISION__ < 3) 89/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ 90#define ANOMALY_05000270 (__SILICON_REVISION__ < 3) 91/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 92#define ANOMALY_05000272 (1) 93/* Writes to Synchronous SDRAM Memory May Be Lost */ 94#define ANOMALY_05000273 (__SILICON_REVISION__ < 3) 95/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ 96#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) 97/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 98#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) 99/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ 100#define ANOMALY_05000280 (1) 101/* False Hardware Error Exception when ISR Context Is Not Restored */ 102#define ANOMALY_05000281 (__SILICON_REVISION__ < 3) 103/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 104#define ANOMALY_05000282 (__SILICON_REVISION__ < 3) 105/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ 106#define ANOMALY_05000283 (__SILICON_REVISION__ < 3) 107/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */ 108#define ANOMALY_05000285 (__SILICON_REVISION__ < 3) 109/* SPORTs May Receive Bad Data If FIFOs Fill Up */ 110#define ANOMALY_05000288 (__SILICON_REVISION__ < 3) 111/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ 112#define ANOMALY_05000301 (1) 113/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ 114#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) 115/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ 116#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) 117/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 118#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) 119/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */ 120#define ANOMALY_05000309 (__SILICON_REVISION__ < 3) 121/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 122#define ANOMALY_05000310 (1) 123/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 124#define ANOMALY_05000312 (1) 125/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ 126#define ANOMALY_05000313 (1) 127/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ 128#define ANOMALY_05000315 (__SILICON_REVISION__ < 3) 129/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */ 130#define ANOMALY_05000316 (__SILICON_REVISION__ < 3) 131/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */ 132#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) 133/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */ 134#define ANOMALY_05000322 (1) 135/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ 136#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) 137/* UART Gets Disabled after UART Boot */ 138#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) 139/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ 140#define ANOMALY_05000355 (1) 141/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 142#define ANOMALY_05000357 (1) 143/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ 144#define ANOMALY_05000359 (1) 145/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 146#define ANOMALY_05000366 (1) 147/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 148#define ANOMALY_05000371 (1) 149/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ 150#define ANOMALY_05000402 (__SILICON_REVISION__ == 2) 151/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 152#define ANOMALY_05000403 (1) 153/* Speculative Fetches Can Cause Undesired External FIFO Operations */ 154#define ANOMALY_05000416 (1) 155/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ 156#define ANOMALY_05000425 (1) 157/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ 158#define ANOMALY_05000426 (1) 159/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 160#define ANOMALY_05000443 (1) 161/* False Hardware Error when RETI Points to Invalid Memory */ 162#define ANOMALY_05000461 (1) 163/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 164#define ANOMALY_05000473 (1) 165/* Possible Lockup Condition whem Modifying PLL from External Memory */ 166#define ANOMALY_05000475 (1) 167/* TESTSET Instruction Cannot Be Interrupted */ 168#define ANOMALY_05000477 (1) 169/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 170#define ANOMALY_05000481 (1) 171/* IFLUSH sucks at life */ 172#define ANOMALY_05000491 (1) 173 174/* Anomalies that don't exist on this proc */ 175#define ANOMALY_05000099 (0) 176#define ANOMALY_05000120 (0) 177#define ANOMALY_05000125 (0) 178#define ANOMALY_05000149 (0) 179#define ANOMALY_05000158 (0) 180#define ANOMALY_05000171 (0) 181#define ANOMALY_05000179 (0) 182#define ANOMALY_05000182 (0) 183#define ANOMALY_05000183 (0) 184#define ANOMALY_05000189 (0) 185#define ANOMALY_05000198 (0) 186#define ANOMALY_05000202 (0) 187#define ANOMALY_05000215 (0) 188#define ANOMALY_05000219 (0) 189#define ANOMALY_05000220 (0) 190#define ANOMALY_05000227 (0) 191#define ANOMALY_05000230 (0) 192#define ANOMALY_05000231 (0) 193#define ANOMALY_05000233 (0) 194#define ANOMALY_05000234 (0) 195#define ANOMALY_05000242 (0) 196#define ANOMALY_05000248 (0) 197#define ANOMALY_05000266 (0) 198#define ANOMALY_05000274 (0) 199#define ANOMALY_05000287 (0) 200#define ANOMALY_05000311 (0) 201#define ANOMALY_05000323 (0) 202#define ANOMALY_05000353 (1) 203#define ANOMALY_05000362 (1) 204#define ANOMALY_05000363 (0) 205#define ANOMALY_05000364 (0) 206#define ANOMALY_05000380 (0) 207#define ANOMALY_05000386 (1) 208#define ANOMALY_05000389 (0) 209#define ANOMALY_05000400 (0) 210#define ANOMALY_05000412 (0) 211#define ANOMALY_05000430 (0) 212#define ANOMALY_05000432 (0) 213#define ANOMALY_05000435 (0) 214#define ANOMALY_05000447 (0) 215#define ANOMALY_05000448 (0) 216#define ANOMALY_05000456 (0) 217#define ANOMALY_05000450 (0) 218#define ANOMALY_05000465 (0) 219#define ANOMALY_05000467 (0) 220#define ANOMALY_05000474 (0) 221#define ANOMALY_05000485 (0) 222 223#endif 224