1/* -*- linux-c -*- 2 * include/asm-blackfin/ipipe.h 3 * 4 * Copyright (C) 2002-2007 Philippe Gerum. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139, 9 * USA; either version 2 of the License, or (at your option) any later 10 * version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22#ifndef __ASM_BLACKFIN_IPIPE_H 23#define __ASM_BLACKFIN_IPIPE_H 24 25#ifdef CONFIG_IPIPE 26 27#include <linux/cpumask.h> 28#include <linux/list.h> 29#include <linux/threads.h> 30#include <linux/irq.h> 31#include <linux/ipipe_percpu.h> 32#include <asm/ptrace.h> 33#include <asm/irq.h> 34#include <asm/bitops.h> 35#include <asm/atomic.h> 36#include <asm/traps.h> 37 38#define IPIPE_ARCH_STRING "1.12-00" 39#define IPIPE_MAJOR_NUMBER 1 40#define IPIPE_MINOR_NUMBER 12 41#define IPIPE_PATCH_NUMBER 0 42 43#ifdef CONFIG_SMP 44#error "I-pipe/blackfin: SMP not implemented" 45#else /* !CONFIG_SMP */ 46#define ipipe_processor_id() 0 47#endif /* CONFIG_SMP */ 48 49#define prepare_arch_switch(next) \ 50do { \ 51 ipipe_schedule_notify(current, next); \ 52 local_irq_disable_hw(); \ 53} while (0) 54 55#define task_hijacked(p) \ 56 ({ \ 57 int __x__ = __ipipe_root_domain_p; \ 58 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \ 59 if (__x__) \ 60 local_irq_enable_hw(); \ 61 !__x__; \ 62 }) 63 64struct ipipe_domain; 65 66struct ipipe_sysinfo { 67 68 int ncpus; /* Number of CPUs on board */ 69 u64 cpufreq; /* CPU frequency (in Hz) */ 70 71 /* Arch-dependent block */ 72 73 struct { 74 unsigned tmirq; /* Timer tick IRQ */ 75 u64 tmfreq; /* Timer frequency */ 76 } archdep; 77}; 78 79#define ipipe_read_tsc(t) \ 80 ({ \ 81 unsigned long __cy2; \ 82 __asm__ __volatile__ ("1: %0 = CYCLES2\n" \ 83 "%1 = CYCLES\n" \ 84 "%2 = CYCLES2\n" \ 85 "CC = %2 == %0\n" \ 86 "if ! CC jump 1b\n" \ 87 : "=d,a" (((unsigned long *)&t)[1]), \ 88 "=d,a" (((unsigned long *)&t)[0]), \ 89 "=d,a" (__cy2) \ 90 : /*no input*/ : "CC"); \ 91 t; \ 92 }) 93 94#define ipipe_cpu_freq() __ipipe_core_clock 95#define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale) 96#define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1) 97 98/* Private interface -- Internal use only */ 99 100#define __ipipe_check_platform() do { } while (0) 101 102#define __ipipe_init_platform() do { } while (0) 103 104extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; 105 106extern unsigned long __ipipe_irq_lvmask; 107 108extern struct ipipe_domain ipipe_root; 109 110/* enable/disable_irqdesc _must_ be used in pairs. */ 111 112void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, 113 unsigned irq); 114 115void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, 116 unsigned irq); 117 118#define __ipipe_enable_irq(irq) (irq_desc[irq].chip->unmask(irq)) 119 120#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) 121 122static inline int __ipipe_check_tickdev(const char *devname) 123{ 124 return 1; 125} 126 127void __ipipe_enable_pipeline(void); 128 129#define __ipipe_hook_critical_ipi(ipd) do { } while (0) 130 131#define __ipipe_sync_pipeline ___ipipe_sync_pipeline 132void ___ipipe_sync_pipeline(unsigned long syncmask); 133 134void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); 135 136int __ipipe_get_irq_priority(unsigned irq); 137 138void __ipipe_serial_debug(const char *fmt, ...); 139 140asmlinkage void __ipipe_call_irqtail(unsigned long addr); 141 142DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); 143 144extern unsigned long __ipipe_core_clock; 145 146extern unsigned long __ipipe_freq_scale; 147 148extern unsigned long __ipipe_irq_tail_hook; 149 150static inline unsigned long __ipipe_ffnz(unsigned long ul) 151{ 152 return ffs(ul) - 1; 153} 154 155#define __ipipe_run_irqtail() /* Must be a macro */ \ 156 do { \ 157 unsigned long __pending; \ 158 CSYNC(); \ 159 __pending = bfin_read_IPEND(); \ 160 if (__pending & 0x8000) { \ 161 __pending &= ~0x8010; \ 162 if (__pending && (__pending & (__pending - 1)) == 0) \ 163 __ipipe_call_irqtail(__ipipe_irq_tail_hook); \ 164 } \ 165 } while (0) 166 167#define __ipipe_run_isr(ipd, irq) \ 168 do { \ 169 if (!__ipipe_pipeline_head_p(ipd)) \ 170 local_irq_enable_hw(); \ 171 if (ipd == ipipe_root_domain) { \ 172 if (unlikely(ipipe_virtual_irq_p(irq))) { \ 173 irq_enter(); \ 174 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ 175 irq_exit(); \ 176 } else \ 177 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ 178 } else { \ 179 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ 180 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ 181 /* Attempt to exit the outer interrupt level before \ 182 * starting the deferred IRQ processing. */ \ 183 __ipipe_run_irqtail(); \ 184 __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ 185 } \ 186 local_irq_disable_hw(); \ 187 } while (0) 188 189#define __ipipe_syscall_watched_p(p, sc) \ 190 (((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls) 191 192void ipipe_init_irq_threads(void); 193 194int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); 195 196#ifdef CONFIG_TICKSOURCE_CORETMR 197#define IRQ_SYSTMR IRQ_CORETMR 198#define IRQ_PRIOTMR IRQ_CORETMR 199#else 200#define IRQ_SYSTMR IRQ_TIMER0 201#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 202#endif 203 204#ifdef CONFIG_BF561 205#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) 206#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) 207#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) 208#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() 209#elif defined(CONFIG_BF54x) 210#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) 211#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) 212#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) 213#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) 214#endif 215 216#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) 217 218#else /* !CONFIG_IPIPE */ 219 220#define task_hijacked(p) 0 221#define ipipe_trap_notify(t, r) 0 222 223#define ipipe_init_irq_threads() do { } while (0) 224#define ipipe_start_irq_thread(irq, desc) 0 225 226#ifndef CONFIG_TICKSOURCE_GPTMR0 227#define IRQ_SYSTMR IRQ_CORETMR 228#define IRQ_PRIOTMR IRQ_CORETMR 229#else 230#define IRQ_SYSTMR IRQ_TIMER0 231#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 232#endif 233 234#define __ipipe_root_tick_p(regs) 1 235 236#endif /* !CONFIG_IPIPE */ 237 238#define ipipe_update_tick_evtdev(evtdev) do { } while (0) 239 240#endif /* !__ASM_BLACKFIN_IPIPE_H */ 241