1/* 2 * arch/arm/plat-spear/include/plat/shirq.h 3 * 4 * SPEAr platform shared irq layer header file 5 * 6 * Copyright (C) 2009 ST Microelectronics 7 * Viresh Kumar<viresh.kumar@st.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14#ifndef __PLAT_SHIRQ_H 15#define __PLAT_SHIRQ_H 16 17#include <linux/irq.h> 18#include <linux/types.h> 19 20/* 21 * struct shirq_dev_config: shared irq device configuration 22 * 23 * virq: virtual irq number of device 24 * enb_mask: enable mask of device 25 * status_mask: status mask of device 26 * clear_mask: clear mask of device 27 */ 28struct shirq_dev_config { 29 u32 virq; 30 u32 enb_mask; 31 u32 status_mask; 32 u32 clear_mask; 33}; 34 35/* 36 * struct shirq_regs: shared irq register configuration 37 * 38 * base: base address of shared irq register 39 * enb_reg: enable register offset 40 * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt 41 * status_reg: status register offset 42 * status_reg_mask: status register valid mask 43 * clear_reg: clear register offset 44 * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt 45 */ 46struct shirq_regs { 47 void __iomem *base; 48 u32 enb_reg; 49 u32 reset_to_enb; 50 u32 status_reg; 51 u32 status_reg_mask; 52 u32 clear_reg; 53 u32 reset_to_clear; 54}; 55 56/* 57 * struct spear_shirq: shared irq structure 58 * 59 * irq: hardware irq number 60 * dev_config: array of device config structures which are using "irq" line 61 * dev_count: size of dev_config array 62 * regs: register configuration for shared irq block 63 */ 64struct spear_shirq { 65 u32 irq; 66 struct shirq_dev_config *dev_config; 67 u32 dev_count; 68 struct shirq_regs regs; 69}; 70 71int spear_shirq_register(struct spear_shirq *shirq); 72 73#endif /* __PLAT_SHIRQ_H */ 74