1/* 2 * OMAP2/3 powerdomain control 3 * 4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 5 * Copyright (C) 2007-2009 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN 15#define ASM_ARM_ARCH_OMAP_POWERDOMAIN 16 17#include <linux/types.h> 18#include <linux/list.h> 19 20#include <asm/atomic.h> 21 22#include <plat/cpu.h> 23 24 25/* Powerdomain basic power states */ 26#define PWRDM_POWER_OFF 0x0 27#define PWRDM_POWER_RET 0x1 28#define PWRDM_POWER_INACTIVE 0x2 29#define PWRDM_POWER_ON 0x3 30 31#define PWRDM_MAX_PWRSTS 4 32 33/* Powerdomain allowable state bitfields */ 34#define PWRSTS_ON (1 << PWRDM_POWER_ON) 35#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ 36 (1 << PWRDM_POWER_ON)) 37 38#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ 39 (1 << PWRDM_POWER_RET)) 40 41#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ 42 (1 << PWRDM_POWER_ON)) 43 44#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) 45 46 47/* Powerdomain flags */ 48#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ 49#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits 50 * in MEM bank 1 position. This is 51 * true for OMAP3430 52 */ 53#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* 54 * support to transition from a 55 * sleep state to a lower sleep 56 * state without waking up the 57 * powerdomain 58 */ 59 60/* 61 * Number of memory banks that are power-controllable. On OMAP4430, the 62 * maximum is 5. 63 */ 64#define PWRDM_MAX_MEM_BANKS 5 65 66/* 67 * Maximum number of clockdomains that can be associated with a powerdomain. 68 * CORE powerdomain on OMAP4 is the worst case 69 */ 70#define PWRDM_MAX_CLKDMS 9 71 72#define PWRDM_TRANSITION_BAILOUT 100000 73 74struct clockdomain; 75struct powerdomain; 76 77/** 78 * struct powerdomain - OMAP powerdomain 79 * @name: Powerdomain name 80 * @omap_chip: represents the OMAP chip types containing this pwrdm 81 * @prcm_offs: the address offset from CM_BASE/PRM_BASE 82 * @pwrsts: Possible powerdomain power states 83 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION 84 * @flags: Powerdomain flags 85 * @banks: Number of software-controllable memory banks in this powerdomain 86 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION 87 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON 88 * @pwrdm_clkdms: Clockdomains in this powerdomain 89 * @node: list_head linking all powerdomains 90 * @state: 91 * @state_counter: 92 * @timer: 93 * @state_timer: 94 */ 95struct powerdomain { 96 const char *name; 97 const struct omap_chip_id omap_chip; 98 const s16 prcm_offs; 99 const u8 pwrsts; 100 const u8 pwrsts_logic_ret; 101 const u8 flags; 102 const u8 banks; 103 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; 104 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; 105 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; 106 struct list_head node; 107 int state; 108 unsigned state_counter[PWRDM_MAX_PWRSTS]; 109 unsigned ret_logic_off_counter; 110 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; 111 112#ifdef CONFIG_PM_DEBUG 113 s64 timer; 114 s64 state_timer[PWRDM_MAX_PWRSTS]; 115#endif 116}; 117 118 119void pwrdm_init(struct powerdomain **pwrdm_list); 120 121struct powerdomain *pwrdm_lookup(const char *name); 122 123int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), 124 void *user); 125int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), 126 void *user); 127 128int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); 129int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); 130int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, 131 int (*fn)(struct powerdomain *pwrdm, 132 struct clockdomain *clkdm)); 133 134int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); 135 136int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); 137int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); 138int pwrdm_read_pwrst(struct powerdomain *pwrdm); 139int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); 140int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); 141 142int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); 143int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 144int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 145 146int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); 147int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); 148int pwrdm_read_logic_retst(struct powerdomain *pwrdm); 149int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); 150int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); 151int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); 152 153int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); 154int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); 155bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); 156 157int pwrdm_wait_transition(struct powerdomain *pwrdm); 158 159int pwrdm_state_switch(struct powerdomain *pwrdm); 160int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); 161int pwrdm_pre_transition(void); 162int pwrdm_post_transition(void); 163 164#endif 165