1/* 2 * General-Purpose Memory Controller for OMAP2 3 * 4 * Copyright (C) 2005-2006 Nokia Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#ifndef __OMAP2_GPMC_H 12#define __OMAP2_GPMC_H 13 14/* Maximum Number of Chip Selects */ 15#define GPMC_CS_NUM 8 16 17#define GPMC_CS_CONFIG1 0x00 18#define GPMC_CS_CONFIG2 0x04 19#define GPMC_CS_CONFIG3 0x08 20#define GPMC_CS_CONFIG4 0x0c 21#define GPMC_CS_CONFIG5 0x10 22#define GPMC_CS_CONFIG6 0x14 23#define GPMC_CS_CONFIG7 0x18 24#define GPMC_CS_NAND_COMMAND 0x1c 25#define GPMC_CS_NAND_ADDRESS 0x20 26#define GPMC_CS_NAND_DATA 0x24 27 28/* Control Commands */ 29#define GPMC_CONFIG_RDY_BSY 0x00000001 30#define GPMC_CONFIG_DEV_SIZE 0x00000002 31#define GPMC_CONFIG_DEV_TYPE 0x00000003 32#define GPMC_SET_IRQ_STATUS 0x00000004 33#define GPMC_CONFIG_WP 0x00000005 34 35#define GPMC_GET_IRQ_STATUS 0x00000006 36#define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */ 37#define GPMC_PREFETCH_COUNT 0x00000008 /* remaining bytes to be read/write*/ 38#define GPMC_STATUS_BUFFER 0x00000009 /* 1: buffer is available to write */ 39 40#define GPMC_NAND_COMMAND 0x0000000a 41#define GPMC_NAND_ADDRESS 0x0000000b 42#define GPMC_NAND_DATA 0x0000000c 43 44/* ECC commands */ 45#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ 46#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ 47#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ 48 49#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 50#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 51#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 52#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) 53#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) 54#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) 55#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) 56#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) 57#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) 58#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) 59#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) 60#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18) 61#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) 62#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) 63#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) 64#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) 65#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) 66#define GPMC_CONFIG1_MUXADDDATA (1 << 9) 67#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) 68#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) 69#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) 70#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) 71#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) 72#define GPMC_CONFIG7_CSVALID (1 << 6) 73 74#define GPMC_DEVICETYPE_NOR 0 75#define GPMC_DEVICETYPE_NAND 2 76#define GPMC_CONFIG_WRITEPROTECT 0x00000010 77#define GPMC_STATUS_BUFF_EMPTY 0x00000001 78#define WR_RD_PIN_MONITORING 0x00600000 79#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) 80#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) 81 82/* 83 * Note that all values in this struct are in nanoseconds, while 84 * the register values are in gpmc_fck cycles. 85 */ 86struct gpmc_timings { 87 /* Minimum clock period for synchronous mode */ 88 u16 sync_clk; 89 90 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ 91 u16 cs_on; /* Assertion time */ 92 u16 cs_rd_off; /* Read deassertion time */ 93 u16 cs_wr_off; /* Write deassertion time */ 94 95 /* ADV signal timings corresponding to GPMC_CONFIG3 */ 96 u16 adv_on; /* Assertion time */ 97 u16 adv_rd_off; /* Read deassertion time */ 98 u16 adv_wr_off; /* Write deassertion time */ 99 100 /* WE signals timings corresponding to GPMC_CONFIG4 */ 101 u16 we_on; /* WE assertion time */ 102 u16 we_off; /* WE deassertion time */ 103 104 /* OE signals timings corresponding to GPMC_CONFIG4 */ 105 u16 oe_on; /* OE assertion time */ 106 u16 oe_off; /* OE deassertion time */ 107 108 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ 109 u16 page_burst_access; /* Multiple access word delay */ 110 u16 access; /* Start-cycle to first data valid delay */ 111 u16 rd_cycle; /* Total read cycle time */ 112 u16 wr_cycle; /* Total write cycle time */ 113 114 /* The following are only on OMAP3430 */ 115 u16 wr_access; /* WRACCESSTIME */ 116 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ 117}; 118 119extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); 120extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); 121extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); 122extern unsigned long gpmc_get_fclk_period(void); 123 124extern void gpmc_cs_write_reg(int cs, int idx, u32 val); 125extern u32 gpmc_cs_read_reg(int cs, int idx); 126extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk); 127extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); 128extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); 129extern void gpmc_cs_free(int cs); 130extern int gpmc_cs_set_reserved(int cs, int reserved); 131extern int gpmc_cs_reserved(int cs); 132extern int gpmc_prefetch_enable(int cs, int dma_mode, 133 unsigned int u32_count, int is_write); 134extern int gpmc_prefetch_reset(int cs); 135extern void omap3_gpmc_save_context(void); 136extern void omap3_gpmc_restore_context(void); 137extern void gpmc_init(void); 138extern int gpmc_read_status(int cmd); 139extern int gpmc_cs_configure(int cs, int cmd, int wval); 140extern int gpmc_nand_read(int cs, int cmd); 141extern int gpmc_nand_write(int cs, int cmd, int wval); 142 143int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size); 144int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code); 145#endif 146