1/* 2 * arch/arm/plat-omap/include/mach/dma.h 3 * 4 * Copyright (C) 2003 Nokia Corporation 5 * Author: Juha Yrj��l�� <juha.yrjola@nokia.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21#ifndef __ASM_ARCH_DMA_H 22#define __ASM_ARCH_DMA_H 23 24/* Move omap4 specific defines to dma-44xx.h */ 25#include "dma-44xx.h" 26 27/* Hardware registers for omap1 */ 28#define OMAP1_DMA_BASE (0xfffed800) 29 30#define OMAP1_DMA_GCR 0x400 31#define OMAP1_DMA_GSCR 0x404 32#define OMAP1_DMA_GRST 0x408 33#define OMAP1_DMA_HW_ID 0x442 34#define OMAP1_DMA_PCH2_ID 0x444 35#define OMAP1_DMA_PCH0_ID 0x446 36#define OMAP1_DMA_PCH1_ID 0x448 37#define OMAP1_DMA_PCHG_ID 0x44a 38#define OMAP1_DMA_PCHD_ID 0x44c 39#define OMAP1_DMA_CAPS_0_U 0x44e 40#define OMAP1_DMA_CAPS_0_L 0x450 41#define OMAP1_DMA_CAPS_1_U 0x452 42#define OMAP1_DMA_CAPS_1_L 0x454 43#define OMAP1_DMA_CAPS_2 0x456 44#define OMAP1_DMA_CAPS_3 0x458 45#define OMAP1_DMA_CAPS_4 0x45a 46#define OMAP1_DMA_PCH2_SR 0x460 47#define OMAP1_DMA_PCH0_SR 0x480 48#define OMAP1_DMA_PCH1_SR 0x482 49#define OMAP1_DMA_PCHD_SR 0x4c0 50 51/* Hardware registers for omap2 and omap3 */ 52#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) 53#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) 54#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000) 55 56#define OMAP_DMA4_REVISION 0x00 57#define OMAP_DMA4_GCR 0x78 58#define OMAP_DMA4_IRQSTATUS_L0 0x08 59#define OMAP_DMA4_IRQSTATUS_L1 0x0c 60#define OMAP_DMA4_IRQSTATUS_L2 0x10 61#define OMAP_DMA4_IRQSTATUS_L3 0x14 62#define OMAP_DMA4_IRQENABLE_L0 0x18 63#define OMAP_DMA4_IRQENABLE_L1 0x1c 64#define OMAP_DMA4_IRQENABLE_L2 0x20 65#define OMAP_DMA4_IRQENABLE_L3 0x24 66#define OMAP_DMA4_SYSSTATUS 0x28 67#define OMAP_DMA4_OCP_SYSCONFIG 0x2c 68#define OMAP_DMA4_CAPS_0 0x64 69#define OMAP_DMA4_CAPS_2 0x6c 70#define OMAP_DMA4_CAPS_3 0x70 71#define OMAP_DMA4_CAPS_4 0x74 72 73#define OMAP1_LOGICAL_DMA_CH_COUNT 17 74#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ 75 76/* Common channel specific registers for omap1 */ 77#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00) 78#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00) 79#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02) 80#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04) 81#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06) 82#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10) 83#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12) 84#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14) 85#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16) 86#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */ 87#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18) 88#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a) 89#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c) 90#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e) 91#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28) 92 93/* Common channel specific registers for omap2 */ 94#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80) 95#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80) 96#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84) 97#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88) 98#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c) 99#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90) 100#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94) 101#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98) 102#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4) 103#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8) 104#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac) 105#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0) 106#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4) 107#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8) 108 109/* Channel specific registers only on omap1 */ 110#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08) 111#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a) 112#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c) 113#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e) 114#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20) 115#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22) 116#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24) 117#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */ 118#define OMAP1_DMA_CCEN(n) 0 119#define OMAP1_DMA_CCFN(n) 0 120 121/* Channel specific registers only on omap2 */ 122#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c) 123#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0) 124#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc) 125#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) 126#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) 127 128/* Additional registers available on OMAP4 */ 129#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0) 130#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4) 131#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8) 132 133/* Dummy defines to keep multi-omap compiles happy */ 134#define OMAP1_DMA_REVISION 0 135#define OMAP1_DMA_IRQSTATUS_L0 0 136#define OMAP1_DMA_IRQENABLE_L0 0 137#define OMAP1_DMA_OCP_SYSCONFIG 0 138#define OMAP_DMA4_HW_ID 0 139#define OMAP_DMA4_CAPS_0_L 0 140#define OMAP_DMA4_CAPS_0_U 0 141#define OMAP_DMA4_CAPS_1_L 0 142#define OMAP_DMA4_CAPS_1_U 0 143#define OMAP_DMA4_GSCR 0 144#define OMAP_DMA4_CPC(n) 0 145 146#define OMAP_DMA4_LCH_CTRL(n) 0 147#define OMAP_DMA4_COLOR_L(n) 0 148#define OMAP_DMA4_COLOR_U(n) 0 149#define OMAP_DMA4_CCR2(n) 0 150#define OMAP1_DMA_CSSA(n) 0 151#define OMAP1_DMA_CDSA(n) 0 152#define OMAP_DMA4_CSSA_L(n) 0 153#define OMAP_DMA4_CSSA_U(n) 0 154#define OMAP_DMA4_CDSA_L(n) 0 155#define OMAP_DMA4_CDSA_U(n) 0 156#define OMAP1_DMA_COLOR(n) 0 157 158/*----------------------------------------------------------------------------*/ 159 160/* DMA channels for omap1 */ 161#define OMAP_DMA_NO_DEVICE 0 162#define OMAP_DMA_MCSI1_TX 1 163#define OMAP_DMA_MCSI1_RX 2 164#define OMAP_DMA_I2C_RX 3 165#define OMAP_DMA_I2C_TX 4 166#define OMAP_DMA_EXT_NDMA_REQ 5 167#define OMAP_DMA_EXT_NDMA_REQ2 6 168#define OMAP_DMA_UWIRE_TX 7 169#define OMAP_DMA_MCBSP1_TX 8 170#define OMAP_DMA_MCBSP1_RX 9 171#define OMAP_DMA_MCBSP3_TX 10 172#define OMAP_DMA_MCBSP3_RX 11 173#define OMAP_DMA_UART1_TX 12 174#define OMAP_DMA_UART1_RX 13 175#define OMAP_DMA_UART2_TX 14 176#define OMAP_DMA_UART2_RX 15 177#define OMAP_DMA_MCBSP2_TX 16 178#define OMAP_DMA_MCBSP2_RX 17 179#define OMAP_DMA_UART3_TX 18 180#define OMAP_DMA_UART3_RX 19 181#define OMAP_DMA_CAMERA_IF_RX 20 182#define OMAP_DMA_MMC_TX 21 183#define OMAP_DMA_MMC_RX 22 184#define OMAP_DMA_NAND 23 185#define OMAP_DMA_IRQ_LCD_LINE 24 186#define OMAP_DMA_MEMORY_STICK 25 187#define OMAP_DMA_USB_W2FC_RX0 26 188#define OMAP_DMA_USB_W2FC_RX1 27 189#define OMAP_DMA_USB_W2FC_RX2 28 190#define OMAP_DMA_USB_W2FC_TX0 29 191#define OMAP_DMA_USB_W2FC_TX1 30 192#define OMAP_DMA_USB_W2FC_TX2 31 193 194/* These are only for 1610 */ 195#define OMAP_DMA_CRYPTO_DES_IN 32 196#define OMAP_DMA_SPI_TX 33 197#define OMAP_DMA_SPI_RX 34 198#define OMAP_DMA_CRYPTO_HASH 35 199#define OMAP_DMA_CCP_ATTN 36 200#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 201#define OMAP_DMA_CMT_APE_TX_CHAN_0 38 202#define OMAP_DMA_CMT_APE_RV_CHAN_0 39 203#define OMAP_DMA_CMT_APE_TX_CHAN_1 40 204#define OMAP_DMA_CMT_APE_RV_CHAN_1 41 205#define OMAP_DMA_CMT_APE_TX_CHAN_2 42 206#define OMAP_DMA_CMT_APE_RV_CHAN_2 43 207#define OMAP_DMA_CMT_APE_TX_CHAN_3 44 208#define OMAP_DMA_CMT_APE_RV_CHAN_3 45 209#define OMAP_DMA_CMT_APE_TX_CHAN_4 46 210#define OMAP_DMA_CMT_APE_RV_CHAN_4 47 211#define OMAP_DMA_CMT_APE_TX_CHAN_5 48 212#define OMAP_DMA_CMT_APE_RV_CHAN_5 49 213#define OMAP_DMA_CMT_APE_TX_CHAN_6 50 214#define OMAP_DMA_CMT_APE_RV_CHAN_6 51 215#define OMAP_DMA_CMT_APE_TX_CHAN_7 52 216#define OMAP_DMA_CMT_APE_RV_CHAN_7 53 217#define OMAP_DMA_MMC2_TX 54 218#define OMAP_DMA_MMC2_RX 55 219#define OMAP_DMA_CRYPTO_DES_OUT 56 220 221/* DMA channels for 24xx */ 222#define OMAP24XX_DMA_NO_DEVICE 0 223#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ 224#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ 225#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ 226#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ 227#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ 228#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ 229#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */ 230#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */ 231#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ 232#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ 233#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ 234#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ 235#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ 236#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ 237#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */ 238#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ 239#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ 240#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ 241#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */ 242#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */ 243#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ 244#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ 245#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ 246#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ 247#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ 248#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ 249#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ 250#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ 251#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */ 252#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ 253#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ 254#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */ 255#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */ 256#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */ 257#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */ 258#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */ 259#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */ 260#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ 261#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ 262#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */ 263#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */ 264#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ 265#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ 266#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ 267#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ 268#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ 269#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ 270#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */ 271#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */ 272#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */ 273#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */ 274#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ 275#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ 276#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ 277#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ 278#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ 279#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ 280#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ 281#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ 282#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ 283#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ 284#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ 285#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ 286#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ 287#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ 288#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ 289#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */ 290#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */ 291#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ 292#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ 293#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ 294#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */ 295#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */ 296#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */ 297#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */ 298#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */ 299#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */ 300#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ 301#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ 302#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */ 303#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ 304#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */ 305#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */ 306#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ 307#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ 308#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */ 309#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */ 310#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ 311#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ 312#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ 313#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */ 314#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */ 315#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */ 316#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */ 317#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */ 318#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */ 319#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ 320#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ 321 322/*----------------------------------------------------------------------------*/ 323 324#define OMAP1_DMA_TOUT_IRQ (1 << 0) 325#define OMAP_DMA_DROP_IRQ (1 << 1) 326#define OMAP_DMA_HALF_IRQ (1 << 2) 327#define OMAP_DMA_FRAME_IRQ (1 << 3) 328#define OMAP_DMA_LAST_IRQ (1 << 4) 329#define OMAP_DMA_BLOCK_IRQ (1 << 5) 330#define OMAP1_DMA_SYNC_IRQ (1 << 6) 331#define OMAP2_DMA_PKT_IRQ (1 << 7) 332#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8) 333#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9) 334#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) 335#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) 336 337#define OMAP_DMA_CCR_EN (1 << 7) 338#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9) 339#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10) 340#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24) 341#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25) 342 343#define OMAP_DMA_DATA_TYPE_S8 0x00 344#define OMAP_DMA_DATA_TYPE_S16 0x01 345#define OMAP_DMA_DATA_TYPE_S32 0x02 346 347#define OMAP_DMA_SYNC_ELEMENT 0x00 348#define OMAP_DMA_SYNC_FRAME 0x01 349#define OMAP_DMA_SYNC_BLOCK 0x02 350#define OMAP_DMA_SYNC_PACKET 0x03 351 352#define OMAP_DMA_DST_SYNC_PREFETCH 0x02 353#define OMAP_DMA_SRC_SYNC 0x01 354#define OMAP_DMA_DST_SYNC 0x00 355 356#define OMAP_DMA_PORT_EMIFF 0x00 357#define OMAP_DMA_PORT_EMIFS 0x01 358#define OMAP_DMA_PORT_OCP_T1 0x02 359#define OMAP_DMA_PORT_TIPB 0x03 360#define OMAP_DMA_PORT_OCP_T2 0x04 361#define OMAP_DMA_PORT_MPUI 0x05 362 363#define OMAP_DMA_AMODE_CONSTANT 0x00 364#define OMAP_DMA_AMODE_POST_INC 0x01 365#define OMAP_DMA_AMODE_SINGLE_IDX 0x02 366#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 367 368#define DMA_DEFAULT_FIFO_DEPTH 0x10 369#define DMA_DEFAULT_ARB_RATE 0x01 370/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */ 371#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */ 372#define DMA_THREAD_RESERVE_ONET (0x01 << 12) 373#define DMA_THREAD_RESERVE_TWOT (0x02 << 12) 374#define DMA_THREAD_RESERVE_THREET (0x03 << 12) 375#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */ 376#define DMA_THREAD_FIFO_75 (0x01 << 14) 377#define DMA_THREAD_FIFO_25 (0x02 << 14) 378#define DMA_THREAD_FIFO_50 (0x03 << 14) 379 380/* DMA4_OCP_SYSCONFIG bits */ 381#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12) 382#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8) 383#define DMA_SYSCONFIG_EMUFREE (1 << 5) 384#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3) 385#define DMA_SYSCONFIG_SOFTRESET (1 << 2) 386#define DMA_SYSCONFIG_AUTOIDLE (1 << 0) 387 388#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12) 389#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3) 390 391#define DMA_IDLEMODE_SMARTIDLE 0x2 392#define DMA_IDLEMODE_NO_IDLE 0x1 393#define DMA_IDLEMODE_FORCE_IDLE 0x0 394 395/* Chaining modes*/ 396#ifndef CONFIG_ARCH_OMAP1 397#define OMAP_DMA_STATIC_CHAIN 0x1 398#define OMAP_DMA_DYNAMIC_CHAIN 0x2 399#define OMAP_DMA_CHAIN_ACTIVE 0x1 400#define OMAP_DMA_CHAIN_INACTIVE 0x0 401#endif 402 403#define DMA_CH_PRIO_HIGH 0x1 404#define DMA_CH_PRIO_LOW 0x0 /* Def */ 405 406enum omap_dma_burst_mode { 407 OMAP_DMA_DATA_BURST_DIS = 0, 408 OMAP_DMA_DATA_BURST_4, 409 OMAP_DMA_DATA_BURST_8, 410 OMAP_DMA_DATA_BURST_16, 411}; 412 413enum end_type { 414 OMAP_DMA_LITTLE_ENDIAN = 0, 415 OMAP_DMA_BIG_ENDIAN 416}; 417 418enum omap_dma_color_mode { 419 OMAP_DMA_COLOR_DIS = 0, 420 OMAP_DMA_CONSTANT_FILL, 421 OMAP_DMA_TRANSPARENT_COPY 422}; 423 424enum omap_dma_write_mode { 425 OMAP_DMA_WRITE_NON_POSTED = 0, 426 OMAP_DMA_WRITE_POSTED, 427 OMAP_DMA_WRITE_LAST_NON_POSTED 428}; 429 430enum omap_dma_channel_mode { 431 OMAP_DMA_LCH_2D = 0, 432 OMAP_DMA_LCH_G, 433 OMAP_DMA_LCH_P, 434 OMAP_DMA_LCH_PD 435}; 436 437struct omap_dma_channel_params { 438 int data_type; /* data type 8,16,32 */ 439 int elem_count; /* number of elements in a frame */ 440 int frame_count; /* number of frames in a element */ 441 442 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ 443 int src_amode; /* constant, post increment, indexed, 444 double indexed */ 445 unsigned long src_start; /* source address : physical */ 446 int src_ei; /* source element index */ 447 int src_fi; /* source frame index */ 448 449 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ 450 int dst_amode; /* constant, post increment, indexed, 451 double indexed */ 452 unsigned long dst_start; /* source address : physical */ 453 int dst_ei; /* source element index */ 454 int dst_fi; /* source frame index */ 455 456 int trigger; /* trigger attached if the channel is 457 synchronized */ 458 int sync_mode; /* sycn on element, frame , block or packet */ 459 int src_or_dst_synch; /* source synch(1) or destination synch(0) */ 460 461 int ie; /* interrupt enabled */ 462 463 unsigned char read_prio;/* read priority */ 464 unsigned char write_prio;/* write priority */ 465 466#ifndef CONFIG_ARCH_OMAP1 467 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */ 468#endif 469}; 470 471 472extern void omap_set_dma_priority(int lch, int dst_port, int priority); 473extern int omap_request_dma(int dev_id, const char *dev_name, 474 void (*callback)(int lch, u16 ch_status, void *data), 475 void *data, int *dma_ch); 476extern void omap_enable_dma_irq(int ch, u16 irq_bits); 477extern void omap_disable_dma_irq(int ch, u16 irq_bits); 478extern void omap_free_dma(int ch); 479extern void omap_start_dma(int lch); 480extern void omap_stop_dma(int lch); 481extern void omap_set_dma_transfer_params(int lch, int data_type, 482 int elem_count, int frame_count, 483 int sync_mode, 484 int dma_trigger, int src_or_dst_synch); 485extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, 486 u32 color); 487extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); 488extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode); 489 490extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, 491 unsigned long src_start, 492 int src_ei, int src_fi); 493extern void omap_set_dma_src_index(int lch, int eidx, int fidx); 494extern void omap_set_dma_src_data_pack(int lch, int enable); 495extern void omap_set_dma_src_burst_mode(int lch, 496 enum omap_dma_burst_mode burst_mode); 497 498extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, 499 unsigned long dest_start, 500 int dst_ei, int dst_fi); 501extern void omap_set_dma_dest_index(int lch, int eidx, int fidx); 502extern void omap_set_dma_dest_data_pack(int lch, int enable); 503extern void omap_set_dma_dest_burst_mode(int lch, 504 enum omap_dma_burst_mode burst_mode); 505 506extern void omap_set_dma_params(int lch, 507 struct omap_dma_channel_params *params); 508 509extern void omap_dma_link_lch(int lch_head, int lch_queue); 510extern void omap_dma_unlink_lch(int lch_head, int lch_queue); 511 512extern int omap_set_dma_callback(int lch, 513 void (*callback)(int lch, u16 ch_status, void *data), 514 void *data); 515extern dma_addr_t omap_get_dma_src_pos(int lch); 516extern dma_addr_t omap_get_dma_dst_pos(int lch); 517extern void omap_clear_dma(int lch); 518extern int omap_get_dma_active_status(int lch); 519extern int omap_dma_running(void); 520extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, 521 int tparams); 522extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, 523 unsigned char write_prio); 524extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype); 525extern void omap_set_dma_src_endian_type(int lch, enum end_type etype); 526extern int omap_get_dma_index(int lch, int *ei, int *fi); 527 528void omap_dma_global_context_save(void); 529void omap_dma_global_context_restore(void); 530 531extern void omap_dma_disable_irq(int lch); 532 533/* Chaining APIs */ 534#ifndef CONFIG_ARCH_OMAP1 535extern int omap_request_dma_chain(int dev_id, const char *dev_name, 536 void (*callback) (int lch, u16 ch_status, 537 void *data), 538 int *chain_id, int no_of_chans, 539 int chain_mode, 540 struct omap_dma_channel_params params); 541extern int omap_free_dma_chain(int chain_id); 542extern int omap_dma_chain_a_transfer(int chain_id, int src_start, 543 int dest_start, int elem_count, 544 int frame_count, void *callbk_data); 545extern int omap_start_dma_chain_transfers(int chain_id); 546extern int omap_stop_dma_chain_transfers(int chain_id); 547extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi); 548extern int omap_get_dma_chain_dst_pos(int chain_id); 549extern int omap_get_dma_chain_src_pos(int chain_id); 550 551extern int omap_modify_dma_chain_params(int chain_id, 552 struct omap_dma_channel_params params); 553extern int omap_dma_chain_status(int chain_id); 554#endif 555 556#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP) 557#include <mach/lcd_dma.h> 558#else 559static inline int omap_lcd_dma_running(void) 560{ 561 return 0; 562} 563#endif 564 565#endif /* __ASM_ARCH_DMA_H */ 566