1/* 2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020 3 * 4 * Copyright (C) 2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * 23 * These are the low level assembler for performing cache and TLB 24 * functions on the arm1020e. 25 * 26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt 27 */ 28#include <linux/linkage.h> 29#include <linux/init.h> 30#include <asm/assembler.h> 31#include <asm/asm-offsets.h> 32#include <asm/hwcap.h> 33#include <asm/pgtable-hwdef.h> 34#include <asm/pgtable.h> 35#include <asm/ptrace.h> 36 37#include "proc-macros.S" 38 39/* 40 * This is the maximum size of an area which will be invalidated 41 * using the single invalidate entry instructions. Anything larger 42 * than this, and we go for the whole cache. 43 * 44 * This value should be chosen such that we choose the cheapest 45 * alternative. 46 */ 47#define MAX_AREA_SIZE 32768 48 49/* 50 * The size of one data cache line. 51 */ 52#define CACHE_DLINESIZE 32 53 54/* 55 * The number of data cache segments. 56 */ 57#define CACHE_DSEGMENTS 16 58 59/* 60 * The number of lines in a cache segment. 61 */ 62#define CACHE_DENTRIES 64 63 64/* 65 * This is the size at which it becomes more efficient to 66 * clean the whole cache, rather than using the individual 67 * cache line maintainence instructions. 68 */ 69#define CACHE_DLIMIT 32768 70 71 .text 72/* 73 * cpu_arm1020e_proc_init() 74 */ 75ENTRY(cpu_arm1020e_proc_init) 76 mov pc, lr 77 78/* 79 * cpu_arm1020e_proc_fin() 80 */ 81ENTRY(cpu_arm1020e_proc_fin) 82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 83 bic r0, r0, #0x1000 @ ...i............ 84 bic r0, r0, #0x000e @ ............wca. 85 mcr p15, 0, r0, c1, c0, 0 @ disable caches 86 mov pc, lr 87 88/* 89 * cpu_arm1020e_reset(loc) 90 * 91 * Perform a soft reset of the system. Put the CPU into the 92 * same state as it would be if it had been reset, and branch 93 * to what would be the reset vector. 94 * 95 * loc: location to jump to for soft reset 96 */ 97 .align 5 98ENTRY(cpu_arm1020e_reset) 99 mov ip, #0 100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 101 mcr p15, 0, ip, c7, c10, 4 @ drain WB 102#ifdef CONFIG_MMU 103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 104#endif 105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 106 bic ip, ip, #0x000f @ ............wcam 107 bic ip, ip, #0x1100 @ ...i...s........ 108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 109 mov pc, r0 110 111/* 112 * cpu_arm1020e_do_idle() 113 */ 114 .align 5 115ENTRY(cpu_arm1020e_do_idle) 116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 117 mov pc, lr 118 119/* ================================= CACHE ================================ */ 120 121 .align 5 122/* 123 * flush_user_cache_all() 124 * 125 * Invalidate all cache entries in a particular address 126 * space. 127 */ 128ENTRY(arm1020e_flush_user_cache_all) 129 /* FALLTHROUGH */ 130/* 131 * flush_kern_cache_all() 132 * 133 * Clean and invalidate the entire cache. 134 */ 135ENTRY(arm1020e_flush_kern_cache_all) 136 mov r2, #VM_EXEC 137 mov ip, #0 138__flush_whole_cache: 139#ifndef CONFIG_CPU_DCACHE_DISABLE 140 mcr p15, 0, ip, c7, c10, 4 @ drain WB 141 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 1421: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1432: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 144 subs r3, r3, #1 << 26 145 bcs 2b @ entries 63 to 0 146 subs r1, r1, #1 << 5 147 bcs 1b @ segments 15 to 0 148#endif 149 tst r2, #VM_EXEC 150#ifndef CONFIG_CPU_ICACHE_DISABLE 151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 152#endif 153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 154 mov pc, lr 155 156/* 157 * flush_user_cache_range(start, end, flags) 158 * 159 * Invalidate a range of cache entries in the specified 160 * address space. 161 * 162 * - start - start address (inclusive) 163 * - end - end address (exclusive) 164 * - flags - vm_flags for this space 165 */ 166ENTRY(arm1020e_flush_user_cache_range) 167 mov ip, #0 168 sub r3, r1, r0 @ calculate total size 169 cmp r3, #CACHE_DLIMIT 170 bhs __flush_whole_cache 171 172#ifndef CONFIG_CPU_DCACHE_DISABLE 1731: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 174 add r0, r0, #CACHE_DLINESIZE 175 cmp r0, r1 176 blo 1b 177#endif 178 tst r2, #VM_EXEC 179#ifndef CONFIG_CPU_ICACHE_DISABLE 180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 181#endif 182 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 183 mov pc, lr 184 185/* 186 * coherent_kern_range(start, end) 187 * 188 * Ensure coherency between the Icache and the Dcache in the 189 * region described by start. If you have non-snooping 190 * Harvard caches, you need to implement this function. 191 * 192 * - start - virtual start address 193 * - end - virtual end address 194 */ 195ENTRY(arm1020e_coherent_kern_range) 196 /* FALLTHROUGH */ 197/* 198 * coherent_user_range(start, end) 199 * 200 * Ensure coherency between the Icache and the Dcache in the 201 * region described by start. If you have non-snooping 202 * Harvard caches, you need to implement this function. 203 * 204 * - start - virtual start address 205 * - end - virtual end address 206 */ 207ENTRY(arm1020e_coherent_user_range) 208 mov ip, #0 209 bic r0, r0, #CACHE_DLINESIZE - 1 2101: 211#ifndef CONFIG_CPU_DCACHE_DISABLE 212 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 213#endif 214#ifndef CONFIG_CPU_ICACHE_DISABLE 215 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 216#endif 217 add r0, r0, #CACHE_DLINESIZE 218 cmp r0, r1 219 blo 1b 220 mcr p15, 0, ip, c7, c10, 4 @ drain WB 221 mov pc, lr 222 223/* 224 * flush_kern_dcache_area(void *addr, size_t size) 225 * 226 * Ensure no D cache aliasing occurs, either with itself or 227 * the I cache 228 * 229 * - addr - kernel address 230 * - size - region size 231 */ 232ENTRY(arm1020e_flush_kern_dcache_area) 233 mov ip, #0 234#ifndef CONFIG_CPU_DCACHE_DISABLE 235 add r1, r0, r1 2361: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 237 add r0, r0, #CACHE_DLINESIZE 238 cmp r0, r1 239 blo 1b 240#endif 241 mcr p15, 0, ip, c7, c10, 4 @ drain WB 242 mov pc, lr 243 244/* 245 * dma_inv_range(start, end) 246 * 247 * Invalidate (discard) the specified virtual address range. 248 * May not write back any entries. If 'start' or 'end' 249 * are not cache line aligned, those lines must be written 250 * back. 251 * 252 * - start - virtual start address 253 * - end - virtual end address 254 * 255 * (same as v4wb) 256 */ 257arm1020e_dma_inv_range: 258 mov ip, #0 259#ifndef CONFIG_CPU_DCACHE_DISABLE 260 tst r0, #CACHE_DLINESIZE - 1 261 bic r0, r0, #CACHE_DLINESIZE - 1 262 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 263 tst r1, #CACHE_DLINESIZE - 1 264 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 2651: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 266 add r0, r0, #CACHE_DLINESIZE 267 cmp r0, r1 268 blo 1b 269#endif 270 mcr p15, 0, ip, c7, c10, 4 @ drain WB 271 mov pc, lr 272 273/* 274 * dma_clean_range(start, end) 275 * 276 * Clean the specified virtual address range. 277 * 278 * - start - virtual start address 279 * - end - virtual end address 280 * 281 * (same as v4wb) 282 */ 283arm1020e_dma_clean_range: 284 mov ip, #0 285#ifndef CONFIG_CPU_DCACHE_DISABLE 286 bic r0, r0, #CACHE_DLINESIZE - 1 2871: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 288 add r0, r0, #CACHE_DLINESIZE 289 cmp r0, r1 290 blo 1b 291#endif 292 mcr p15, 0, ip, c7, c10, 4 @ drain WB 293 mov pc, lr 294 295/* 296 * dma_flush_range(start, end) 297 * 298 * Clean and invalidate the specified virtual address range. 299 * 300 * - start - virtual start address 301 * - end - virtual end address 302 */ 303ENTRY(arm1020e_dma_flush_range) 304 mov ip, #0 305#ifndef CONFIG_CPU_DCACHE_DISABLE 306 bic r0, r0, #CACHE_DLINESIZE - 1 3071: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 308 add r0, r0, #CACHE_DLINESIZE 309 cmp r0, r1 310 blo 1b 311#endif 312 mcr p15, 0, ip, c7, c10, 4 @ drain WB 313 mov pc, lr 314 315/* 316 * dma_map_area(start, size, dir) 317 * - start - kernel virtual start address 318 * - size - size of region 319 * - dir - DMA direction 320 */ 321ENTRY(arm1020e_dma_map_area) 322 add r1, r1, r0 323 cmp r2, #DMA_TO_DEVICE 324 beq arm1020e_dma_clean_range 325 bcs arm1020e_dma_inv_range 326 b arm1020e_dma_flush_range 327ENDPROC(arm1020e_dma_map_area) 328 329/* 330 * dma_unmap_area(start, size, dir) 331 * - start - kernel virtual start address 332 * - size - size of region 333 * - dir - DMA direction 334 */ 335ENTRY(arm1020e_dma_unmap_area) 336 mov pc, lr 337ENDPROC(arm1020e_dma_unmap_area) 338 339ENTRY(arm1020e_cache_fns) 340 .long arm1020e_flush_kern_cache_all 341 .long arm1020e_flush_user_cache_all 342 .long arm1020e_flush_user_cache_range 343 .long arm1020e_coherent_kern_range 344 .long arm1020e_coherent_user_range 345 .long arm1020e_flush_kern_dcache_area 346 .long arm1020e_dma_map_area 347 .long arm1020e_dma_unmap_area 348 .long arm1020e_dma_flush_range 349 350 .align 5 351ENTRY(cpu_arm1020e_dcache_clean_area) 352#ifndef CONFIG_CPU_DCACHE_DISABLE 353 mov ip, #0 3541: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 355 add r0, r0, #CACHE_DLINESIZE 356 subs r1, r1, #CACHE_DLINESIZE 357 bhi 1b 358#endif 359 mov pc, lr 360 361/* =============================== PageTable ============================== */ 362 363/* 364 * cpu_arm1020e_switch_mm(pgd) 365 * 366 * Set the translation base pointer to be as described by pgd. 367 * 368 * pgd: new page tables 369 */ 370 .align 5 371ENTRY(cpu_arm1020e_switch_mm) 372#ifdef CONFIG_MMU 373#ifndef CONFIG_CPU_DCACHE_DISABLE 374 mcr p15, 0, r3, c7, c10, 4 375 mov r1, #0xF @ 16 segments 3761: mov r3, #0x3F @ 64 entries 3772: mov ip, r3, LSL #26 @ shift up entry 378 orr ip, ip, r1, LSL #5 @ shift in/up index 379 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry 380 mov ip, #0 381 subs r3, r3, #1 382 cmp r3, #0 383 bge 2b @ entries 3F to 0 384 subs r1, r1, #1 385 cmp r1, #0 386 bge 1b @ segments 15 to 0 387 388#endif 389 mov r1, #0 390#ifndef CONFIG_CPU_ICACHE_DISABLE 391 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 392#endif 393 mcr p15, 0, r1, c7, c10, 4 @ drain WB 394 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 395 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 396#endif 397 mov pc, lr 398 399/* 400 * cpu_arm1020e_set_pte(ptep, pte) 401 * 402 * Set a PTE and flush it out 403 */ 404 .align 5 405ENTRY(cpu_arm1020e_set_pte_ext) 406#ifdef CONFIG_MMU 407 armv3_set_pte_ext 408 mov r0, r0 409#ifndef CONFIG_CPU_DCACHE_DISABLE 410 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 411#endif 412#endif /* CONFIG_MMU */ 413 mov pc, lr 414 415 __INIT 416 417 .type __arm1020e_setup, #function 418__arm1020e_setup: 419 mov r0, #0 420 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 421 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 422#ifdef CONFIG_MMU 423 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 424#endif 425 adr r5, arm1020e_crval 426 ldmia r5, {r5, r6} 427 mrc p15, 0, r0, c1, c0 @ get control register v4 428 bic r0, r0, r5 429 orr r0, r0, r6 430#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 431 orr r0, r0, #0x4000 @ .R.. .... .... .... 432#endif 433 mov pc, lr 434 .size __arm1020e_setup, . - __arm1020e_setup 435 436 /* 437 * R 438 * .RVI ZFRS BLDP WCAM 439 * .011 1001 ..11 0101 440 */ 441 .type arm1020e_crval, #object 442arm1020e_crval: 443 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930 444 445 __INITDATA 446 447/* 448 * Purpose : Function pointers used to access above functions - all calls 449 * come through these 450 */ 451 .type arm1020e_processor_functions, #object 452arm1020e_processor_functions: 453 .word v4t_early_abort 454 .word legacy_pabort 455 .word cpu_arm1020e_proc_init 456 .word cpu_arm1020e_proc_fin 457 .word cpu_arm1020e_reset 458 .word cpu_arm1020e_do_idle 459 .word cpu_arm1020e_dcache_clean_area 460 .word cpu_arm1020e_switch_mm 461 .word cpu_arm1020e_set_pte_ext 462 .size arm1020e_processor_functions, . - arm1020e_processor_functions 463 464 .section ".rodata" 465 466 .type cpu_arch_name, #object 467cpu_arch_name: 468 .asciz "armv5te" 469 .size cpu_arch_name, . - cpu_arch_name 470 471 .type cpu_elf_name, #object 472cpu_elf_name: 473 .asciz "v5" 474 .size cpu_elf_name, . - cpu_elf_name 475 476 .type cpu_arm1020e_name, #object 477cpu_arm1020e_name: 478 .asciz "ARM1020E" 479 .size cpu_arm1020e_name, . - cpu_arm1020e_name 480 481 .align 482 483 .section ".proc.info.init", #alloc, #execinstr 484 485 .type __arm1020e_proc_info,#object 486__arm1020e_proc_info: 487 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE) 488 .long 0xff0ffff0 489 .long PMD_TYPE_SECT | \ 490 PMD_BIT4 | \ 491 PMD_SECT_AP_WRITE | \ 492 PMD_SECT_AP_READ 493 .long PMD_TYPE_SECT | \ 494 PMD_BIT4 | \ 495 PMD_SECT_AP_WRITE | \ 496 PMD_SECT_AP_READ 497 b __arm1020e_setup 498 .long cpu_arch_name 499 .long cpu_elf_name 500 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP 501 .long cpu_arm1020e_name 502 .long arm1020e_processor_functions 503 .long v4wbi_tlb_fns 504 .long v4wb_user_fns 505 .long arm1020e_cache_fns 506 .size __arm1020e_proc_info, . - __arm1020e_proc_info 507