1/* linux/arch/arm/mach-s3c24a0/include/mach/map.h 2 * 3 * Copyright 2003-2007 Simtec Electronics 4 * http://armlinux.simtec.co.uk/ 5 * Ben Dooks <ben@simtec.co.uk> 6 * 7 * S3C24A0 - Memory map definitions 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12*/ 13 14#ifndef __ASM_ARCH_24A0_MAP_H 15#define __ASM_ARCH_24A0_MAP_H __FILE__ 16 17#include <plat/map-base.h> 18#include <plat/map.h> 19 20#define S3C24A0_PA_IO_BASE (0x40000000) 21#define S3C24A0_PA_CLKPWR (0x40000000) 22#define S3C24A0_PA_IRQ (0x40200000) 23#define S3C24A0_PA_DMA (0x40400000) 24#define S3C24A0_PA_MEMCTRL (0x40C00000) 25#define S3C24A0_PA_NAND (0x40C00000) 26#define S3C24A0_PA_SROM (0x40C20000) 27#define S3C24A0_PA_SDRAM (0x40C40000) 28#define S3C24A0_PA_BUSM (0x40CE0000) 29#define S3C24A0_PA_USBHOST (0x41000000) 30#define S3C24A0_PA_MODEMIF (0x41180000) 31#define S3C24A0_PA_IRDA (0x41800000) 32#define S3C24A0_PA_TIMER (0x44000000) 33#define S3C24A0_PA_WATCHDOG (0x44100000) 34#define S3C24A0_PA_RTC (0x44200000) 35#define S3C24A0_PA_UART (0x44400000) 36#define S3C24A0_PA_UART0 (S3C24A0_PA_UART) 37#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000) 38#define S3C24A0_PA_SPI (0x44500000) 39#define S3C24A0_PA_IIC (0x44600000) 40#define S3C24A0_PA_IIS (0x44700000) 41#define S3C24A0_PA_GPIO (0x44800000) 42#define S3C24A0_PA_KEYIF (0x44900000) 43#define S3C24A0_PA_USBDEV (0x44A00000) 44#define S3C24A0_PA_AC97 (0x45000000) 45#define S3C24A0_PA_ADC (0x45800000) 46#define S3C24A0_PA_SDI (0x46000000) 47#define S3C24A0_PA_MS (0x46100000) 48#define S3C24A0_PA_LCD (0x4A000000) 49#define S3C24A0_PA_VPOST (0x4A100000) 50 51/* physical addresses of all the chip-select areas */ 52 53#define S3C24A0_CS0 (0x00000000) 54#define S3C24A0_CS1 (0x04000000) 55#define S3C24A0_CS2 (0x08000000) 56#define S3C24A0_CS3 (0x0C000000) 57#define S3C24A0_CS4 (0x10000000) 58#define S3C24A0_CS5 (0x40000000) 59 60#define S3C24A0_SDRAM_PA (S3C24A0_CS4) 61 62/* Use a single interface for common resources between S3C24XX cpus */ 63 64#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ 65#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL 66#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST 67#define S3C24XX_PA_DMA S3C24A0_PA_DMA 68#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR 69#define S3C24XX_PA_LCD S3C24A0_PA_LCD 70#define S3C24XX_PA_UART S3C24A0_PA_UART 71#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER 72#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV 73#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG 74#define S3C24XX_PA_IIS S3C24A0_PA_IIS 75#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO 76#define S3C24XX_PA_RTC S3C24A0_PA_RTC 77#define S3C24XX_PA_ADC S3C24A0_PA_ADC 78#define S3C24XX_PA_SPI S3C24A0_PA_SPI 79#define S3C24XX_PA_SDI S3C24A0_PA_SDI 80#define S3C24XX_PA_NAND S3C24A0_PA_NAND 81 82#define S3C_PA_UART S3C24A0_PA_UART 83#define S3C_PA_IIC S3C24A0_PA_IIC 84#define S3C_PA_NAND S3C24XX_PA_NAND 85 86#endif /* __ASM_ARCH_24A0_MAP_H */ 87