1/* 2 * arch/arm/mach-orion5x/irq.c 3 * 4 * Core IRQ functions for Marvell Orion System On Chip 5 * 6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/init.h> 15#include <linux/irq.h> 16#include <linux/io.h> 17#include <asm/gpio.h> 18#include <mach/bridge-regs.h> 19#include <plat/irq.h> 20#include "common.h" 21 22static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 23{ 24 BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); 25 26 orion_gpio_irq_handler((irq - IRQ_ORION5X_GPIO_0_7) << 3); 27} 28 29void __init orion5x_init_irq(void) 30{ 31 int i; 32 33 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); 34 35 /* 36 * Mask and clear GPIO IRQ interrupts 37 */ 38 writel(0x0, GPIO_LEVEL_MASK(0)); 39 writel(0x0, GPIO_EDGE_MASK(0)); 40 writel(0x0, GPIO_EDGE_CAUSE(0)); 41 42 /* 43 * Register chained level handlers for GPIO IRQs by default. 44 * User can use set_type() if he wants to use edge types handlers. 45 */ 46 for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { 47 set_irq_chip(i, &orion_gpio_irq_chip); 48 set_irq_handler(i, handle_level_irq); 49 irq_desc[i].status |= IRQ_LEVEL; 50 set_irq_flags(i, IRQF_VALID); 51 } 52 set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); 53 set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); 54 set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); 55 set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); 56} 57