1 2 3#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H 4#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H 5 6/** 7 * struct prcm_config - define clock rates on a per-OPP basis (24xx) 8 * 9 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 10 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP 11 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM 12 * 13 * This is deprecated. As soon as we have a decent OPP API, we should 14 * move all this stuff to it. 15 */ 16struct prcm_config { 17 unsigned long xtal_speed; /* crystal rate */ 18 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ 19 unsigned long mpu_speed; /* speed of MPU */ 20 unsigned long cm_clksel_mpu; /* mpu divider */ 21 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ 22 unsigned long cm_clksel_gfx; /* gfx dividers */ 23 unsigned long cm_clksel1_core; /* major subsystem dividers */ 24 unsigned long cm_clksel1_pll; /* m,n */ 25 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ 26 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ 27 unsigned long base_sdrc_rfr; /* base refresh timing for a set */ 28 unsigned char flags; 29}; 30 31 32/* Core fields for cm_clksel, not ratio governed */ 33#define RX_CLKSEL_DSS1 (0x10 << 8) 34#define RX_CLKSEL_DSS2 (0x0 << 13) 35#define RX_CLKSEL_SSI (0x5 << 20) 36 37/*------------------------------------------------------------------------- 38 * Voltage/DPLL ratios 39 *-------------------------------------------------------------------------*/ 40 41/* 2430 Ratio's, 2430-Ratio Config 1 */ 42#define R1_CLKSEL_L3 (4 << 0) 43#define R1_CLKSEL_L4 (2 << 5) 44#define R1_CLKSEL_USB (4 << 25) 45#define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \ 46 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 47 R1_CLKSEL_L4 | R1_CLKSEL_L3) 48#define R1_CLKSEL_MPU (2 << 0) 49#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU 50#define R1_CLKSEL_DSP (2 << 0) 51#define R1_CLKSEL_DSP_IF (2 << 5) 52#define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF) 53#define R1_CLKSEL_GFX (2 << 0) 54#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX 55#define R1_CLKSEL_MDM (4 << 0) 56#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM 57 58/* 2430-Ratio Config 2 */ 59#define R2_CLKSEL_L3 (6 << 0) 60#define R2_CLKSEL_L4 (2 << 5) 61#define R2_CLKSEL_USB (2 << 25) 62#define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \ 63 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 64 R2_CLKSEL_L4 | R2_CLKSEL_L3) 65#define R2_CLKSEL_MPU (2 << 0) 66#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU 67#define R2_CLKSEL_DSP (2 << 0) 68#define R2_CLKSEL_DSP_IF (3 << 5) 69#define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF) 70#define R2_CLKSEL_GFX (2 << 0) 71#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX 72#define R2_CLKSEL_MDM (6 << 0) 73#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM 74 75/* 2430-Ratio Bootm (BYPASS) */ 76#define RB_CLKSEL_L3 (1 << 0) 77#define RB_CLKSEL_L4 (1 << 5) 78#define RB_CLKSEL_USB (1 << 25) 79#define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \ 80 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 81 RB_CLKSEL_L4 | RB_CLKSEL_L3) 82#define RB_CLKSEL_MPU (1 << 0) 83#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU 84#define RB_CLKSEL_DSP (1 << 0) 85#define RB_CLKSEL_DSP_IF (1 << 5) 86#define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF) 87#define RB_CLKSEL_GFX (1 << 0) 88#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX 89#define RB_CLKSEL_MDM (1 << 0) 90#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM 91 92/* 2420 Ratio Equivalents */ 93#define RXX_CLKSEL_VLYNQ (0x12 << 15) 94#define RXX_CLKSEL_SSI (0x8 << 20) 95 96/* 2420-PRCM III 532MHz core */ 97#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ 98#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ 99#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ 100#define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ 101 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ 102 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ 103 RIII_CLKSEL_L3) 104#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ 105#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU 106#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ 107#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ 108#define RIII_SYNC_DSP (1 << 7) /* Enable sync */ 109#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ 110#define RIII_SYNC_IVA (1 << 13) /* Enable sync */ 111#define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ 112 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ 113 RIII_CLKSEL_DSP) 114#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ 115#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX 116 117/* 2420-PRCM II 600MHz core */ 118#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ 119#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ 120#define RII_CLKSEL_USB (2 << 25) /* 50MHz */ 121#define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \ 122 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ 123 RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \ 124 RII_CLKSEL_L3) 125#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ 126#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU 127#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ 128#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ 129#define RII_SYNC_DSP (0 << 7) /* Bypass sync */ 130#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ 131#define RII_SYNC_IVA (0 << 13) /* Bypass sync */ 132#define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \ 133 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ 134 RII_CLKSEL_DSP) 135#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ 136#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX 137 138/* 2420-PRCM I 660MHz core */ 139#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ 140#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ 141#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ 142#define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \ 143 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ 144 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 145 RI_CLKSEL_L4 | RI_CLKSEL_L3) 146#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ 147#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU 148#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ 149#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ 150#define RI_SYNC_DSP (1 << 7) /* Activate sync */ 151#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ 152#define RI_SYNC_IVA (0 << 13) /* Bypass sync */ 153#define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \ 154 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ 155 RI_CLKSEL_DSP) 156#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ 157#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX 158 159/* 2420-PRCM VII (boot) */ 160#define RVII_CLKSEL_L3 (1 << 0) 161#define RVII_CLKSEL_L4 (1 << 5) 162#define RVII_CLKSEL_DSS1 (1 << 8) 163#define RVII_CLKSEL_DSS2 (0 << 13) 164#define RVII_CLKSEL_VLYNQ (1 << 15) 165#define RVII_CLKSEL_SSI (1 << 20) 166#define RVII_CLKSEL_USB (1 << 25) 167 168#define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ 169 RVII_CLKSEL_VLYNQ | \ 170 RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \ 171 RVII_CLKSEL_L4 | RVII_CLKSEL_L3) 172 173#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ 174#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU 175 176#define RVII_CLKSEL_DSP (1 << 0) 177#define RVII_CLKSEL_DSP_IF (1 << 5) 178#define RVII_SYNC_DSP (0 << 7) 179#define RVII_CLKSEL_IVA (1 << 8) 180#define RVII_SYNC_IVA (0 << 13) 181#define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \ 182 RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \ 183 RVII_CLKSEL_DSP) 184 185#define RVII_CLKSEL_GFX (1 << 0) 186#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX 187 188/*------------------------------------------------------------------------- 189 * 2430 Target modes: Along with each configuration the CPU has several 190 * modes which goes along with them. Modes mainly are the addition of 191 * describe DPLL combinations to go along with a ratio. 192 *-------------------------------------------------------------------------*/ 193 194/* Hardware governed */ 195#define MX_48M_SRC (0 << 3) 196#define MX_54M_SRC (0 << 5) 197#define MX_APLLS_CLIKIN_12 (3 << 23) 198#define MX_APLLS_CLIKIN_13 (2 << 23) 199#define MX_APLLS_CLIKIN_19_2 (0 << 23) 200 201/* 202 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed 203 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz 204 */ 205#define M5A_DPLL_MULT_12 (133 << 12) 206#define M5A_DPLL_DIV_12 (5 << 8) 207#define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 208 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ 209 MX_APLLS_CLIKIN_12) 210#define M5A_DPLL_MULT_13 (61 << 12) 211#define M5A_DPLL_DIV_13 (2 << 8) 212#define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 213 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ 214 MX_APLLS_CLIKIN_13) 215#define M5A_DPLL_MULT_19 (55 << 12) 216#define M5A_DPLL_DIV_19 (3 << 8) 217#define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 218 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ 219 MX_APLLS_CLIKIN_19_2) 220/* #5b (ratio1) target DPLL = 200*2 = 400MHz */ 221#define M5B_DPLL_MULT_12 (50 << 12) 222#define M5B_DPLL_DIV_12 (2 << 8) 223#define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 224 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ 225 MX_APLLS_CLIKIN_12) 226#define M5B_DPLL_MULT_13 (200 << 12) 227#define M5B_DPLL_DIV_13 (12 << 8) 228 229#define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 230 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ 231 MX_APLLS_CLIKIN_13) 232#define M5B_DPLL_MULT_19 (125 << 12) 233#define M5B_DPLL_DIV_19 (31 << 8) 234#define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 235 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ 236 MX_APLLS_CLIKIN_19_2) 237/* 238 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz 239 */ 240#define M4_DPLL_MULT_12 (133 << 12) 241#define M4_DPLL_DIV_12 (3 << 8) 242#define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 243 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ 244 MX_APLLS_CLIKIN_12) 245 246#define M4_DPLL_MULT_13 (399 << 12) 247#define M4_DPLL_DIV_13 (12 << 8) 248#define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 249 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ 250 MX_APLLS_CLIKIN_13) 251 252#define M4_DPLL_MULT_19 (145 << 12) 253#define M4_DPLL_DIV_19 (6 << 8) 254#define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 255 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ 256 MX_APLLS_CLIKIN_19_2) 257 258/* 259 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz 260 */ 261#define M3_DPLL_MULT_12 (55 << 12) 262#define M3_DPLL_DIV_12 (1 << 8) 263#define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 264 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ 265 MX_APLLS_CLIKIN_12) 266#define M3_DPLL_MULT_13 (76 << 12) 267#define M3_DPLL_DIV_13 (2 << 8) 268#define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 269 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ 270 MX_APLLS_CLIKIN_13) 271#define M3_DPLL_MULT_19 (17 << 12) 272#define M3_DPLL_DIV_19 (0 << 8) 273#define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 274 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ 275 MX_APLLS_CLIKIN_19_2) 276 277/* 278 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz 279 */ 280#define M2_DPLL_MULT_12 (55 << 12) 281#define M2_DPLL_DIV_12 (1 << 8) 282#define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 283 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ 284 MX_APLLS_CLIKIN_12) 285 286/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, 287 * relock time issue */ 288/* Core frequency changed from 330/165 to 329/164 MHz*/ 289#define M2_DPLL_MULT_13 (76 << 12) 290#define M2_DPLL_DIV_13 (2 << 8) 291#define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 292 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ 293 MX_APLLS_CLIKIN_13) 294 295#define M2_DPLL_MULT_19 (17 << 12) 296#define M2_DPLL_DIV_19 (0 << 8) 297#define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 298 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ 299 MX_APLLS_CLIKIN_19_2) 300 301/* boot (boot) */ 302#define MB_DPLL_MULT (1 << 12) 303#define MB_DPLL_DIV (0 << 8) 304#define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 305 MB_DPLL_DIV | MB_DPLL_MULT | \ 306 MX_APLLS_CLIKIN_12) 307 308#define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 309 MB_DPLL_DIV | MB_DPLL_MULT | \ 310 MX_APLLS_CLIKIN_13) 311 312#define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 313 MB_DPLL_DIV | MB_DPLL_MULT | \ 314 MX_APLLS_CLIKIN_19) 315 316/* 317 * 2430 - chassis (sedna) 318 * 165 (ratio1) same as above #2 319 * 150 (ratio1) 320 * 133 (ratio2) same as above #4 321 * 110 (ratio2) same as above #3 322 * 104 (ratio2) 323 * boot (boot) 324 */ 325 326/* PRCM I target DPLL = 2*330MHz = 660MHz */ 327#define MI_DPLL_MULT_12 (55 << 12) 328#define MI_DPLL_DIV_12 (1 << 8) 329#define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 330 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ 331 MX_APLLS_CLIKIN_12) 332 333/* 334 * 2420 Equivalent - mode registers 335 * PRCM II , target DPLL = 2*300MHz = 600MHz 336 */ 337#define MII_DPLL_MULT_12 (50 << 12) 338#define MII_DPLL_DIV_12 (1 << 8) 339#define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 340 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ 341 MX_APLLS_CLIKIN_12) 342#define MII_DPLL_MULT_13 (300 << 12) 343#define MII_DPLL_DIV_13 (12 << 8) 344#define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 345 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ 346 MX_APLLS_CLIKIN_13) 347 348/* PRCM III target DPLL = 2*266 = 532MHz*/ 349#define MIII_DPLL_MULT_12 (133 << 12) 350#define MIII_DPLL_DIV_12 (5 << 8) 351#define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 352 MIII_DPLL_DIV_12 | \ 353 MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12) 354#define MIII_DPLL_MULT_13 (266 << 12) 355#define MIII_DPLL_DIV_13 (12 << 8) 356#define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 357 MIII_DPLL_DIV_13 | \ 358 MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13) 359 360/* PRCM VII (boot bypass) */ 361#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL 362#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL 363 364/* High and low operation value */ 365#define MX_CLKSEL2_PLL_2x_VAL (2 << 0) 366#define MX_CLKSEL2_PLL_1x_VAL (1 << 0) 367 368/* MPU speed defines */ 369#define S12M 12000000 370#define S13M 13000000 371#define S19M 19200000 372#define S26M 26000000 373#define S100M 100000000 374#define S133M 133000000 375#define S150M 150000000 376#define S164M 164000000 377#define S165M 165000000 378#define S199M 199000000 379#define S200M 200000000 380#define S266M 266000000 381#define S300M 300000000 382#define S329M 329000000 383#define S330M 330000000 384#define S399M 399000000 385#define S400M 400000000 386#define S532M 532000000 387#define S600M 600000000 388#define S658M 658000000 389#define S660M 660000000 390#define S798M 798000000 391 392 393extern const struct prcm_config omap2420_rate_table[]; 394 395#ifdef CONFIG_ARCH_OMAP2430 396extern const struct prcm_config omap2430_rate_table[]; 397#else 398#define omap2430_rate_table NULL 399#endif 400extern const struct prcm_config *rate_table; 401extern const struct prcm_config *curr_prcm_set; 402 403#endif 404