1/* 2 * linux/arch/arm/mach-omap2/clock.h 3 * 4 * Copyright (C) 2005-2009 Texas Instruments, Inc. 5 * Copyright (C) 2004-2009 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H 17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H 18 19#include <plat/clock.h> 20 21/* The maximum error between a target DPLL rate and the rounded rate in Hz */ 22#define DEFAULT_DPLL_RATE_TOLERANCE 50000 23 24/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 25#define CORE_CLK_SRC_32K 0x0 26#define CORE_CLK_SRC_DPLL 0x1 27#define CORE_CLK_SRC_DPLL_X2 0x2 28 29/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ 30#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 31#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 32#define OMAP2XXX_EN_DPLL_LOCKED 0x3 33 34/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ 35#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 36#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 37#define OMAP3XXX_EN_DPLL_LOCKED 0x7 38 39/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ 40#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 41#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 42#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 43#define OMAP4XXX_EN_DPLL_LOCKED 0x7 44 45/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ 46#define DPLL_LOW_POWER_STOP 0x1 47#define DPLL_LOW_POWER_BYPASS 0x5 48#define DPLL_LOCKED 0x7 49 50/* DPLL Type and DCO Selection Flags */ 51#define DPLL_J_TYPE 0x1 52#define DPLL_NO_DCO_SEL 0x2 53 54int omap2_clk_enable(struct clk *clk); 55void omap2_clk_disable(struct clk *clk); 56long omap2_clk_round_rate(struct clk *clk, unsigned long rate); 57int omap2_clk_set_rate(struct clk *clk, unsigned long rate); 58int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); 59int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); 60long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); 61unsigned long omap3_dpll_recalc(struct clk *clk); 62unsigned long omap3_clkoutx2_recalc(struct clk *clk); 63void omap3_dpll_allow_idle(struct clk *clk); 64void omap3_dpll_deny_idle(struct clk *clk); 65u32 omap3_dpll_autoidle_read(struct clk *clk); 66int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); 67int omap3_noncore_dpll_enable(struct clk *clk); 68void omap3_noncore_dpll_disable(struct clk *clk); 69 70#ifdef CONFIG_OMAP_RESET_CLOCKS 71void omap2_clk_disable_unused(struct clk *clk); 72#else 73#define omap2_clk_disable_unused NULL 74#endif 75 76void omap2_init_clk_clkdm(struct clk *clk); 77 78/* clkt_clksel.c public functions */ 79u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 80 u32 *new_div); 81void omap2_init_clksel_parent(struct clk *clk); 82unsigned long omap2_clksel_recalc(struct clk *clk); 83long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); 84int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); 85int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); 86 87u32 omap2_get_dpll_rate(struct clk *clk); 88void omap2_init_dpll_parent(struct clk *clk); 89 90int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); 91 92 93#ifdef CONFIG_ARCH_OMAP2 94void omap2xxx_clk_prepare_for_reboot(void); 95#else 96static inline void omap2xxx_clk_prepare_for_reboot(void) 97{ 98} 99#endif 100 101#ifdef CONFIG_ARCH_OMAP3 102void omap3_clk_prepare_for_reboot(void); 103#else 104static inline void omap3_clk_prepare_for_reboot(void) 105{ 106} 107#endif 108 109#ifdef CONFIG_ARCH_OMAP4 110void omap4_clk_prepare_for_reboot(void); 111#else 112static inline void omap4_clk_prepare_for_reboot(void) 113{ 114} 115#endif 116 117int omap2_dflt_clk_enable(struct clk *clk); 118void omap2_dflt_clk_disable(struct clk *clk); 119void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, 120 u8 *other_bit); 121void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 122 u8 *idlest_bit, u8 *idlest_val); 123int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); 124void omap2_clk_print_new_rates(const char *hfclkin_ck_name, 125 const char *core_ck_name, 126 const char *mpu_ck_name); 127 128extern u8 cpu_mask; 129 130extern const struct clkops clkops_omap2_dflt_wait; 131extern const struct clkops clkops_dummy; 132extern const struct clkops clkops_omap2_dflt; 133 134extern struct clk_functions omap2_clk_functions; 135extern struct clk *vclk, *sclk; 136 137extern const struct clksel_rate gpt_32k_rates[]; 138extern const struct clksel_rate gpt_sys_rates[]; 139extern const struct clksel_rate gfx_l3_rates[]; 140 141#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ) 142extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table); 143extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); 144#else 145#define omap2_clk_init_cpufreq_table 0 146#define omap2_clk_exit_cpufreq_table 0 147#endif 148 149extern const struct clkops clkops_omap3_noncore_dpll_ops; 150 151#endif 152