1/* 2 * Copyright (C) 2009 by Sascha Hauer, Pengutronix 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 16 * MA 02110-1301, USA. 17 */ 18 19#include <linux/kernel.h> 20#include <linux/init.h> 21#include <linux/list.h> 22#include <linux/clk.h> 23#include <linux/io.h> 24 25#include <asm/clkdev.h> 26 27#include <mach/clock.h> 28#include <mach/hardware.h> 29#include <mach/common.h> 30#include <mach/mx25.h> 31 32#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR) 33 34#define CCM_MPCTL 0x00 35#define CCM_UPCTL 0x04 36#define CCM_CCTL 0x08 37#define CCM_CGCR0 0x0C 38#define CCM_CGCR1 0x10 39#define CCM_CGCR2 0x14 40#define CCM_PCDR0 0x18 41#define CCM_PCDR1 0x1C 42#define CCM_PCDR2 0x20 43#define CCM_PCDR3 0x24 44#define CCM_RCSR 0x28 45#define CCM_CRDR 0x2C 46#define CCM_DCVR0 0x30 47#define CCM_DCVR1 0x34 48#define CCM_DCVR2 0x38 49#define CCM_DCVR3 0x3c 50#define CCM_LTR0 0x40 51#define CCM_LTR1 0x44 52#define CCM_LTR2 0x48 53#define CCM_LTR3 0x4c 54 55static unsigned long get_rate_mpll(void) 56{ 57 ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL); 58 59 return mxc_decode_pll(mpctl, 24000000); 60} 61 62static unsigned long get_rate_upll(void) 63{ 64 ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL); 65 66 return mxc_decode_pll(mpctl, 24000000); 67} 68 69unsigned long get_rate_arm(struct clk *clk) 70{ 71 unsigned long cctl = readl(CRM_BASE + CCM_CCTL); 72 unsigned long rate = get_rate_mpll(); 73 74 if (cctl & (1 << 14)) 75 rate = (rate * 3) >> 1; 76 77 return rate / ((cctl >> 30) + 1); 78} 79 80static unsigned long get_rate_ahb(struct clk *clk) 81{ 82 unsigned long cctl = readl(CRM_BASE + CCM_CCTL); 83 84 return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1); 85} 86 87static unsigned long get_rate_ipg(struct clk *clk) 88{ 89 return get_rate_ahb(NULL) >> 1; 90} 91 92static unsigned long get_rate_per(int per) 93{ 94 unsigned long ofs = (per & 0x3) * 8; 95 unsigned long reg = per & ~0x3; 96 unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f; 97 unsigned long fref; 98 99 if (readl(CRM_BASE + 0x64) & (1 << per)) 100 fref = get_rate_upll(); 101 else 102 fref = get_rate_ipg(NULL); 103 104 return fref / (val + 1); 105} 106 107static unsigned long get_rate_uart(struct clk *clk) 108{ 109 return get_rate_per(15); 110} 111 112static unsigned long get_rate_ssi2(struct clk *clk) 113{ 114 return get_rate_per(14); 115} 116 117static unsigned long get_rate_ssi1(struct clk *clk) 118{ 119 return get_rate_per(13); 120} 121 122static unsigned long get_rate_i2c(struct clk *clk) 123{ 124 return get_rate_per(6); 125} 126 127static unsigned long get_rate_nfc(struct clk *clk) 128{ 129 return get_rate_per(8); 130} 131 132static unsigned long get_rate_gpt(struct clk *clk) 133{ 134 return get_rate_per(5); 135} 136 137static unsigned long get_rate_lcdc(struct clk *clk) 138{ 139 return get_rate_per(7); 140} 141 142static unsigned long get_rate_csi(struct clk *clk) 143{ 144 return get_rate_per(0); 145} 146 147static unsigned long get_rate_otg(struct clk *clk) 148{ 149 unsigned long cctl = readl(CRM_BASE + CCM_CCTL); 150 unsigned long rate = get_rate_upll(); 151 152 return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1); 153} 154 155static int clk_cgcr_enable(struct clk *clk) 156{ 157 u32 reg; 158 159 reg = __raw_readl(clk->enable_reg); 160 reg |= 1 << clk->enable_shift; 161 __raw_writel(reg, clk->enable_reg); 162 163 return 0; 164} 165 166static void clk_cgcr_disable(struct clk *clk) 167{ 168 u32 reg; 169 170 reg = __raw_readl(clk->enable_reg); 171 reg &= ~(1 << clk->enable_shift); 172 __raw_writel(reg, clk->enable_reg); 173} 174 175#define DEFINE_CLOCK(name, i, er, es, gr, sr, s) \ 176 static struct clk name = { \ 177 .id = i, \ 178 .enable_reg = CRM_BASE + er, \ 179 .enable_shift = es, \ 180 .get_rate = gr, \ 181 .set_rate = sr, \ 182 .enable = clk_cgcr_enable, \ 183 .disable = clk_cgcr_disable, \ 184 .secondary = s, \ 185 } 186 187/* 188 * Note: the following IPG clock gating bits are wrongly marked "Reserved" in 189 * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is 190 * taken from the Freescale released BSP. 191 * 192 * bit reg offset clock 193 * 194 * 0 CGCR1 0 AUDMUX 195 * 12 CGCR1 12 ESAI 196 * 16 CGCR1 16 GPIO1 197 * 17 CGCR1 17 GPIO2 198 * 18 CGCR1 18 GPIO3 199 * 23 CGCR1 23 I2C1 200 * 24 CGCR1 24 I2C2 201 * 25 CGCR1 25 I2C3 202 * 27 CGCR1 27 IOMUXC 203 * 28 CGCR1 28 KPP 204 * 30 CGCR1 30 OWIRE 205 * 36 CGCR2 4 RTIC 206 * 51 CGCR2 19 WDOG 207 */ 208 209DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL); 210DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL); 211DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL); 212DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL); 213DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); 214DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); 215DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); 216DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); 217DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); 218DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); 219DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL); 220DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk); 221DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); 222DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); 223DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); 224DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk); 225DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk); 226DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL, NULL); 227DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL); 228DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL); 229DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL, NULL); 230DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL, NULL); 231DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL, NULL); 232DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL); 233DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL); 234DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); 235DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); 236DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); 237DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); 238DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); 239DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); 240DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); 241DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); 242DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); 243DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); 244DEFINE_CLOCK(can2_clk, 0, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); 245 246#define _REGISTER_CLOCK(d, n, c) \ 247 { \ 248 .dev_id = d, \ 249 .con_id = n, \ 250 .clk = &c, \ 251 }, 252 253static struct clk_lookup lookups[] = { 254 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) 255 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) 256 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) 257 _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk) 258 _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk) 259 _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk) 260 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk) 261 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) 262 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) 263 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) 264 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) 265 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) 266 _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) 267 _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk) 268 _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk) 269 _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk) 270 _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk) 271 _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk) 272 _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk) 273 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) 274 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) 275 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk) 276 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 277 _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) 278 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 279 _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) 280 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) 281 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) 282 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) 283 _REGISTER_CLOCK(NULL, "audmux", audmux_clk) 284 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) 285 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) 286}; 287 288int __init mx25_clocks_init(void) 289{ 290 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 291 292 /* Turn off all clocks except the ones we need to survive, namely: 293 * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM, 294 * SCC 295 */ 296 __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0); 297 __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); 298 __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); 299#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) 300 clk_enable(&uart1_clk); 301#endif 302 303 /* Clock source for lcdc and csi is upll */ 304 __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0), 305 CRM_BASE + 0x64); 306 307 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); 308 309 return 0; 310} 311