1/* 2 * Copyright (C) 2007 Broadcom 3 * Copyright (C) 1999 ARM Limited 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20#if !defined(ARCH_BCMRING_IRQS_H) 21#define ARCH_BCMRING_IRQS_H 22 23/* INTC0 - interrupt controller 0 */ 24#define IRQ_INTC0_START 0 25#define IRQ_DMA0C0 0 /* DMA0 channel 0 interrupt */ 26#define IRQ_DMA0C1 1 /* DMA0 channel 1 interrupt */ 27#define IRQ_DMA0C2 2 /* DMA0 channel 2 interrupt */ 28#define IRQ_DMA0C3 3 /* DMA0 channel 3 interrupt */ 29#define IRQ_DMA0C4 4 /* DMA0 channel 4 interrupt */ 30#define IRQ_DMA0C5 5 /* DMA0 channel 5 interrupt */ 31#define IRQ_DMA0C6 6 /* DMA0 channel 6 interrupt */ 32#define IRQ_DMA0C7 7 /* DMA0 channel 7 interrupt */ 33#define IRQ_DMA1C0 8 /* DMA1 channel 0 interrupt */ 34#define IRQ_DMA1C1 9 /* DMA1 channel 1 interrupt */ 35#define IRQ_DMA1C2 10 /* DMA1 channel 2 interrupt */ 36#define IRQ_DMA1C3 11 /* DMA1 channel 3 interrupt */ 37#define IRQ_DMA1C4 12 /* DMA1 channel 4 interrupt */ 38#define IRQ_DMA1C5 13 /* DMA1 channel 5 interrupt */ 39#define IRQ_DMA1C6 14 /* DMA1 channel 6 interrupt */ 40#define IRQ_DMA1C7 15 /* DMA1 channel 7 interrupt */ 41#define IRQ_VPM 16 /* Voice process module interrupt */ 42#define IRQ_USBHD2 17 /* USB host2/device2 interrupt */ 43#define IRQ_USBH1 18 /* USB1 host interrupt */ 44#define IRQ_USBD 19 /* USB device interrupt */ 45#define IRQ_SDIOH0 20 /* SDIO0 host interrupt */ 46#define IRQ_SDIOH1 21 /* SDIO1 host interrupt */ 47#define IRQ_TIMER0 22 /* Timer0 interrupt */ 48#define IRQ_TIMER1 23 /* Timer1 interrupt */ 49#define IRQ_TIMER2 24 /* Timer2 interrupt */ 50#define IRQ_TIMER3 25 /* Timer3 interrupt */ 51#define IRQ_SPIH 26 /* SPI host interrupt */ 52#define IRQ_ESW 27 /* Ethernet switch interrupt */ 53#define IRQ_APM 28 /* Audio process module interrupt */ 54#define IRQ_GE 29 /* Graphic engine interrupt */ 55#define IRQ_CLCD 30 /* LCD Controller interrupt */ 56#define IRQ_PIF 31 /* Peripheral interface interrupt */ 57#define IRQ_INTC0_END 31 58 59/* INTC1 - interrupt controller 1 */ 60#define IRQ_INTC1_START 32 61#define IRQ_GPIO0 32 /* 0 GPIO bit 31//0 combined interrupt */ 62#define IRQ_GPIO1 33 /* 1 GPIO bit 64//32 combined interrupt */ 63#define IRQ_I2S0 34 /* 2 I2S0 interrupt */ 64#define IRQ_I2S1 35 /* 3 I2S1 interrupt */ 65#define IRQ_I2CH 36 /* 4 I2C host interrupt */ 66#define IRQ_I2CS 37 /* 5 I2C slave interrupt */ 67#define IRQ_SPIS 38 /* 6 SPI slave interrupt */ 68#define IRQ_GPHY 39 /* 7 Gigabit Phy interrupt */ 69#define IRQ_FLASHC 40 /* 8 Flash controller interrupt */ 70#define IRQ_COMMTX 41 /* 9 ARM DDC transmit interrupt */ 71#define IRQ_COMMRX 42 /* 10 ARM DDC receive interrupt */ 72#define IRQ_PMUIRQ 43 /* 11 ARM performance monitor interrupt */ 73#define IRQ_UARTB 44 /* 12 UARTB */ 74#define IRQ_WATCHDOG 45 /* 13 Watchdog timer interrupt */ 75#define IRQ_UARTA 46 /* 14 UARTA */ 76#define IRQ_TSC 47 /* 15 Touch screen controller interrupt */ 77#define IRQ_KEYC 48 /* 16 Key pad controller interrupt */ 78#define IRQ_DMPU 49 /* 17 DDR2 memory partition interrupt */ 79#define IRQ_VMPU 50 /* 18 VRAM memory partition interrupt */ 80#define IRQ_FMPU 51 /* 19 Flash memory parition unit interrupt */ 81#define IRQ_RNG 52 /* 20 Random number generator interrupt */ 82#define IRQ_RTC0 53 /* 21 Real time clock periodic interrupt */ 83#define IRQ_RTC1 54 /* 22 Real time clock one-shot interrupt */ 84#define IRQ_SPUM 55 /* 23 Secure process module interrupt */ 85#define IRQ_VDEC 56 /* 24 Hantro video decoder interrupt */ 86#define IRQ_RTC2 57 /* 25 Real time clock tamper interrupt */ 87#define IRQ_DDRP 58 /* 26 DDR Panic interrupt */ 88#define IRQ_INTC1_END 58 89 90/* SINTC secure int controller */ 91#define IRQ_SINTC_START 59 92#define IRQ_SEC_WATCHDOG 59 /* 0 Watchdog timer interrupt */ 93#define IRQ_SEC_UARTA 60 /* 1 UARTA interrupt */ 94#define IRQ_SEC_TSC 61 /* 2 Touch screen controller interrupt */ 95#define IRQ_SEC_KEYC 62 /* 3 Key pad controller interrupt */ 96#define IRQ_SEC_DMPU 63 /* 4 DDR2 memory partition interrupt */ 97#define IRQ_SEC_VMPU 64 /* 5 VRAM memory partition interrupt */ 98#define IRQ_SEC_FMPU 65 /* 6 Flash memory parition unit interrupt */ 99#define IRQ_SEC_RNG 66 /* 7 Random number generator interrupt */ 100#define IRQ_SEC_RTC0 67 /* 8 Real time clock periodic interrupt */ 101#define IRQ_SEC_RTC1 68 /* 9 Real time clock one-shot interrupt */ 102#define IRQ_SEC_SPUM 69 /* 10 Secure process module interrupt */ 103#define IRQ_SEC_TIMER0 70 /* 11 Secure timer0 interrupt */ 104#define IRQ_SEC_TIMER1 71 /* 12 Secure timer1 interrupt */ 105#define IRQ_SEC_TIMER2 72 /* 13 Secure timer2 interrupt */ 106#define IRQ_SEC_TIMER3 73 /* 14 Secure timer3 interrupt */ 107#define IRQ_SEC_RTC2 74 /* 15 Real time clock tamper interrupt */ 108 109#define IRQ_SINTC_END 74 110 111/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */ 112/* Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */ 113/* to make the mapping easy for humans to decipher. */ 114 115#define IRQ_GPIO_0 100 116 117#define NUM_INTERNAL_IRQS (IRQ_SINTC_END+1) 118 119/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */ 120/* define NUM_GPIO_IRQS GPIOHW_TOTAL_NUM_PINS */ 121#define NUM_GPIO_IRQS 62 122 123#define NR_IRQS (IRQ_GPIO_0 + NUM_GPIO_IRQS) 124 125#define IRQ_UNKNOWN -1 126 127/* Tune these bits to preclude noisy or unsupported interrupt sources as required. */ 128#define IRQ_INTC0_VALID_MASK 0xffffffff 129#define IRQ_INTC1_VALID_MASK 0x07ffffff 130#define IRQ_SINTC_VALID_MASK 0x0000ffff 131 132#endif /* ARCH_BCMRING_IRQS_H */ 133