1/***************************************************************************** 2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. 3* 4* Unless you and Broadcom execute a separate written software license 5* agreement governing use of this software, this software is licensed to you 6* under the terms of the GNU General Public License version 2, available at 7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). 8* 9* Notwithstanding the above, under no circumstances may you combine this 10* software in any way with any other Broadcom software provided under a 11* license other than the GPL, without Broadcom's express prior written 12* consent. 13*****************************************************************************/ 14 15/****************************************************************************/ 16/** 17* @file chipcHw_reg.h 18* 19* @brief Definitions for low level chip control registers 20* 21*/ 22/****************************************************************************/ 23#ifndef CHIPCHW_REG_H 24#define CHIPCHW_REG_H 25 26#include <mach/csp/mm_io.h> 27#include <csp/reg.h> 28#include <mach/csp/ddrcReg.h> 29 30#define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC 31 32typedef struct { 33 uint32_t ChipId; /* Chip ID */ 34 uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */ 35 uint32_t ARMClock; /* PLL1 Channel 2 for ARM clock */ 36 uint32_t ESWClock; /* PLL1 Channel 3 for ESW system clock */ 37 uint32_t VPMClock; /* PLL1 Channel 4 for VPM clock */ 38 uint32_t ESW125Clock; /* PLL1 Channel 5 for ESW 125MHz clock */ 39 uint32_t UARTClock; /* PLL1 Channel 6 for UART clock */ 40 uint32_t SDIO0Clock; /* PLL1 Channel 7 for SDIO 0 clock */ 41 uint32_t SDIO1Clock; /* PLL1 Channel 8 for SDIO 1 clock */ 42 uint32_t SPIClock; /* PLL1 Channel 9 for SPI master Clock */ 43 uint32_t ETMClock; /* PLL1 Channel 10 for ARM ETM Clock */ 44 45 uint32_t ACLKClock; /* ACLK Clock (Divider) */ 46 uint32_t OTPClock; /* OTP Clock (Divider) */ 47 uint32_t I2CClock; /* I2C Clock (CK_13m) (Divider) */ 48 uint32_t I2S0Clock; /* I2S0 Clock (Divider) */ 49 uint32_t RTBUSClock; /* RTBUS (DDR PHY Config.) Clock (Divider) */ 50 uint32_t pad1; 51 uint32_t APM100Clock; /* APM 100MHz CLK Clock (Divider) */ 52 uint32_t TSCClock; /* TSC Clock (Divider) */ 53 uint32_t LEDClock; /* LED Clock (Divider) */ 54 55 uint32_t USBClock; /* PLL2 Channel 1 for USB clock */ 56 uint32_t LCDClock; /* PLL2 Channel 2 for LCD clock */ 57 uint32_t APMClock; /* PLL2 Channel 3 for APM 200 MHz clock */ 58 59 uint32_t BusIntfClock; /* Bus interface clock */ 60 61 uint32_t PLLStatus; /* PLL status register (PLL1) */ 62 uint32_t PLLConfig; /* PLL configuration register (PLL1) */ 63 uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */ 64 uint32_t PLLDivider; /* PLL divider control register (PLL1) */ 65 uint32_t PLLControl1; /* PLL analog control register #1 (PLL1) */ 66 uint32_t PLLControl2; /* PLL analog control register #2 (PLL1) */ 67 68 uint32_t I2S1Clock; /* I2S1 Clock */ 69 uint32_t AudioEnable; /* Enable/ disable audio channel */ 70 uint32_t SoftReset1; /* Reset blocks */ 71 uint32_t SoftReset2; /* Reset blocks */ 72 uint32_t Spare1; /* Phase align interrupts */ 73 uint32_t Sticky; /* Sticky bits */ 74 uint32_t MiscCtrl; /* Misc. control */ 75 uint32_t pad3[3]; 76 77 uint32_t PLLStatus2; /* PLL status register (PLL2) */ 78 uint32_t PLLConfig2; /* PLL configuration register (PLL2) */ 79 uint32_t PLLPreDivider2; /* PLL pre-divider control register (PLL2) */ 80 uint32_t PLLDivider2; /* PLL divider control register (PLL2) */ 81 uint32_t PLLControl12; /* PLL analog control register #1 (PLL2) */ 82 uint32_t PLLControl22; /* PLL analog control register #2 (PLL2) */ 83 84 uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */ 85 uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */ 86 uint32_t PhaseAlignStatus; /* DDR/VPM Clock Phase Alignment Status */ 87 uint32_t PhaseCtrlStatus; /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */ 88 uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */ 89 uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */ 90 uint32_t pad4[9]; 91 92 uint32_t SoftOTP1; /* Software OTP control */ 93 uint32_t SoftOTP2; /* Software OTP control */ 94 uint32_t SoftStraps; /* Software strap */ 95 uint32_t PinStraps; /* Pin Straps */ 96 uint32_t DiffOscCtrl; /* Diff oscillator control */ 97 uint32_t DiagsCtrl; /* Diagnostic control */ 98 uint32_t DiagsOutputCtrl; /* Diagnostic output enable */ 99 uint32_t DiagsReadBackCtrl; /* Diagnostic read back control */ 100 101 uint32_t LcdPifMode; /* LCD/PIF Pin Sharing MUX Mode */ 102 103 uint32_t GpioMux_0_7; /* Pin Sharing MUX0 Control */ 104 uint32_t GpioMux_8_15; /* Pin Sharing MUX1 Control */ 105 uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */ 106 uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */ 107 uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */ 108 uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */ 109 uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */ 110 uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */ 111 112 uint32_t GpioSR_0_7; /* Slew rate for GPIO 0 - 7 */ 113 uint32_t GpioSR_8_15; /* Slew rate for GPIO 8 - 15 */ 114 uint32_t GpioSR_16_23; /* Slew rate for GPIO 16 - 23 */ 115 uint32_t GpioSR_24_31; /* Slew rate for GPIO 24 - 31 */ 116 uint32_t GpioSR_32_39; /* Slew rate for GPIO 32 - 39 */ 117 uint32_t GpioSR_40_47; /* Slew rate for GPIO 40 - 47 */ 118 uint32_t GpioSR_48_55; /* Slew rate for GPIO 48 - 55 */ 119 uint32_t GpioSR_56_63; /* Slew rate for GPIO 56 - 63 */ 120 uint32_t MiscSR_0_7; /* Slew rate for MISC 0 - 7 */ 121 uint32_t MiscSR_8_15; /* Slew rate for MISC 8 - 15 */ 122 123 uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */ 124 uint32_t GpioPull_16_31; /* Pull up registers for GPIO 16 - 31 */ 125 uint32_t GpioPull_32_47; /* Pull up registers for GPIO 32 - 47 */ 126 uint32_t GpioPull_48_63; /* Pull up registers for GPIO 48 - 63 */ 127 uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */ 128 129 uint32_t GpioInput_0_31; /* Input type for GPIO 0 - 31 */ 130 uint32_t GpioInput_32_63; /* Input type for GPIO 32 - 63 */ 131 uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */ 132} chipcHw_REG_t; 133 134#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) 135#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC) 136 137#define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000 138#define chipcHw_REG_CHIPID_BASE_SHIFT 12 139#define chipcHw_REG_CHIPID_REV_MASK 0x00000FFF 140#define chipcHw_REG_REV_A0 0xA00 141#define chipcHw_REG_REV_B0 0x0B0 142 143#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE 0x80000000 /* Allow controlling PLL registers */ 144#define chipcHw_REG_PLL_STATUS_LOCKED 0x00000001 /* PLL is settled */ 145#define chipcHw_REG_PLL_CONFIG_D_RESET 0x00000008 /* Digital reset */ 146#define chipcHw_REG_PLL_CONFIG_A_RESET 0x00000004 /* Analog reset */ 147#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE 0x00000020 /* Bypass enable */ 148#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE 0x00000010 /* Output enable */ 149#define chipcHw_REG_PLL_CONFIG_POWER_DOWN 0x00000001 /* Power down */ 150#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ 1600000000 /* 1.6GHz VCO split frequency */ 151#define chipcHw_REG_PLL_CONFIG_VCO_800_1600 0x00000000 /* VCO range 800-1600 MHz */ 152#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200 0x00000080 /* VCO range 1601-3200 MHz */ 153#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE 0x00010000 /* PLL test output enable */ 154#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK 0x003E0000 /* Mask to set test values */ 155#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT 17 156 157#define chipcHw_REG_PLL_CLOCK_PHASE_COMP 0x00800000 /* Phase comparator output */ 158#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK 0x00300000 /* Clock to bus ratio mask */ 159#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT 20 /* Number of bits to be shifted */ 160#define chipcHw_REG_PLL_CLOCK_POWER_DOWN 0x00080000 /* PLL channel power down */ 161#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO 0x00040000 /* Use GPIO as source */ 162#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT 0x00020000 /* Select bypass clock */ 163#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE 0x00010000 /* Clock gated ON */ 164#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE 0x00008000 /* Clock phase update enable */ 165#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT 8 /* Number of bits to be shifted */ 166#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK 0x00003F00 /* Phase control mask */ 167#define chipcHw_REG_PLL_CLOCK_MDIV_MASK 0x000000FF /* Clock post divider mask 168 169 00000000 = divide-by-256 170 00000001 = divide-by-1 171 00000010 = divide-by-2 172 00000011 = divide-by-3 173 00000100 = divide-by-4 174 00000101 = divide-by-5 175 00000110 = divide-by-6 176 . 177 . 178 11111011 = divide-by-251 179 11111100 = divide-by-252 180 11111101 = divide-by-253 181 11111110 = divide-by-254 182 */ 183 184#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER 0x00040000 /* NON-PLL clock source select */ 185#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT 0x00020000 /* NON-PLL clock bypass enable */ 186#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE 0x00010000 /* NON-PLL clock output enable */ 187#define chipcHw_REG_DIV_CLOCK_DIV_MASK 0x000000FF /* NON-PLL clock post-divide mask */ 188#define chipcHw_REG_DIV_CLOCK_DIV_256 0x00000000 /* NON-PLL clock post-divide by 256 */ 189 190#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT 0 191#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT 4 192#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT 8 193#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK 0x0001FF00 194#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN 0x02000000 195#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK 0x00700000 /* Divider mask */ 196#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER 0x00000000 /* Integer-N Mode */ 197#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT 0x00100000 /* MASH Sigma-Delta Modulator Unit Mode */ 198#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT 0x00200000 /* MFB Sigma-Delta Modulator Unit Mode */ 199#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 0x00300000 /* MASH Sigma-Delta Modulator 1/8 Mode */ 200#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8 0x00400000 /* MFB Sigma-Delta Modulator 1/8 Mode */ 201 202#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco) ((vco) / chipcHw_XTAL_FREQ_Hz) 203#define chipcHw_REG_PLL_PREDIVIDER_P1 1 204#define chipcHw_REG_PLL_PREDIVIDER_P2 1 205 206#define chipcHw_REG_PLL_DIVIDER_M1DIV 0x03000000 207#define chipcHw_REG_PLL_DIVIDER_FRAC 0x00FFFFFF /* Fractional divider */ 208 209#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS (0x00FFFFFF) /* To attain spread with max frequency */ 210 211#define chipcHw_REG_PLL_DIVIDER_NDIV_f 0 /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f / 212 chipcHw_REG_PLL_DIVIDER_FRAC 213 = 0, when SS is disable 214 */ 215 216#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz) ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz))) 217 218#define chipcHw_REG_ACLKClock_CLK_DIV_MASK 0x3 219 220/* System booting strap options */ 221#define chipcHw_STRAPS_SOFT_OVERRIDE 0x00000001 /* Software Strap Override */ 222 223#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8 0x00000000 /* 8 bit NAND FLASH Boot */ 224#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16 0x00000002 /* 16 bit NOR FLASH Boot */ 225#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH 0x00000004 /* Serial FLASH Boot */ 226#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16 0x00000006 /* 16 bit NAND FLASH Boot */ 227#define chipcHw_STRAPS_BOOT_DEVICE_UART 0x00000008 /* UART Boot */ 228#define chipcHw_STRAPS_BOOT_DEVICE_MASK 0x0000000E /* Mask */ 229 230/* System boot option */ 231#define chipcHw_STRAPS_BOOT_OPTION_BROM 0x00000000 /* Boot from Boot ROM */ 232#define chipcHw_STRAPS_BOOT_OPTION_ARAM 0x00000020 /* Boot from ARAM */ 233#define chipcHw_STRAPS_BOOT_OPTION_NOR 0x00000030 /* Boot from NOR flash */ 234 235/* NAND Flash page size strap options */ 236#define chipcHw_STRAPS_NAND_PAGESIZE_512 0x00000000 /* NAND FLASH page size of 512 bytes */ 237#define chipcHw_STRAPS_NAND_PAGESIZE_2048 0x00000040 /* NAND FLASH page size of 2048 bytes */ 238#define chipcHw_STRAPS_NAND_PAGESIZE_4096 0x00000080 /* NAND FLASH page size of 4096 bytes */ 239#define chipcHw_STRAPS_NAND_PAGESIZE_EXT 0x000000C0 /* NAND FLASH page of extened size */ 240#define chipcHw_STRAPS_NAND_PAGESIZE_MASK 0x000000C0 /* Mask */ 241 242#define chipcHw_STRAPS_NAND_EXTRA_CYCLE 0x00000400 /* NAND FLASH address cycle configuration */ 243#define chipcHw_STRAPS_REBOOT_TO_UART 0x00000800 /* Reboot to UART on error */ 244 245/* Secure boot mode strap options */ 246#define chipcHw_STRAPS_BOOT_MODE_NORMAL 0x00000000 /* Normal Boot */ 247#define chipcHw_STRAPS_BOOT_MODE_DBG_SW 0x00000100 /* Software debugging Boot */ 248#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT 0x00000200 /* Boot rom debugging Boot */ 249#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET 0x00000300 /* Normal Boot (Quiet BootRom) */ 250#define chipcHw_STRAPS_BOOT_MODE_MASK 0x00000300 /* Mask */ 251 252/* Slave Mode straps */ 253#define chipcHw_STRAPS_I2CS 0x02000000 /* I2C Slave */ 254#define chipcHw_STRAPS_SPIS 0x01000000 /* SPI Slave */ 255 256/* Strap pin options */ 257#define chipcHw_REG_SW_STRAPS ((pChipcHw->PinStraps & 0x0000FC00) >> 10) 258 259/* PIF/LCD pin sharing defines */ 260#define chipcHw_REG_LCD_PIN_ENABLE 0x00000001 /* LCD Controller is used and the pins have LCD functions */ 261#define chipcHw_REG_PIF_PIN_ENABLE 0x00000002 /* LCD pins are used to perform PIF functions */ 262 263#define chipcHw_GPIO_COUNT 61 /* Number of GPIO pin accessible thorugh CHIPC */ 264 265/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */ 266#define chipcHw_REG_GPIO_MUX_KEYPAD 0x00000001 /* GPIO mux for Keypad */ 267#define chipcHw_REG_GPIO_MUX_I2CH 0x00000002 /* GPIO mux for I2CH */ 268#define chipcHw_REG_GPIO_MUX_SPI 0x00000003 /* GPIO mux for SPI */ 269#define chipcHw_REG_GPIO_MUX_UART 0x00000004 /* GPIO mux for UART */ 270#define chipcHw_REG_GPIO_MUX_LEDMTXP 0x00000005 /* GPIO mux for LEDMTXP */ 271#define chipcHw_REG_GPIO_MUX_LEDMTXS 0x00000006 /* GPIO mux for LEDMTXS */ 272#define chipcHw_REG_GPIO_MUX_SDIO0 0x00000007 /* GPIO mux for SDIO0 */ 273#define chipcHw_REG_GPIO_MUX_SDIO1 0x00000008 /* GPIO mux for SDIO1 */ 274#define chipcHw_REG_GPIO_MUX_PCM 0x00000009 /* GPIO mux for PCM */ 275#define chipcHw_REG_GPIO_MUX_I2S 0x0000000A /* GPIO mux for I2S */ 276#define chipcHw_REG_GPIO_MUX_ETM 0x0000000B /* GPIO mux for ETM */ 277#define chipcHw_REG_GPIO_MUX_DEBUG 0x0000000C /* GPIO mux for DEBUG */ 278#define chipcHw_REG_GPIO_MUX_MISC 0x0000000D /* GPIO mux for MISC */ 279#define chipcHw_REG_GPIO_MUX_GPIO 0x00000000 /* GPIO mux for GPIO */ 280#define chipcHw_REG_GPIO_MUX(pin) (&pChipcHw->GpioMux_0_7 + ((pin) >> 3)) 281#define chipcHw_REG_GPIO_MUX_POSITION(pin) (((pin) & 0x00000007) << 2) 282#define chipcHw_REG_GPIO_MUX_MASK 0x0000000F /* Mask */ 283 284#define chipcHw_REG_SLEW_RATE_HIGH 0x00000000 /* High speed slew rate */ 285#define chipcHw_REG_SLEW_RATE_NORMAL 0x00000008 /* Normal slew rate */ 286 /* Pins beyond 42 are defined by skipping 8 bits within the register */ 287#define chipcHw_REG_SLEW_RATE(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3))) 288#define chipcHw_REG_SLEW_RATE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2)) 289#define chipcHw_REG_SLEW_RATE_MASK 0x00000008 /* Mask */ 290 291#define chipcHw_REG_CURRENT_STRENGTH_2mA 0x00000001 /* Current driving strength 2 milli ampere */ 292#define chipcHw_REG_CURRENT_STRENGTH_4mA 0x00000002 /* Current driving strength 4 milli ampere */ 293#define chipcHw_REG_CURRENT_STRENGTH_6mA 0x00000004 /* Current driving strength 6 milli ampere */ 294#define chipcHw_REG_CURRENT_STRENGTH_8mA 0x00000005 /* Current driving strength 8 milli ampere */ 295#define chipcHw_REG_CURRENT_STRENGTH_10mA 0x00000006 /* Current driving strength 10 milli ampere */ 296#define chipcHw_REG_CURRENT_STRENGTH_12mA 0x00000007 /* Current driving strength 12 milli ampere */ 297#define chipcHw_REG_CURRENT_MASK 0x00000007 /* Mask */ 298 /* Pins beyond 42 are defined by skipping 8 bits */ 299#define chipcHw_REG_CURRENT(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3))) 300#define chipcHw_REG_CURRENT_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2)) 301 302#define chipcHw_REG_PULL_NONE 0x00000000 /* No pull up register */ 303#define chipcHw_REG_PULL_UP 0x00000001 /* Pull up register enable */ 304#define chipcHw_REG_PULL_DOWN 0x00000002 /* Pull down register enable */ 305#define chipcHw_REG_PULLUP_MASK 0x00000003 /* Mask */ 306 /* Pins beyond 42 are defined by skipping 4 bits */ 307#define chipcHw_REG_PULLUP(pin) (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4))) 308#define chipcHw_REG_PULLUP_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1)) 309 310#define chipcHw_REG_INPUTTYPE_CMOS 0x00000000 /* Normal CMOS logic */ 311#define chipcHw_REG_INPUTTYPE_ST 0x00000001 /* High speed Schmitt Trigger */ 312#define chipcHw_REG_INPUTTYPE_MASK 0x00000001 /* Mask */ 313 /* Pins beyond 42 are defined by skipping 2 bits */ 314#define chipcHw_REG_INPUTTYPE(pin) (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5))) 315#define chipcHw_REG_INPUTTYPE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F))) 316 317/* Device connected to the bus clock */ 318#define chipcHw_REG_BUS_CLOCK_ARM 0x00000001 /* Bus interface clock for ARM */ 319#define chipcHw_REG_BUS_CLOCK_VDEC 0x00000002 /* Bus interface clock for VDEC */ 320#define chipcHw_REG_BUS_CLOCK_ARAM 0x00000004 /* Bus interface clock for ARAM */ 321#define chipcHw_REG_BUS_CLOCK_HPM 0x00000008 /* Bus interface clock for HPM */ 322#define chipcHw_REG_BUS_CLOCK_DDRC 0x00000010 /* Bus interface clock for DDRC */ 323#define chipcHw_REG_BUS_CLOCK_DMAC0 0x00000020 /* Bus interface clock for DMAC0 */ 324#define chipcHw_REG_BUS_CLOCK_DMAC1 0x00000040 /* Bus interface clock for DMAC1 */ 325#define chipcHw_REG_BUS_CLOCK_NVI 0x00000080 /* Bus interface clock for NVI */ 326#define chipcHw_REG_BUS_CLOCK_ESW 0x00000100 /* Bus interface clock for ESW */ 327#define chipcHw_REG_BUS_CLOCK_GE 0x00000200 /* Bus interface clock for GE */ 328#define chipcHw_REG_BUS_CLOCK_I2CH 0x00000400 /* Bus interface clock for I2CH */ 329#define chipcHw_REG_BUS_CLOCK_I2S0 0x00000800 /* Bus interface clock for I2S0 */ 330#define chipcHw_REG_BUS_CLOCK_I2S1 0x00001000 /* Bus interface clock for I2S1 */ 331#define chipcHw_REG_BUS_CLOCK_VRAM 0x00002000 /* Bus interface clock for VRAM */ 332#define chipcHw_REG_BUS_CLOCK_CLCD 0x00004000 /* Bus interface clock for CLCD */ 333#define chipcHw_REG_BUS_CLOCK_LDK 0x00008000 /* Bus interface clock for LDK */ 334#define chipcHw_REG_BUS_CLOCK_LED 0x00010000 /* Bus interface clock for LED */ 335#define chipcHw_REG_BUS_CLOCK_OTP 0x00020000 /* Bus interface clock for OTP */ 336#define chipcHw_REG_BUS_CLOCK_PIF 0x00040000 /* Bus interface clock for PIF */ 337#define chipcHw_REG_BUS_CLOCK_SPU 0x00080000 /* Bus interface clock for SPU */ 338#define chipcHw_REG_BUS_CLOCK_SDIO0 0x00100000 /* Bus interface clock for SDIO0 */ 339#define chipcHw_REG_BUS_CLOCK_SDIO1 0x00200000 /* Bus interface clock for SDIO1 */ 340#define chipcHw_REG_BUS_CLOCK_SPIH 0x00400000 /* Bus interface clock for SPIH */ 341#define chipcHw_REG_BUS_CLOCK_SPIS 0x00800000 /* Bus interface clock for SPIS */ 342#define chipcHw_REG_BUS_CLOCK_UART0 0x01000000 /* Bus interface clock for UART0 */ 343#define chipcHw_REG_BUS_CLOCK_UART1 0x02000000 /* Bus interface clock for UART1 */ 344#define chipcHw_REG_BUS_CLOCK_BBL 0x04000000 /* Bus interface clock for BBL */ 345#define chipcHw_REG_BUS_CLOCK_I2CS 0x08000000 /* Bus interface clock for I2CS */ 346#define chipcHw_REG_BUS_CLOCK_USBH 0x10000000 /* Bus interface clock for USB Host */ 347#define chipcHw_REG_BUS_CLOCK_USBD 0x20000000 /* Bus interface clock for USB Device */ 348#define chipcHw_REG_BUS_CLOCK_BROM 0x40000000 /* Bus interface clock for Boot ROM */ 349#define chipcHw_REG_BUS_CLOCK_TSC 0x80000000 /* Bus interface clock for Touch screen */ 350 351/* Software resets defines */ 352#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD 0x0000000080000000ULL /* Reset Global VPM and hold */ 353#define chipcHw_REG_SOFT_RESET_VPM_HOLD 0x0000000040000000ULL /* Reset VPM and hold */ 354#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL 0x0000000020000000ULL /* Reset Global VPM */ 355#define chipcHw_REG_SOFT_RESET_VPM 0x0000000010000000ULL /* Reset VPM */ 356#define chipcHw_REG_SOFT_RESET_KEYPAD 0x0000000008000000ULL /* Reset Key pad */ 357#define chipcHw_REG_SOFT_RESET_LED 0x0000000004000000ULL /* Reset LED */ 358#define chipcHw_REG_SOFT_RESET_SPU 0x0000000002000000ULL /* Reset SPU */ 359#define chipcHw_REG_SOFT_RESET_RNG 0x0000000001000000ULL /* Reset RNG */ 360#define chipcHw_REG_SOFT_RESET_PKA 0x0000000000800000ULL /* Reset PKA */ 361#define chipcHw_REG_SOFT_RESET_LCD 0x0000000000400000ULL /* Reset LCD */ 362#define chipcHw_REG_SOFT_RESET_PIF 0x0000000000200000ULL /* Reset PIF */ 363#define chipcHw_REG_SOFT_RESET_I2CS 0x0000000000100000ULL /* Reset I2C Slave */ 364#define chipcHw_REG_SOFT_RESET_I2CH 0x0000000000080000ULL /* Reset I2C Host */ 365#define chipcHw_REG_SOFT_RESET_SDIO1 0x0000000000040000ULL /* Reset SDIO 1 */ 366#define chipcHw_REG_SOFT_RESET_SDIO0 0x0000000000020000ULL /* Reset SDIO 0 */ 367#define chipcHw_REG_SOFT_RESET_BBL 0x0000000000010000ULL /* Reset BBL */ 368#define chipcHw_REG_SOFT_RESET_I2S1 0x0000000000008000ULL /* Reset I2S1 */ 369#define chipcHw_REG_SOFT_RESET_I2S0 0x0000000000004000ULL /* Reset I2S0 */ 370#define chipcHw_REG_SOFT_RESET_SPIS 0x0000000000002000ULL /* Reset SPI Slave */ 371#define chipcHw_REG_SOFT_RESET_SPIH 0x0000000000001000ULL /* Reset SPI Host */ 372#define chipcHw_REG_SOFT_RESET_GPIO1 0x0000000000000800ULL /* Reset GPIO block 1 */ 373#define chipcHw_REG_SOFT_RESET_GPIO0 0x0000000000000400ULL /* Reset GPIO block 0 */ 374#define chipcHw_REG_SOFT_RESET_UART1 0x0000000000000200ULL /* Reset UART 1 */ 375#define chipcHw_REG_SOFT_RESET_UART0 0x0000000000000100ULL /* Reset UART 0 */ 376#define chipcHw_REG_SOFT_RESET_NVI 0x0000000000000080ULL /* Reset NVI */ 377#define chipcHw_REG_SOFT_RESET_WDOG 0x0000000000000040ULL /* Reset Watch dog */ 378#define chipcHw_REG_SOFT_RESET_TMR 0x0000000000000020ULL /* Reset Timer */ 379#define chipcHw_REG_SOFT_RESET_ETM 0x0000000000000010ULL /* Reset ETM */ 380#define chipcHw_REG_SOFT_RESET_ARM_HOLD 0x0000000000000008ULL /* Reset ARM and HOLD */ 381#define chipcHw_REG_SOFT_RESET_ARM 0x0000000000000004ULL /* Reset ARM */ 382#define chipcHw_REG_SOFT_RESET_CHIP_WARM 0x0000000000000002ULL /* Chip warm reset */ 383#define chipcHw_REG_SOFT_RESET_CHIP_SOFT 0x0000000000000001ULL /* Chip soft reset */ 384#define chipcHw_REG_SOFT_RESET_VDEC 0x0000100000000000ULL /* Video decoder */ 385#define chipcHw_REG_SOFT_RESET_GE 0x0000080000000000ULL /* Graphics engine */ 386#define chipcHw_REG_SOFT_RESET_OTP 0x0000040000000000ULL /* Reset OTP */ 387#define chipcHw_REG_SOFT_RESET_USB2 0x0000020000000000ULL /* Reset USB2 */ 388#define chipcHw_REG_SOFT_RESET_USB1 0x0000010000000000ULL /* Reset USB 1 */ 389#define chipcHw_REG_SOFT_RESET_USB 0x0000008000000000ULL /* Reset USB 1 and USB2 soft reset */ 390#define chipcHw_REG_SOFT_RESET_ESW 0x0000004000000000ULL /* Reset Ethernet switch */ 391#define chipcHw_REG_SOFT_RESET_ESWCLK 0x0000002000000000ULL /* Reset Ethernet switch clock */ 392#define chipcHw_REG_SOFT_RESET_DDRPHY 0x0000001000000000ULL /* Reset DDR Physical */ 393#define chipcHw_REG_SOFT_RESET_DDR 0x0000000800000000ULL /* Reset DDR Controller */ 394#define chipcHw_REG_SOFT_RESET_TSC 0x0000000400000000ULL /* Reset Touch screen */ 395#define chipcHw_REG_SOFT_RESET_PCM 0x0000000200000000ULL /* Reset PCM device */ 396#define chipcHw_REG_SOFT_RESET_APM 0x0000200100000000ULL /* Reset APM device */ 397 398#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD 0x8000000000000000ULL /* Unhold Global VPM */ 399#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD 0x4000000000000000ULL /* Unhold VPM */ 400#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD 0x2000000000000000ULL /* Unhold ARM reset */ 401#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK 0xF000000000000000ULL /* Mask to handle unhold request */ 402 403/* Audio channel control defines */ 404#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL 0x00000001 /* Enable all audio channel */ 405#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A 0x00000002 /* Enable channel A */ 406#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B 0x00000004 /* Enable channel B */ 407#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C 0x00000008 /* Enable channel C */ 408#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK 0x00000010 /* Enable NTP clock */ 409#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK 0x00000020 /* Enable PCM0 clock */ 410#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK 0x00000040 /* Enable PCM1 clock */ 411#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK 0x00000080 /* Enable APM clock */ 412 413/* Misc. chip control defines */ 414#define chipcHw_REG_MISC_CTRL_GE_SEL 0x00040000 /* Select GE2/GE3 */ 415#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S1 */ 416#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO 0x00020000 /* Use external clock via GPIO pin 26 for I2S1 */ 417#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S0 */ 418#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO 0x00010000 /* Use external clock via GPIO pin 45 for I2S0 */ 419#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE 0x00008000 /* Disable ARM CP15 bit */ 420#define chipcHw_REG_MISC_CTRL_RTC_DISABLE 0x00000008 /* Disable RTC registers */ 421#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE 0x00000004 /* Disable Battery Backed RAM */ 422#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST 0x00000002 /* Set USB as host */ 423#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE 0xFFFFFFFD /* Set USB as device */ 424#define chipcHw_REG_MISC_CTRL_USB_POWERON 0xFFFFFFFE /* Power up USB */ 425#define chipcHw_REG_MISC_CTRL_USB_POWEROFF 0x00000001 /* Power down USB */ 426 427/* OTP configuration defines */ 428#define chipcHw_REG_OTP_SECURITY_OFF 0x0000020000000000ULL /* Security support is OFF */ 429#define chipcHw_REG_OTP_SPU_SLOW 0x0000010000000000ULL /* Limited SPU throughput */ 430#define chipcHw_REG_OTP_LCD_SPEED 0x0000000600000000ULL /* Set VPM speed one */ 431#define chipcHw_REG_OTP_VPM_SPEED_1 0x0000000100000000ULL /* Set VPM speed one */ 432#define chipcHw_REG_OTP_VPM_SPEED_0 0x0000000080000000ULL /* Set VPM speed zero */ 433#define chipcHw_REG_OTP_AXI_SPEED 0x0000000060000000ULL /* Set maximum AXI bus speed */ 434#define chipcHw_REG_OTP_APM_DISABLE 0x000000001F000000ULL /* Disable APM */ 435#define chipcHw_REG_OTP_PIF_DISABLE 0x0000000000200000ULL /* Disable PIF */ 436#define chipcHw_REG_OTP_VDEC_DISABLE 0x0000000000100000ULL /* Disable Video decoder */ 437#define chipcHw_REG_OTP_BBL_DISABLE 0x0000000000080000ULL /* Disable RTC and BBRAM */ 438#define chipcHw_REG_OTP_LED_DISABLE 0x0000000000040000ULL /* Disable LED */ 439#define chipcHw_REG_OTP_GE_DISABLE 0x0000000000020000ULL /* Disable Graphics Engine */ 440#define chipcHw_REG_OTP_LCD_DISABLE 0x0000000000010000ULL /* Disable LCD */ 441#define chipcHw_REG_OTP_KEYPAD_DISABLE 0x0000000000008000ULL /* Disable keypad */ 442#define chipcHw_REG_OTP_UART_DISABLE 0x0000000000004000ULL /* Disable UART */ 443#define chipcHw_REG_OTP_SDIOH_DISABLE 0x0000000000003000ULL /* Disable SDIO host */ 444#define chipcHw_REG_OTP_HSS_DISABLE 0x0000000000000C00ULL /* Disable HSS */ 445#define chipcHw_REG_OTP_TSC_DISABLE 0x0000000000000200ULL /* Disable touch screen */ 446#define chipcHw_REG_OTP_USB_DISABLE 0x0000000000000180ULL /* Disable USB */ 447#define chipcHw_REG_OTP_SGMII_DISABLE 0x0000000000000060ULL /* Disable SGMII */ 448#define chipcHw_REG_OTP_ETH_DISABLE 0x0000000000000018ULL /* Disable gigabit ethernet */ 449#define chipcHw_REG_OTP_ETH_PHY_DISABLE 0x0000000000000006ULL /* Disable ethernet PHY */ 450#define chipcHw_REG_OTP_VPM_DISABLE 0x0000000000000001ULL /* Disable VPM */ 451 452/* Sticky bit defines */ 453#define chipcHw_REG_STICKY_BOOT_DONE 0x00000001 /* Boot done */ 454#define chipcHw_REG_STICKY_SOFT_RESET 0x00000002 /* ARM soft reset */ 455#define chipcHw_REG_STICKY_GENERAL_1 0x00000004 /* General purpose bit 1 */ 456#define chipcHw_REG_STICKY_GENERAL_2 0x00000008 /* General purpose bit 2 */ 457#define chipcHw_REG_STICKY_GENERAL_3 0x00000010 /* General purpose bit 3 */ 458#define chipcHw_REG_STICKY_GENERAL_4 0x00000020 /* General purpose bit 4 */ 459#define chipcHw_REG_STICKY_GENERAL_5 0x00000040 /* General purpose bit 5 */ 460#define chipcHw_REG_STICKY_POR_BROM 0x00000080 /* Special sticky bit for security - set in BROM to avoid other modes being entered */ 461#define chipcHw_REG_STICKY_ARM_RESET 0x00000100 /* ARM reset */ 462#define chipcHw_REG_STICKY_CHIP_SOFT_RESET 0x00000200 /* Chip soft reset */ 463#define chipcHw_REG_STICKY_CHIP_WARM_RESET 0x00000400 /* Chip warm reset */ 464#define chipcHw_REG_STICKY_WDOG_RESET 0x00000800 /* Watchdog reset */ 465#define chipcHw_REG_STICKY_OTP_RESET 0x00001000 /* OTP reset */ 466 467 /* HW phase alignment defines *//* Spare1 register definitions */ 468#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE 0x80000000 /* Enable DDR phase align panic interrupt */ 469#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE 0x40000000 /* Enable VPM phase align panic interrupt */ 470#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE 0x00000002 /* Enable access to VPM using system BUS */ 471#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE 0x00000001 /* Enable access to DDR using system BUS */ 472 /* DDRPhaseCtrl1 register definitions */ 473#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable DDR SW phase alignment */ 474#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable DDR HW phase alignment */ 475#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK 0x0000007F /* DDR lower threshold for phase alignment */ 476#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT 23 477#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK 0x0000007F /* DDR upper threshold for phase alignment */ 478#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT 16 479#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to run next DDR phase alignment */ 480#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0 481 /* VPMPhaseCtrl1 register definitions */ 482#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable VPM SW phase alignment */ 483#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable VPM HW phase alignment */ 484#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK 0x0000007F /* VPM lower threshold for phase alignment */ 485#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT 23 486#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK 0x0000007F /* VPM upper threshold for phase alignment */ 487#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT 16 488#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to complete the VPM phase alignment */ 489#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0 490 /* PhaseAlignStatus register definitions */ 491#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS 0x80000000 /* DDR time out interrupt status */ 492#define chipcHw_REG_DDR_PHASE_STATUS_MASK 0x0000007F /* DDR phase status value */ 493#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT 24 494#define chipcHw_REG_DDR_PHASE_ALIGNED 0x00800000 /* DDR Phase aligned status */ 495#define chipcHw_REG_DDR_LOAD 0x00400000 /* Load DDR phase status */ 496#define chipcHw_REG_DDR_PHASE_CTRL_MASK 0x0000003F /* DDR phase control value */ 497#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT 16 498#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS 0x80000000 /* VPM time out interrupt status */ 499#define chipcHw_REG_VPM_PHASE_STATUS_MASK 0x0000007F /* VPM phase status value */ 500#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT 8 501#define chipcHw_REG_VPM_PHASE_ALIGNED 0x00000080 /* VPM Phase aligned status */ 502#define chipcHw_REG_VPM_LOAD 0x00000040 /* Load VPM phase status */ 503#define chipcHw_REG_VPM_PHASE_CTRL_MASK 0x0000003F /* VPM phase control value */ 504#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT 0 505 /* DDRPhaseCtrl2 register definitions */ 506#define chipcHw_REG_DDR_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */ 507#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */ 508#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */ 509#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT 20 510#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait to settle ph_ctrl and load_ch */ 511#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT 16 512#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for DDR HW phase alignment */ 513#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT 0 514 /* VPMPhaseCtrl2 register definitions */ 515#define chipcHw_REG_VPM_INTR_SELECT_MASK 0x00000003 /* Interrupt select */ 516#define chipcHw_REG_VPM_INTR_SELECT_SHIFT 26 517#define chipcHw_REG_VPM_INTR_DISABLE 0x00000000 518#define chipcHw_REG_VPM_INTR_FAST (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT) 519#define chipcHw_REG_VPM_INTR_MEDIUM (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT) 520#define chipcHw_REG_VPM_INTR_SLOW (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT) 521#define chipcHw_REG_VPM_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */ 522#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */ 523#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */ 524#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT 20 525#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait cycle to settle ph_ctrl and load_ch */ 526#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT 16 527#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for VPM HW phase alignment */ 528#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT 0 529 530#endif /* CHIPCHW_REG_H */ 531