1/***************************************************************************** 2* Copyright 2009 Broadcom Corporation. All rights reserved. 3* 4* Unless you and Broadcom execute a separate written software license 5* agreement governing use of this software, this software is licensed to you 6* under the terms of the GNU General Public License version 2, available at 7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). 8* 9* Notwithstanding the above, under no circumstances may you combine this 10* software in any way with any other Broadcom software provided under a 11* license other than the GPL, without Broadcom's express prior written 12* consent. 13*****************************************************************************/ 14 15#ifndef CAP_INLINE_H 16#define CAP_INLINE_H 17 18/* ---- Include Files ---------------------------------------------------- */ 19#include <mach/csp/cap.h> 20#include <cfg_global.h> 21 22/* ---- Public Constants and Types --------------------------------------- */ 23#define CAP_CONFIG0_VPM_DIS 0x00000001 24#define CAP_CONFIG0_ETH_PHY0_DIS 0x00000002 25#define CAP_CONFIG0_ETH_PHY1_DIS 0x00000004 26#define CAP_CONFIG0_ETH_GMII0_DIS 0x00000008 27#define CAP_CONFIG0_ETH_GMII1_DIS 0x00000010 28#define CAP_CONFIG0_ETH_SGMII0_DIS 0x00000020 29#define CAP_CONFIG0_ETH_SGMII1_DIS 0x00000040 30#define CAP_CONFIG0_USB0_DIS 0x00000080 31#define CAP_CONFIG0_USB1_DIS 0x00000100 32#define CAP_CONFIG0_TSC_DIS 0x00000200 33#define CAP_CONFIG0_EHSS0_DIS 0x00000400 34#define CAP_CONFIG0_EHSS1_DIS 0x00000800 35#define CAP_CONFIG0_SDIO0_DIS 0x00001000 36#define CAP_CONFIG0_SDIO1_DIS 0x00002000 37#define CAP_CONFIG0_UARTB_DIS 0x00004000 38#define CAP_CONFIG0_KEYPAD_DIS 0x00008000 39#define CAP_CONFIG0_CLCD_DIS 0x00010000 40#define CAP_CONFIG0_GE_DIS 0x00020000 41#define CAP_CONFIG0_LEDM_DIS 0x00040000 42#define CAP_CONFIG0_BBL_DIS 0x00080000 43#define CAP_CONFIG0_VDEC_DIS 0x00100000 44#define CAP_CONFIG0_PIF_DIS 0x00200000 45#define CAP_CONFIG0_RESERVED1_DIS 0x00400000 46#define CAP_CONFIG0_RESERVED2_DIS 0x00800000 47 48#define CAP_CONFIG1_APMA_DIS 0x00000001 49#define CAP_CONFIG1_APMB_DIS 0x00000002 50#define CAP_CONFIG1_APMC_DIS 0x00000004 51#define CAP_CONFIG1_CLCD_RES_MASK 0x00000600 52#define CAP_CONFIG1_CLCD_RES_SHIFT 9 53#define CAP_CONFIG1_CLCD_RES_WVGA (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT) 54#define CAP_CONFIG1_CLCD_RES_VGA (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT) 55#define CAP_CONFIG1_CLCD_RES_WQVGA (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT) 56#define CAP_CONFIG1_CLCD_RES_QVGA (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT) 57 58#define CAP_CONFIG2_SPU_DIS 0x00000010 59#define CAP_CONFIG2_PKA_DIS 0x00000020 60#define CAP_CONFIG2_RNG_DIS 0x00000080 61 62#if (CFG_GLOBAL_CHIP == BCM11107) 63#define capConfig0 0 64#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA 65#define capConfig2 0 66#define CAP_APM_MAX_NUM_CHANS 3 67#elif (CFG_GLOBAL_CHIP == FPGA11107) 68#define capConfig0 0 69#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA 70#define capConfig2 0 71#define CAP_APM_MAX_NUM_CHANS 3 72#elif (CFG_GLOBAL_CHIP == BCM11109) 73#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) 74#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA) 75#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) 76#define CAP_APM_MAX_NUM_CHANS 2 77#elif (CFG_GLOBAL_CHIP == BCM11170) 78#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) 79#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA) 80#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) 81#define CAP_APM_MAX_NUM_CHANS 2 82#elif (CFG_GLOBAL_CHIP == BCM11110) 83#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) 84#define capConfig1 CAP_CONFIG1_APMC_DIS 85#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) 86#define CAP_APM_MAX_NUM_CHANS 2 87#elif (CFG_GLOBAL_CHIP == BCM11211) 88#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS) 89#define capConfig1 CAP_CONFIG1_APMC_DIS 90#define capConfig2 0 91#define CAP_APM_MAX_NUM_CHANS 2 92#else 93#error CFG_GLOBAL_CHIP type capabilities not defined 94#endif 95 96#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107)) 97#define CAP_HW_CFG_ARM_CLK_HZ 500000000 98#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || \ 99 (CFG_GLOBAL_CHIP == BCM11110)) 100#define CAP_HW_CFG_ARM_CLK_HZ 300000000 101#elif (CFG_GLOBAL_CHIP == BCM11211) 102#define CAP_HW_CFG_ARM_CLK_HZ 666666666 103#else 104#error CFG_GLOBAL_CHIP type capabilities not defined 105#endif 106 107#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP \ 108 == FPGA11107)) 109#define CAP_HW_CFG_VPM_CLK_HZ 333333333 110#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || \ 111 (CFG_GLOBAL_CHIP == BCM11110)) 112#define CAP_HW_CFG_VPM_CLK_HZ 200000000 113#else 114#error CFG_GLOBAL_CHIP type capabilities not defined 115#endif 116 117/* ---- Public Variable Externs ------------------------------------------ */ 118/* ---- Public Function Prototypes --------------------------------------- */ 119 120/**************************************************************************** 121* cap_isPresent - 122* 123* PURPOSE: 124* Determines if the chip has a certain capability present 125* 126* PARAMETERS: 127* capability - type of capability to determine if present 128* 129* RETURNS: 130* CAP_PRESENT or CAP_NOT_PRESENT 131****************************************************************************/ 132static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index) 133{ 134 CAP_RC_T returnVal = CAP_NOT_PRESENT; 135 136 switch (capability) { 137 case CAP_VPM: 138 { 139 if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) { 140 returnVal = CAP_PRESENT; 141 } 142 } 143 break; 144 145 case CAP_ETH_PHY: 146 { 147 if ((index == 0) 148 && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) { 149 returnVal = CAP_PRESENT; 150 } 151 if ((index == 1) 152 && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) { 153 returnVal = CAP_PRESENT; 154 } 155 } 156 break; 157 158 case CAP_ETH_GMII: 159 { 160 if ((index == 0) 161 && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) { 162 returnVal = CAP_PRESENT; 163 } 164 if ((index == 1) 165 && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) { 166 returnVal = CAP_PRESENT; 167 } 168 } 169 break; 170 171 case CAP_ETH_SGMII: 172 { 173 if ((index == 0) 174 && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) { 175 returnVal = CAP_PRESENT; 176 } 177 if ((index == 1) 178 && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) { 179 returnVal = CAP_PRESENT; 180 } 181 } 182 break; 183 184 case CAP_USB: 185 { 186 if ((index == 0) 187 && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) { 188 returnVal = CAP_PRESENT; 189 } 190 if ((index == 1) 191 && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) { 192 returnVal = CAP_PRESENT; 193 } 194 } 195 break; 196 197 case CAP_TSC: 198 { 199 if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) { 200 returnVal = CAP_PRESENT; 201 } 202 } 203 break; 204 205 case CAP_EHSS: 206 { 207 if ((index == 0) 208 && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) { 209 returnVal = CAP_PRESENT; 210 } 211 if ((index == 1) 212 && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) { 213 returnVal = CAP_PRESENT; 214 } 215 } 216 break; 217 218 case CAP_SDIO: 219 { 220 if ((index == 0) 221 && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) { 222 returnVal = CAP_PRESENT; 223 } 224 if ((index == 1) 225 && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) { 226 returnVal = CAP_PRESENT; 227 } 228 } 229 break; 230 231 case CAP_UARTB: 232 { 233 if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) { 234 returnVal = CAP_PRESENT; 235 } 236 } 237 break; 238 239 case CAP_KEYPAD: 240 { 241 if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) { 242 returnVal = CAP_PRESENT; 243 } 244 } 245 break; 246 247 case CAP_CLCD: 248 { 249 if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) { 250 returnVal = CAP_PRESENT; 251 } 252 } 253 break; 254 255 case CAP_GE: 256 { 257 if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) { 258 returnVal = CAP_PRESENT; 259 } 260 } 261 break; 262 263 case CAP_LEDM: 264 { 265 if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) { 266 returnVal = CAP_PRESENT; 267 } 268 } 269 break; 270 271 case CAP_BBL: 272 { 273 if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) { 274 returnVal = CAP_PRESENT; 275 } 276 } 277 break; 278 279 case CAP_VDEC: 280 { 281 if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) { 282 returnVal = CAP_PRESENT; 283 } 284 } 285 break; 286 287 case CAP_PIF: 288 { 289 if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) { 290 returnVal = CAP_PRESENT; 291 } 292 } 293 break; 294 295 case CAP_APM: 296 { 297 if ((index == 0) 298 && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) { 299 returnVal = CAP_PRESENT; 300 } 301 if ((index == 1) 302 && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) { 303 returnVal = CAP_PRESENT; 304 } 305 if ((index == 2) 306 && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) { 307 returnVal = CAP_PRESENT; 308 } 309 } 310 break; 311 312 case CAP_SPU: 313 { 314 if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) { 315 returnVal = CAP_PRESENT; 316 } 317 } 318 break; 319 320 case CAP_PKA: 321 { 322 if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) { 323 returnVal = CAP_PRESENT; 324 } 325 } 326 break; 327 328 case CAP_RNG: 329 { 330 if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) { 331 returnVal = CAP_PRESENT; 332 } 333 } 334 break; 335 336 default: 337 { 338 } 339 break; 340 } 341 return returnVal; 342} 343 344/**************************************************************************** 345* cap_getMaxArmSpeedHz - 346* 347* PURPOSE: 348* Determines the maximum speed of the ARM CPU 349* 350* PARAMETERS: 351* none 352* 353* RETURNS: 354* clock speed in Hz that the ARM processor is able to run at 355****************************************************************************/ 356static inline uint32_t cap_getMaxArmSpeedHz(void) 357{ 358#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107)) 359 return 500000000; 360#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || \ 361 (CFG_GLOBAL_CHIP == BCM11110)) 362 return 300000000; 363#elif (CFG_GLOBAL_CHIP == BCM11211) 364 return 666666666; 365#else 366#error CFG_GLOBAL_CHIP type capabilities not defined 367#endif 368} 369 370/**************************************************************************** 371* cap_getMaxVpmSpeedHz - 372* 373* PURPOSE: 374* Determines the maximum speed of the VPM 375* 376* PARAMETERS: 377* none 378* 379* RETURNS: 380* clock speed in Hz that the VPM is able to run at 381****************************************************************************/ 382static inline uint32_t cap_getMaxVpmSpeedHz(void) 383{ 384#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP \ 385 == FPGA11107)) 386 return 333333333; 387#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || \ 388 (CFG_GLOBAL_CHIP == BCM11110)) 389 return 200000000; 390#else 391#error CFG_GLOBAL_CHIP type capabilities not defined 392#endif 393} 394 395/**************************************************************************** 396* cap_getMaxLcdRes - 397* 398* PURPOSE: 399* Determines the maximum LCD resolution capabilities 400* 401* PARAMETERS: 402* none 403* 404* RETURNS: 405* CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA 406* 407****************************************************************************/ 408static inline CAP_LCD_RES_T cap_getMaxLcdRes(void) 409{ 410 return (CAP_LCD_RES_T) 411 ((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >> 412 CAP_CONFIG1_CLCD_RES_SHIFT); 413} 414 415#endif 416