1/* 2 * arch/arm/mach-at91/at91sam9261_devices.c 3 * 4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org> 5 * Copyright (C) 2005 David Brownell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 */ 13#include <asm/mach/arch.h> 14#include <asm/mach/map.h> 15 16#include <linux/dma-mapping.h> 17#include <linux/platform_device.h> 18#include <linux/i2c-gpio.h> 19 20#include <linux/fb.h> 21#include <video/atmel_lcdc.h> 22 23#include <mach/board.h> 24#include <mach/gpio.h> 25#include <mach/at91sam9261.h> 26#include <mach/at91sam9261_matrix.h> 27#include <mach/at91sam9_smc.h> 28 29#include "generic.h" 30 31 32/* -------------------------------------------------------------------- 33 * USB Host 34 * -------------------------------------------------------------------- */ 35 36#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 37static u64 ohci_dmamask = DMA_BIT_MASK(32); 38static struct at91_usbh_data usbh_data; 39 40static struct resource usbh_resources[] = { 41 [0] = { 42 .start = AT91SAM9261_UHP_BASE, 43 .end = AT91SAM9261_UHP_BASE + SZ_1M - 1, 44 .flags = IORESOURCE_MEM, 45 }, 46 [1] = { 47 .start = AT91SAM9261_ID_UHP, 48 .end = AT91SAM9261_ID_UHP, 49 .flags = IORESOURCE_IRQ, 50 }, 51}; 52 53static struct platform_device at91sam9261_usbh_device = { 54 .name = "at91_ohci", 55 .id = -1, 56 .dev = { 57 .dma_mask = &ohci_dmamask, 58 .coherent_dma_mask = DMA_BIT_MASK(32), 59 .platform_data = &usbh_data, 60 }, 61 .resource = usbh_resources, 62 .num_resources = ARRAY_SIZE(usbh_resources), 63}; 64 65void __init at91_add_device_usbh(struct at91_usbh_data *data) 66{ 67 if (!data) 68 return; 69 70 usbh_data = *data; 71 platform_device_register(&at91sam9261_usbh_device); 72} 73#else 74void __init at91_add_device_usbh(struct at91_usbh_data *data) {} 75#endif 76 77 78/* -------------------------------------------------------------------- 79 * USB Device (Gadget) 80 * -------------------------------------------------------------------- */ 81 82#ifdef CONFIG_USB_GADGET_AT91 83static struct at91_udc_data udc_data; 84 85static struct resource udc_resources[] = { 86 [0] = { 87 .start = AT91SAM9261_BASE_UDP, 88 .end = AT91SAM9261_BASE_UDP + SZ_16K - 1, 89 .flags = IORESOURCE_MEM, 90 }, 91 [1] = { 92 .start = AT91SAM9261_ID_UDP, 93 .end = AT91SAM9261_ID_UDP, 94 .flags = IORESOURCE_IRQ, 95 }, 96}; 97 98static struct platform_device at91sam9261_udc_device = { 99 .name = "at91_udc", 100 .id = -1, 101 .dev = { 102 .platform_data = &udc_data, 103 }, 104 .resource = udc_resources, 105 .num_resources = ARRAY_SIZE(udc_resources), 106}; 107 108void __init at91_add_device_udc(struct at91_udc_data *data) 109{ 110 if (!data) 111 return; 112 113 if (data->vbus_pin) { 114 at91_set_gpio_input(data->vbus_pin, 0); 115 at91_set_deglitch(data->vbus_pin, 1); 116 } 117 118 /* Pullup pin is handled internally by USB device peripheral */ 119 120 udc_data = *data; 121 platform_device_register(&at91sam9261_udc_device); 122} 123#else 124void __init at91_add_device_udc(struct at91_udc_data *data) {} 125#endif 126 127/* -------------------------------------------------------------------- 128 * MMC / SD 129 * -------------------------------------------------------------------- */ 130 131#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) 132static u64 mmc_dmamask = DMA_BIT_MASK(32); 133static struct at91_mmc_data mmc_data; 134 135static struct resource mmc_resources[] = { 136 [0] = { 137 .start = AT91SAM9261_BASE_MCI, 138 .end = AT91SAM9261_BASE_MCI + SZ_16K - 1, 139 .flags = IORESOURCE_MEM, 140 }, 141 [1] = { 142 .start = AT91SAM9261_ID_MCI, 143 .end = AT91SAM9261_ID_MCI, 144 .flags = IORESOURCE_IRQ, 145 }, 146}; 147 148static struct platform_device at91sam9261_mmc_device = { 149 .name = "at91_mci", 150 .id = -1, 151 .dev = { 152 .dma_mask = &mmc_dmamask, 153 .coherent_dma_mask = DMA_BIT_MASK(32), 154 .platform_data = &mmc_data, 155 }, 156 .resource = mmc_resources, 157 .num_resources = ARRAY_SIZE(mmc_resources), 158}; 159 160void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) 161{ 162 if (!data) 163 return; 164 165 /* input/irq */ 166 if (data->det_pin) { 167 at91_set_gpio_input(data->det_pin, 1); 168 at91_set_deglitch(data->det_pin, 1); 169 } 170 if (data->wp_pin) 171 at91_set_gpio_input(data->wp_pin, 1); 172 if (data->vcc_pin) 173 at91_set_gpio_output(data->vcc_pin, 0); 174 175 /* CLK */ 176 at91_set_B_periph(AT91_PIN_PA2, 0); 177 178 /* CMD */ 179 at91_set_B_periph(AT91_PIN_PA1, 1); 180 181 /* DAT0, maybe DAT1..DAT3 */ 182 at91_set_B_periph(AT91_PIN_PA0, 1); 183 if (data->wire4) { 184 at91_set_B_periph(AT91_PIN_PA4, 1); 185 at91_set_B_periph(AT91_PIN_PA5, 1); 186 at91_set_B_periph(AT91_PIN_PA6, 1); 187 } 188 189 mmc_data = *data; 190 platform_device_register(&at91sam9261_mmc_device); 191} 192#else 193void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} 194#endif 195 196 197/* -------------------------------------------------------------------- 198 * NAND / SmartMedia 199 * -------------------------------------------------------------------- */ 200 201#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE) 202static struct atmel_nand_data nand_data; 203 204#define NAND_BASE AT91_CHIPSELECT_3 205 206static struct resource nand_resources[] = { 207 { 208 .start = NAND_BASE, 209 .end = NAND_BASE + SZ_256M - 1, 210 .flags = IORESOURCE_MEM, 211 } 212}; 213 214static struct platform_device atmel_nand_device = { 215 .name = "atmel_nand", 216 .id = -1, 217 .dev = { 218 .platform_data = &nand_data, 219 }, 220 .resource = nand_resources, 221 .num_resources = ARRAY_SIZE(nand_resources), 222}; 223 224void __init at91_add_device_nand(struct atmel_nand_data *data) 225{ 226 unsigned long csa; 227 228 if (!data) 229 return; 230 231 csa = at91_sys_read(AT91_MATRIX_EBICSA); 232 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 233 234 /* enable pin */ 235 if (data->enable_pin) 236 at91_set_gpio_output(data->enable_pin, 1); 237 238 /* ready/busy pin */ 239 if (data->rdy_pin) 240 at91_set_gpio_input(data->rdy_pin, 1); 241 242 /* card detect pin */ 243 if (data->det_pin) 244 at91_set_gpio_input(data->det_pin, 1); 245 246 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ 247 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ 248 249 nand_data = *data; 250 platform_device_register(&atmel_nand_device); 251} 252 253#else 254void __init at91_add_device_nand(struct atmel_nand_data *data) {} 255#endif 256 257 258/* -------------------------------------------------------------------- 259 * TWI (i2c) 260 * -------------------------------------------------------------------- */ 261 262/* 263 * Prefer the GPIO code since the TWI controller isn't robust 264 * (gets overruns and underruns under load) and can only issue 265 * repeated STARTs in one scenario (the driver doesn't yet handle them). 266 */ 267#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) 268 269static struct i2c_gpio_platform_data pdata = { 270 .sda_pin = AT91_PIN_PA7, 271 .sda_is_open_drain = 1, 272 .scl_pin = AT91_PIN_PA8, 273 .scl_is_open_drain = 1, 274 .udelay = 2, /* ~100 kHz */ 275}; 276 277static struct platform_device at91sam9261_twi_device = { 278 .name = "i2c-gpio", 279 .id = -1, 280 .dev.platform_data = &pdata, 281}; 282 283void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 284{ 285 at91_set_GPIO_periph(AT91_PIN_PA7, 1); /* TWD (SDA) */ 286 at91_set_multi_drive(AT91_PIN_PA7, 1); 287 288 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */ 289 at91_set_multi_drive(AT91_PIN_PA8, 1); 290 291 i2c_register_board_info(0, devices, nr_devices); 292 platform_device_register(&at91sam9261_twi_device); 293} 294 295#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) 296 297static struct resource twi_resources[] = { 298 [0] = { 299 .start = AT91SAM9261_BASE_TWI, 300 .end = AT91SAM9261_BASE_TWI + SZ_16K - 1, 301 .flags = IORESOURCE_MEM, 302 }, 303 [1] = { 304 .start = AT91SAM9261_ID_TWI, 305 .end = AT91SAM9261_ID_TWI, 306 .flags = IORESOURCE_IRQ, 307 }, 308}; 309 310static struct platform_device at91sam9261_twi_device = { 311 .name = "at91_i2c", 312 .id = -1, 313 .resource = twi_resources, 314 .num_resources = ARRAY_SIZE(twi_resources), 315}; 316 317void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) 318{ 319 /* pins used for TWI interface */ 320 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */ 321 at91_set_multi_drive(AT91_PIN_PA7, 1); 322 323 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */ 324 at91_set_multi_drive(AT91_PIN_PA8, 1); 325 326 i2c_register_board_info(0, devices, nr_devices); 327 platform_device_register(&at91sam9261_twi_device); 328} 329#else 330void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {} 331#endif 332 333 334/* -------------------------------------------------------------------- 335 * SPI 336 * -------------------------------------------------------------------- */ 337 338#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) 339static u64 spi_dmamask = DMA_BIT_MASK(32); 340 341static struct resource spi0_resources[] = { 342 [0] = { 343 .start = AT91SAM9261_BASE_SPI0, 344 .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1, 345 .flags = IORESOURCE_MEM, 346 }, 347 [1] = { 348 .start = AT91SAM9261_ID_SPI0, 349 .end = AT91SAM9261_ID_SPI0, 350 .flags = IORESOURCE_IRQ, 351 }, 352}; 353 354static struct platform_device at91sam9261_spi0_device = { 355 .name = "atmel_spi", 356 .id = 0, 357 .dev = { 358 .dma_mask = &spi_dmamask, 359 .coherent_dma_mask = DMA_BIT_MASK(32), 360 }, 361 .resource = spi0_resources, 362 .num_resources = ARRAY_SIZE(spi0_resources), 363}; 364 365static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 }; 366 367static struct resource spi1_resources[] = { 368 [0] = { 369 .start = AT91SAM9261_BASE_SPI1, 370 .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1, 371 .flags = IORESOURCE_MEM, 372 }, 373 [1] = { 374 .start = AT91SAM9261_ID_SPI1, 375 .end = AT91SAM9261_ID_SPI1, 376 .flags = IORESOURCE_IRQ, 377 }, 378}; 379 380static struct platform_device at91sam9261_spi1_device = { 381 .name = "atmel_spi", 382 .id = 1, 383 .dev = { 384 .dma_mask = &spi_dmamask, 385 .coherent_dma_mask = DMA_BIT_MASK(32), 386 }, 387 .resource = spi1_resources, 388 .num_resources = ARRAY_SIZE(spi1_resources), 389}; 390 391static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 }; 392 393void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) 394{ 395 int i; 396 unsigned long cs_pin; 397 short enable_spi0 = 0; 398 short enable_spi1 = 0; 399 400 /* Choose SPI chip-selects */ 401 for (i = 0; i < nr_devices; i++) { 402 if (devices[i].controller_data) 403 cs_pin = (unsigned long) devices[i].controller_data; 404 else if (devices[i].bus_num == 0) 405 cs_pin = spi0_standard_cs[devices[i].chip_select]; 406 else 407 cs_pin = spi1_standard_cs[devices[i].chip_select]; 408 409 if (devices[i].bus_num == 0) 410 enable_spi0 = 1; 411 else 412 enable_spi1 = 1; 413 414 /* enable chip-select pin */ 415 at91_set_gpio_output(cs_pin, 1); 416 417 /* pass chip-select pin to driver */ 418 devices[i].controller_data = (void *) cs_pin; 419 } 420 421 spi_register_board_info(devices, nr_devices); 422 423 /* Configure SPI bus(es) */ 424 if (enable_spi0) { 425 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ 426 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ 427 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ 428 429 at91_clock_associate("spi0_clk", &at91sam9261_spi0_device.dev, "spi_clk"); 430 platform_device_register(&at91sam9261_spi0_device); 431 } 432 if (enable_spi1) { 433 at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */ 434 at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */ 435 at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */ 436 437 at91_clock_associate("spi1_clk", &at91sam9261_spi1_device.dev, "spi_clk"); 438 platform_device_register(&at91sam9261_spi1_device); 439 } 440} 441#else 442void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} 443#endif 444 445 446/* -------------------------------------------------------------------- 447 * LCD Controller 448 * -------------------------------------------------------------------- */ 449 450#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) 451static u64 lcdc_dmamask = DMA_BIT_MASK(32); 452static struct atmel_lcdfb_info lcdc_data; 453 454static struct resource lcdc_resources[] = { 455 [0] = { 456 .start = AT91SAM9261_LCDC_BASE, 457 .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1, 458 .flags = IORESOURCE_MEM, 459 }, 460 [1] = { 461 .start = AT91SAM9261_ID_LCDC, 462 .end = AT91SAM9261_ID_LCDC, 463 .flags = IORESOURCE_IRQ, 464 }, 465#if defined(CONFIG_FB_INTSRAM) 466 [2] = { 467 .start = AT91SAM9261_SRAM_BASE, 468 .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1, 469 .flags = IORESOURCE_MEM, 470 }, 471#endif 472}; 473 474static struct platform_device at91_lcdc_device = { 475 .name = "atmel_lcdfb", 476 .id = 0, 477 .dev = { 478 .dma_mask = &lcdc_dmamask, 479 .coherent_dma_mask = DMA_BIT_MASK(32), 480 .platform_data = &lcdc_data, 481 }, 482 .resource = lcdc_resources, 483 .num_resources = ARRAY_SIZE(lcdc_resources), 484}; 485 486void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) 487{ 488 if (!data) { 489 return; 490 } 491 492#if defined(CONFIG_FB_ATMEL_STN) 493 at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */ 494 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ 495 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ 496 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ 497 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ 498 at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */ 499 at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */ 500 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ 501 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ 502#else 503 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ 504 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ 505 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ 506 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ 507 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ 508 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ 509 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ 510 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ 511 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ 512 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ 513 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ 514 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ 515 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ 516 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ 517 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ 518 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ 519 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ 520 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ 521 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ 522 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ 523 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ 524 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ 525#endif 526 527 if (ARRAY_SIZE(lcdc_resources) > 2) { 528 void __iomem *fb; 529 struct resource *fb_res = &lcdc_resources[2]; 530 size_t fb_len = fb_res->end - fb_res->start + 1; 531 532 fb = ioremap(fb_res->start, fb_len); 533 if (fb) { 534 memset(fb, 0, fb_len); 535 iounmap(fb); 536 } 537 } 538 lcdc_data = *data; 539 platform_device_register(&at91_lcdc_device); 540} 541#else 542void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} 543#endif 544 545 546/* -------------------------------------------------------------------- 547 * Timer/Counter block 548 * -------------------------------------------------------------------- */ 549 550#ifdef CONFIG_ATMEL_TCLIB 551 552static struct resource tcb_resources[] = { 553 [0] = { 554 .start = AT91SAM9261_BASE_TCB0, 555 .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1, 556 .flags = IORESOURCE_MEM, 557 }, 558 [1] = { 559 .start = AT91SAM9261_ID_TC0, 560 .end = AT91SAM9261_ID_TC0, 561 .flags = IORESOURCE_IRQ, 562 }, 563 [2] = { 564 .start = AT91SAM9261_ID_TC1, 565 .end = AT91SAM9261_ID_TC1, 566 .flags = IORESOURCE_IRQ, 567 }, 568 [3] = { 569 .start = AT91SAM9261_ID_TC2, 570 .end = AT91SAM9261_ID_TC2, 571 .flags = IORESOURCE_IRQ, 572 }, 573}; 574 575static struct platform_device at91sam9261_tcb_device = { 576 .name = "atmel_tcb", 577 .id = 0, 578 .resource = tcb_resources, 579 .num_resources = ARRAY_SIZE(tcb_resources), 580}; 581 582static void __init at91_add_device_tc(void) 583{ 584 /* this chip has a separate clock and irq for each TC channel */ 585 at91_clock_associate("tc0_clk", &at91sam9261_tcb_device.dev, "t0_clk"); 586 at91_clock_associate("tc1_clk", &at91sam9261_tcb_device.dev, "t1_clk"); 587 at91_clock_associate("tc2_clk", &at91sam9261_tcb_device.dev, "t2_clk"); 588 platform_device_register(&at91sam9261_tcb_device); 589} 590#else 591static void __init at91_add_device_tc(void) { } 592#endif 593 594 595/* -------------------------------------------------------------------- 596 * RTT 597 * -------------------------------------------------------------------- */ 598 599static struct resource rtt_resources[] = { 600 { 601 .start = AT91_BASE_SYS + AT91_RTT, 602 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, 603 .flags = IORESOURCE_MEM, 604 } 605}; 606 607static struct platform_device at91sam9261_rtt_device = { 608 .name = "at91_rtt", 609 .id = 0, 610 .resource = rtt_resources, 611 .num_resources = ARRAY_SIZE(rtt_resources), 612}; 613 614static void __init at91_add_device_rtt(void) 615{ 616 platform_device_register(&at91sam9261_rtt_device); 617} 618 619 620/* -------------------------------------------------------------------- 621 * Watchdog 622 * -------------------------------------------------------------------- */ 623 624#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) 625static struct platform_device at91sam9261_wdt_device = { 626 .name = "at91_wdt", 627 .id = -1, 628 .num_resources = 0, 629}; 630 631static void __init at91_add_device_watchdog(void) 632{ 633 platform_device_register(&at91sam9261_wdt_device); 634} 635#else 636static void __init at91_add_device_watchdog(void) {} 637#endif 638 639 640/* -------------------------------------------------------------------- 641 * SSC -- Synchronous Serial Controller 642 * -------------------------------------------------------------------- */ 643 644#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE) 645static u64 ssc0_dmamask = DMA_BIT_MASK(32); 646 647static struct resource ssc0_resources[] = { 648 [0] = { 649 .start = AT91SAM9261_BASE_SSC0, 650 .end = AT91SAM9261_BASE_SSC0 + SZ_16K - 1, 651 .flags = IORESOURCE_MEM, 652 }, 653 [1] = { 654 .start = AT91SAM9261_ID_SSC0, 655 .end = AT91SAM9261_ID_SSC0, 656 .flags = IORESOURCE_IRQ, 657 }, 658}; 659 660static struct platform_device at91sam9261_ssc0_device = { 661 .name = "ssc", 662 .id = 0, 663 .dev = { 664 .dma_mask = &ssc0_dmamask, 665 .coherent_dma_mask = DMA_BIT_MASK(32), 666 }, 667 .resource = ssc0_resources, 668 .num_resources = ARRAY_SIZE(ssc0_resources), 669}; 670 671static inline void configure_ssc0_pins(unsigned pins) 672{ 673 if (pins & ATMEL_SSC_TF) 674 at91_set_A_periph(AT91_PIN_PB21, 1); 675 if (pins & ATMEL_SSC_TK) 676 at91_set_A_periph(AT91_PIN_PB22, 1); 677 if (pins & ATMEL_SSC_TD) 678 at91_set_A_periph(AT91_PIN_PB23, 1); 679 if (pins & ATMEL_SSC_RD) 680 at91_set_A_periph(AT91_PIN_PB24, 1); 681 if (pins & ATMEL_SSC_RK) 682 at91_set_A_periph(AT91_PIN_PB25, 1); 683 if (pins & ATMEL_SSC_RF) 684 at91_set_A_periph(AT91_PIN_PB26, 1); 685} 686 687static u64 ssc1_dmamask = DMA_BIT_MASK(32); 688 689static struct resource ssc1_resources[] = { 690 [0] = { 691 .start = AT91SAM9261_BASE_SSC1, 692 .end = AT91SAM9261_BASE_SSC1 + SZ_16K - 1, 693 .flags = IORESOURCE_MEM, 694 }, 695 [1] = { 696 .start = AT91SAM9261_ID_SSC1, 697 .end = AT91SAM9261_ID_SSC1, 698 .flags = IORESOURCE_IRQ, 699 }, 700}; 701 702static struct platform_device at91sam9261_ssc1_device = { 703 .name = "ssc", 704 .id = 1, 705 .dev = { 706 .dma_mask = &ssc1_dmamask, 707 .coherent_dma_mask = DMA_BIT_MASK(32), 708 }, 709 .resource = ssc1_resources, 710 .num_resources = ARRAY_SIZE(ssc1_resources), 711}; 712 713static inline void configure_ssc1_pins(unsigned pins) 714{ 715 if (pins & ATMEL_SSC_TF) 716 at91_set_B_periph(AT91_PIN_PA17, 1); 717 if (pins & ATMEL_SSC_TK) 718 at91_set_B_periph(AT91_PIN_PA18, 1); 719 if (pins & ATMEL_SSC_TD) 720 at91_set_B_periph(AT91_PIN_PA19, 1); 721 if (pins & ATMEL_SSC_RD) 722 at91_set_B_periph(AT91_PIN_PA20, 1); 723 if (pins & ATMEL_SSC_RK) 724 at91_set_B_periph(AT91_PIN_PA21, 1); 725 if (pins & ATMEL_SSC_RF) 726 at91_set_B_periph(AT91_PIN_PA22, 1); 727} 728 729static u64 ssc2_dmamask = DMA_BIT_MASK(32); 730 731static struct resource ssc2_resources[] = { 732 [0] = { 733 .start = AT91SAM9261_BASE_SSC2, 734 .end = AT91SAM9261_BASE_SSC2 + SZ_16K - 1, 735 .flags = IORESOURCE_MEM, 736 }, 737 [1] = { 738 .start = AT91SAM9261_ID_SSC2, 739 .end = AT91SAM9261_ID_SSC2, 740 .flags = IORESOURCE_IRQ, 741 }, 742}; 743 744static struct platform_device at91sam9261_ssc2_device = { 745 .name = "ssc", 746 .id = 2, 747 .dev = { 748 .dma_mask = &ssc2_dmamask, 749 .coherent_dma_mask = DMA_BIT_MASK(32), 750 }, 751 .resource = ssc2_resources, 752 .num_resources = ARRAY_SIZE(ssc2_resources), 753}; 754 755static inline void configure_ssc2_pins(unsigned pins) 756{ 757 if (pins & ATMEL_SSC_TF) 758 at91_set_B_periph(AT91_PIN_PC25, 1); 759 if (pins & ATMEL_SSC_TK) 760 at91_set_B_periph(AT91_PIN_PC26, 1); 761 if (pins & ATMEL_SSC_TD) 762 at91_set_B_periph(AT91_PIN_PC27, 1); 763 if (pins & ATMEL_SSC_RD) 764 at91_set_B_periph(AT91_PIN_PC28, 1); 765 if (pins & ATMEL_SSC_RK) 766 at91_set_B_periph(AT91_PIN_PC29, 1); 767 if (pins & ATMEL_SSC_RF) 768 at91_set_B_periph(AT91_PIN_PC30, 1); 769} 770 771/* 772 * SSC controllers are accessed through library code, instead of any 773 * kind of all-singing/all-dancing driver. For example one could be 774 * used by a particular I2S audio codec's driver, while another one 775 * on the same system might be used by a custom data capture driver. 776 */ 777void __init at91_add_device_ssc(unsigned id, unsigned pins) 778{ 779 struct platform_device *pdev; 780 781 /* 782 * NOTE: caller is responsible for passing information matching 783 * "pins" to whatever will be using each particular controller. 784 */ 785 switch (id) { 786 case AT91SAM9261_ID_SSC0: 787 pdev = &at91sam9261_ssc0_device; 788 configure_ssc0_pins(pins); 789 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk"); 790 break; 791 case AT91SAM9261_ID_SSC1: 792 pdev = &at91sam9261_ssc1_device; 793 configure_ssc1_pins(pins); 794 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk"); 795 break; 796 case AT91SAM9261_ID_SSC2: 797 pdev = &at91sam9261_ssc2_device; 798 configure_ssc2_pins(pins); 799 at91_clock_associate("ssc2_clk", &pdev->dev, "pclk"); 800 break; 801 default: 802 return; 803 } 804 805 platform_device_register(pdev); 806} 807 808#else 809void __init at91_add_device_ssc(unsigned id, unsigned pins) {} 810#endif 811 812 813/* -------------------------------------------------------------------- 814 * UART 815 * -------------------------------------------------------------------- */ 816 817#if defined(CONFIG_SERIAL_ATMEL) 818static struct resource dbgu_resources[] = { 819 [0] = { 820 .start = AT91_VA_BASE_SYS + AT91_DBGU, 821 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, 822 .flags = IORESOURCE_MEM, 823 }, 824 [1] = { 825 .start = AT91_ID_SYS, 826 .end = AT91_ID_SYS, 827 .flags = IORESOURCE_IRQ, 828 }, 829}; 830 831static struct atmel_uart_data dbgu_data = { 832 .use_dma_tx = 0, 833 .use_dma_rx = 0, /* DBGU not capable of receive DMA */ 834 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), 835}; 836 837static u64 dbgu_dmamask = DMA_BIT_MASK(32); 838 839static struct platform_device at91sam9261_dbgu_device = { 840 .name = "atmel_usart", 841 .id = 0, 842 .dev = { 843 .dma_mask = &dbgu_dmamask, 844 .coherent_dma_mask = DMA_BIT_MASK(32), 845 .platform_data = &dbgu_data, 846 }, 847 .resource = dbgu_resources, 848 .num_resources = ARRAY_SIZE(dbgu_resources), 849}; 850 851static inline void configure_dbgu_pins(void) 852{ 853 at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ 854 at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ 855} 856 857static struct resource uart0_resources[] = { 858 [0] = { 859 .start = AT91SAM9261_BASE_US0, 860 .end = AT91SAM9261_BASE_US0 + SZ_16K - 1, 861 .flags = IORESOURCE_MEM, 862 }, 863 [1] = { 864 .start = AT91SAM9261_ID_US0, 865 .end = AT91SAM9261_ID_US0, 866 .flags = IORESOURCE_IRQ, 867 }, 868}; 869 870static struct atmel_uart_data uart0_data = { 871 .use_dma_tx = 1, 872 .use_dma_rx = 1, 873}; 874 875static u64 uart0_dmamask = DMA_BIT_MASK(32); 876 877static struct platform_device at91sam9261_uart0_device = { 878 .name = "atmel_usart", 879 .id = 1, 880 .dev = { 881 .dma_mask = &uart0_dmamask, 882 .coherent_dma_mask = DMA_BIT_MASK(32), 883 .platform_data = &uart0_data, 884 }, 885 .resource = uart0_resources, 886 .num_resources = ARRAY_SIZE(uart0_resources), 887}; 888 889static inline void configure_usart0_pins(unsigned pins) 890{ 891 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ 892 at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ 893 894 if (pins & ATMEL_UART_RTS) 895 at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */ 896 if (pins & ATMEL_UART_CTS) 897 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */ 898} 899 900static struct resource uart1_resources[] = { 901 [0] = { 902 .start = AT91SAM9261_BASE_US1, 903 .end = AT91SAM9261_BASE_US1 + SZ_16K - 1, 904 .flags = IORESOURCE_MEM, 905 }, 906 [1] = { 907 .start = AT91SAM9261_ID_US1, 908 .end = AT91SAM9261_ID_US1, 909 .flags = IORESOURCE_IRQ, 910 }, 911}; 912 913static struct atmel_uart_data uart1_data = { 914 .use_dma_tx = 1, 915 .use_dma_rx = 1, 916}; 917 918static u64 uart1_dmamask = DMA_BIT_MASK(32); 919 920static struct platform_device at91sam9261_uart1_device = { 921 .name = "atmel_usart", 922 .id = 2, 923 .dev = { 924 .dma_mask = &uart1_dmamask, 925 .coherent_dma_mask = DMA_BIT_MASK(32), 926 .platform_data = &uart1_data, 927 }, 928 .resource = uart1_resources, 929 .num_resources = ARRAY_SIZE(uart1_resources), 930}; 931 932static inline void configure_usart1_pins(unsigned pins) 933{ 934 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ 935 at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ 936 937 if (pins & ATMEL_UART_RTS) 938 at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */ 939 if (pins & ATMEL_UART_CTS) 940 at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */ 941} 942 943static struct resource uart2_resources[] = { 944 [0] = { 945 .start = AT91SAM9261_BASE_US2, 946 .end = AT91SAM9261_BASE_US2 + SZ_16K - 1, 947 .flags = IORESOURCE_MEM, 948 }, 949 [1] = { 950 .start = AT91SAM9261_ID_US2, 951 .end = AT91SAM9261_ID_US2, 952 .flags = IORESOURCE_IRQ, 953 }, 954}; 955 956static struct atmel_uart_data uart2_data = { 957 .use_dma_tx = 1, 958 .use_dma_rx = 1, 959}; 960 961static u64 uart2_dmamask = DMA_BIT_MASK(32); 962 963static struct platform_device at91sam9261_uart2_device = { 964 .name = "atmel_usart", 965 .id = 3, 966 .dev = { 967 .dma_mask = &uart2_dmamask, 968 .coherent_dma_mask = DMA_BIT_MASK(32), 969 .platform_data = &uart2_data, 970 }, 971 .resource = uart2_resources, 972 .num_resources = ARRAY_SIZE(uart2_resources), 973}; 974 975static inline void configure_usart2_pins(unsigned pins) 976{ 977 at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ 978 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ 979 980 if (pins & ATMEL_UART_RTS) 981 at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/ 982 if (pins & ATMEL_UART_CTS) 983 at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */ 984} 985 986static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 987struct platform_device *atmel_default_console_device; /* the serial console device */ 988 989void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 990{ 991 struct platform_device *pdev; 992 993 switch (id) { 994 case 0: /* DBGU */ 995 pdev = &at91sam9261_dbgu_device; 996 configure_dbgu_pins(); 997 at91_clock_associate("mck", &pdev->dev, "usart"); 998 break; 999 case AT91SAM9261_ID_US0: 1000 pdev = &at91sam9261_uart0_device; 1001 configure_usart0_pins(pins); 1002 at91_clock_associate("usart0_clk", &pdev->dev, "usart"); 1003 break; 1004 case AT91SAM9261_ID_US1: 1005 pdev = &at91sam9261_uart1_device; 1006 configure_usart1_pins(pins); 1007 at91_clock_associate("usart1_clk", &pdev->dev, "usart"); 1008 break; 1009 case AT91SAM9261_ID_US2: 1010 pdev = &at91sam9261_uart2_device; 1011 configure_usart2_pins(pins); 1012 at91_clock_associate("usart2_clk", &pdev->dev, "usart"); 1013 break; 1014 default: 1015 return; 1016 } 1017 pdev->id = portnr; /* update to mapped ID */ 1018 1019 if (portnr < ATMEL_MAX_UART) 1020 at91_uarts[portnr] = pdev; 1021} 1022 1023void __init at91_set_serial_console(unsigned portnr) 1024{ 1025 if (portnr < ATMEL_MAX_UART) 1026 atmel_default_console_device = at91_uarts[portnr]; 1027} 1028 1029void __init at91_add_device_serial(void) 1030{ 1031 int i; 1032 1033 for (i = 0; i < ATMEL_MAX_UART; i++) { 1034 if (at91_uarts[i]) 1035 platform_device_register(at91_uarts[i]); 1036 } 1037 1038 if (!atmel_default_console_device) 1039 printk(KERN_INFO "AT91: No default serial console defined.\n"); 1040} 1041#else 1042void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} 1043void __init at91_set_serial_console(unsigned portnr) {} 1044void __init at91_add_device_serial(void) {} 1045#endif 1046 1047 1048/* -------------------------------------------------------------------- */ 1049 1050/* 1051 * These devices are always present and don't need any board-specific 1052 * setup. 1053 */ 1054static int __init at91_add_standard_devices(void) 1055{ 1056 at91_add_device_rtt(); 1057 at91_add_device_watchdog(); 1058 at91_add_device_tc(); 1059 return 0; 1060} 1061 1062arch_initcall(at91_add_standard_devices); 1063