1/* 2 * Broadcom SiliconBackplane USB device core support 3 * 4 * Copyright (C) 2015, Broadcom Corporation 5 * All Rights Reserved. 6 * 7 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation; 8 * the contents of this file may not be disclosed to third parties, copied 9 * or duplicated in any form, in whole or in part, without the prior 10 * written permission of Broadcom Corporation. 11 * 12 * $Id: sbusbd.h 419467 2013-08-21 09:19:48Z $ 13 */ 14 15#ifndef _usbdev_sb_h_ 16#define _usbdev_sb_h_ 17 18#include <typedefs.h> 19#include <sbconfig.h> 20#include <sbhnddma.h> 21 22/* 23 * Control endpoint 0 maps to DMA engine 0 24 * IN endpoints 1-4 map to transmit side of DMA engines 1-4 25 * OUT endpoints 5-8 map to receive side DMA engines 1-4 26 */ 27#define DMA_MAX 5 28#define EP_MAX 9 29#define EP2DMA(ep) (((ep) < DMA_MAX) ? (ep) : ((ep) - DMA_MAX + 1)) 30#define DMA2EP(i, dir) (((i) == 0) ? 0 : ((dir) == EP_DIR_IN ? (i) : ((i) + DMA_MAX - 1))) 31 32/* rev 3 or higher has a dedicated DMA engine for Setup tokens */ 33#define SETUP_DMA 5 34#define SETUP_DMA_DEPTH 4 35 36/* cpp contortions to concatenate w/arg prescan */ 37#ifndef PAD 38#define _PADLINE(line) pad ## line 39#define _XSTR(line) _PADLINE(line) 40#define PAD _XSTR(__LINE__) 41#endif /* PAD */ 42 43/* dma64 corerev >= 7 */ 44typedef volatile struct { 45 dma64regs_t dmaxmt; /* dma tx */ 46 uint32 PAD[2]; 47 dma64regs_t dmarcv; /* dma rx */ 48 uint32 PAD[2]; 49} dma64_t; 50 51/* Host interface registers */ 52typedef volatile struct { 53 /* Device control */ 54 uint32 devcontrol; /* DevControl, 0x000, rev 2 */ 55 uint32 devstatus; /* DevStatus, 0x004, rev 2 */ 56 uint32 PAD[1]; 57 uint32 biststatus; /* BISTStatus, 0x00C, rev 2 */ 58 59 /* USB control */ 60 uint32 usbsetting; /* USBSetting, 0x010, rev 2 */ 61 uint32 usbframe; /* USBFrame, 0x014, rev 2 */ 62 uint32 lpmcontrol; /* LpmRegister, 0x18, rev 9 */ 63 uint32 PAD[1]; 64 65 /* 2nd level DMA int status/mask, IntStatus0-4, IntMask0-4 */ 66 struct { 67 uint32 status; 68 uint32 mask; 69 } dmaint[DMA_MAX]; /* 0x020 - 0x44, rev 2 */ 70 71 /* Top level interrupt status and mask */ 72 uint32 usbintstatus; /* IntStatus, 0x048, rev 2 */ 73 uint32 usbintmask; /* IntMask, 0x04C, rev 2 */ 74 75 /* Endpoint status */ 76 uint32 epstatus; /* CtrlOutStatus, 0x050, rev 2 */ 77 uint32 txfifowtermark; /* bytes threshold before commit tx, POR=0x100 */ 78 79 /* Dedicated 2nd level DMA int status/mask for Setup Data, rev 3 */ 80 uint32 sdintstatus; /* IntStatus5, 0x58, rev 3 */ 81 uint32 sdintmask; /* IntMask5, 0x5C, rev 3 */ 82 uint32 PAD[40]; 83 84 /* Lazy interrupt control, IntRcv0-4Lazy, 0x100-0x110, rev 2 */ 85 uint32 intrcvlazy[DMA_MAX]; 86 /* Setup token Lazy interrupt control, rev 3 */ 87 uint32 sdintrcvlazy; /* IntRcvLazy5 (Setup Data), 0x114, rev 3 */ 88 uint32 PAD[50]; 89 90 uint32 clkctlstatus; /* ClockCtlStatus, 0x1E0, rev 3 */ 91 uint32 PAD[7]; 92 93 /* DMA engine regs, 0x200-0x29C, rev 2 */ 94 dma32regp_t dmaregs[DMA_MAX]; 95 dma32diag_t dmafifo; /* fifo diag regs, 0x2A0-0x2AC */ 96 uint32 PAD[1]; 97 98 /* Endpoint byte counters, EPByteCount0-8, 0x2B4-0x2D4, rev 2 */ 99 uint32 epbytes[EP_MAX]; 100 uint32 PAD[2]; 101 102 uint32 hsicphyctrl1; /* HSICPhyCtrl1 0x2e0, rev 10 */ 103 uint32 hsicphyctrl2; /* HSICPhyCtrl2 0x2e4, rev 10 */ 104 uint32 hsicphystat1; /* HSICPhyStat1 0x2e8, rev 9 */ 105 uint32 PAD[9]; 106 uint32 utmi_ctl; /* utmi PHY contorol 0x310 */ 107 uint32 PAD[3]; 108 uint32 mdio_ctl; /* mdio_ctl, 0x320 */ 109 uint32 mdio_data; /* mdio_data, 0x324 */ 110 uint32 phymiscctl; /* PhyMiscCtl, 0x328, rev 4 */ 111 uint32 PAD[5]; 112 113 /* Dedicated Setup Data DMA engine, 0x340-0x35C, rev 3 */ 114 dma32regp_t sddmaregs; 115 uint32 PAD[40]; 116 117 /* Core registers */ 118 uint32 commandaddr; /* CommmandAddress, 0x400, rev 2 */ 119 /* EndPointConfig0-8, 0x404-0x424, rev 2 */ 120 uint32 epinfo[EP_MAX]; 121 uint32 PAD[54]; 122 123 /* 124 * dma64 registers, including Setup Data DMA engine, for corerev >= 7 125 * 0ffsets 0x500 to 0x674. 126 */ 127 dma64_t dma64regs[DMA_MAX + 1]; 128 uint32 PAD[544]; 129 130 131 /* Sonics SiliconBackplane registers */ 132 sbconfig_t sbconfig; 133} usbdev_sb_regs_t; 134 135/* Device control bits */ 136#define DC_RS (1L << 0) /* Device Reset */ 137#define DC_PL (1L << 1) /* USB11D: PLL Reset, USB20D PLL Power Down */ 138#define DC_US (1L << 2) /* USB Ready */ 139#define DC_ST (1L << 3) /* Force a Stall on all endpoints */ 140#define DC_RM (1L << 4) /* Resume */ 141#define DC_SD (1L << 5) /* Set Descriptor */ 142#define DC_SC (1L << 6) /* Sync Frame */ 143#define DC_SP (1L << 7) /* Self Power */ 144#define DC_RW (1L << 8) /* Remote Wakeup */ 145#define DC_AR (1L << 9) /* App Reset */ 146 147/* USB20 device specific bits */ 148#define DC_UP (1L << 10) /* UTMI Power Down */ 149#define DC_AP (1L << 11) /* Analog Power Down */ 150#define DC_PR (1L << 12) /* Phy Reset */ 151#define DC_SS_MASK 0x6000 /* Speed Select bits */ 152#define DC_SS_SHIFT 13 153#define DC_SS_FS 1 /* Full Speed */ 154#define DC_SS_HS 0 /* High Speed */ 155#define DC_PE (1L << 15) /* Phy Error Detect Enable */ 156#define DC_NZLP_MASK 0x30000 /* Non-zero length Packet Stall */ 157#define DC_NZLP_SHIFT 16 158#define DC_EH (1L << 18) /* Ep0 Halt Command Stall */ 159#define DC_HSTC_MASK 0x380000 /* HS Timeout Calibration */ 160#define DC_HSTC_SHIFT 19 161#define DC_FSTC_MASK 0x1c00000 /* FS Timeout Calibration */ 162#define DC_FSTC_SHIFT 22 163#define DC_DC (1L << 25) /* Soft Disconnect */ 164#define DC_UR (1L << 26) /* UTMI Soft Reset */ 165#define DC_UL (1L << 27) /* App ULPI Select */ 166#define DC_ULD (1L << 28) /* App ULPI DDR Select */ 167#define DC_LPM (1L << 29) /* LPM Enable */ 168#define DC_SS(n) (((uint32)(n) << DC_SS_SHIFT) & DC_SS_MASK) 169 170/* Device status bits */ 171#define DS_SP (1L << 0) /* Suspend */ 172#define DS_RS (1L << 1) /* Reset */ 173#define DS_PE (1L << 4) /* Phy Error (USB20D) */ 174#define DS_DS_MASK 0xC /* Device Operating Speed (USB20D) */ 175#define DS_DS_SHIFT 2 176#define DS_DS_HSCAP_HSMODE 0 /* HS cap, operating in HS mode */ 177#define DS_DS_HSCAP_FSMODE 1 /* HS cap, operating in FS mode */ 178#define DS_DS_FSCAP_FSMODE 3 /* FS cap, operating in FS mode */ 179#define DS_DS_HS (DS_DS_HSCAP_HSMODE << DS_DS_SHIFT) 180#define DS_PHYMODE_MASK 0x0300 181#define DS_PHYMODE_SHIFT 8 182#define DS_PHYMODE_NORMAL 0 /* normal operation */ 183#define DS_PHYMODE_NONDRIVING 1 /* nob-driving */ 184#define DS_PHYMODE_NOSTUFF_NZI 2 /* disable bit stuffing and NZI */ 185#define DS_RWF (1L << 10) /* LPM Device Remote Wakeup Feature rev 9 */ 186 187/* USB setting bits */ 188#define USB_CF_MASK 0x00f /* Configuration */ 189#define USB_CF_SHIFT 0 190#define USB_CF(n) (((uint32)(n) << USB_CF_SHIFT) & USB_CF_MASK) 191#define USB_IF_MASK 0x0f0 /* Interface */ 192#define USB_IF_SHIFT 4 193#define USB_IF(n) (((uint32)(n) << USB_IF_SHIFT) & USB_IF_MASK) 194#define USB_AI_MASK 0xf00 /* Alternate Interface */ 195#define USB_AI_SHIFT 8 196#define USB_AI(n) (((uint32)(n) << USB_AI_SHIFT) & USB_AI_MASK) 197#define USB_LPM_DATA_MASK 0xffff0000 /* LPM data. rev 9 */ 198#define USB_LPM_DATA_SHIFT 16 199#define USB_LPM_DATA_HANDSHAKE_MASK 0x60000000 /* LPM Handshake Sent. rev 9 */ 200#define USB_LPM_DATA_HANDSHAKE_SHIFT 29 201#define USB_LPM_DATA_REMOTEWK_MASK 0x10000000 /* LPM Remote Wakeup Enabled, rev 9 */ 202#define USB_LPM_DATA_REMOTEWK_SHIFT 28 203#define USB_LPM_DATA_HIRD_MASK 0xf000000 /* LPM HIRD. rev 9 */ 204#define USB_LPM_DATA_HIRD_SHIFT 24 205#define USB_LPM_DATA_LS_MASK 0xf00000 /* LPM Link State. rev 9 */ 206#define USB_LPM_DATA_LS_SHIFT 20 207#define USB_LPM_DATA_EP_MASK 0xf0000 /* USB endpoint. rev 9 */ 208#define USB_LPM_DATA_EP_SHIFT 16 209 210/* LPM Handshake */ 211#define USB_LPM_HANDSHAKE_ACK 0x2 /* ACK */ 212#define USB_LPM_HANDSHAKE_NAK 0xa /* NAK */ 213#define USB_LPM_HANDSHAKE_STALL 0xe /* STALL */ 214#define USB_LPM_HANDSHAKE_NYET 0x6 /* NYET */ 215 216/* LPM Link State */ 217#define USB_LPM_L1_SLEEP 0x1 /* L1 Sleep */ 218 219/* LPM Control bits */ 220#define LC_INT_THRESH 0xf 221#define LC_DS_THRESH 0xf0 222#define LC_DS_THRESH_SHIFT 4 223#define LC_DS_ENAB (1L << 8) 224#define LC_DOZE_ENAB (1L << 9) 225 226/* DMA interrupt bits */ 227#define I_PC (1L << 10) /* descriptor error */ 228#define I_PD (1L << 11) /* data error */ 229#define I_DE (1L << 12) /* Descriptor protocol Error */ 230#define I_RU (1L << 13) /* Receive descriptor Underflow */ 231#define I_RO (1L << 14) /* Receive fifo Overflow */ 232#define I_XU (1L << 15) /* Transmit fifo Underflow */ 233#define I_RI (1L << 16) /* Receive Interrupt */ 234#define I_XI (1L << 24) /* Transmit Interrupt */ 235#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) 236 237/* USB interrupt status and mask bits */ 238#define I_SETUP_MASK 0x0000003f /* Endpoint Setup interrupt (4:0) + Ctrl Req */ 239#define I_SETUP_SHIFT 0 240#define I_SETUP(n) (1L << ((n) + I_SETUP_SHIFT)) 241#define I_DEV_REQ (1L << 5) /* SetupDataPresent on Setup DMA engine, rev 3 */ 242#define I_LPM_SLEEP (1L << 6) /* LPM Sleep Event, rev 9 */ 243#define I_DATAERR_MASK 0x0003fe00 /* Endpoint Data Error (17:9) */ 244#define I_DATAERR_SHIFT 9 245#define I_DATAERR(n) (1L << ((n) + I_DATAERR_SHIFT)) 246#define I_SUS_RES (1L << 18) /* Suspend/Resume interrupt */ 247#define I_RESET (1L << 19) /* USB Reset interrupt */ 248#define I_SOF (1L << 20) /* USB Start of Frame interrupt */ 249#define I_CFG (1L << 21) /* Set Configuration interrupt */ 250#define I_DMA_MASK 0x07c00000 /* DMA interrupt pending (26:22) */ 251#define I_DMA_SHIFT 22 252#define I_DMA(n) (1L << ((n) + I_DMA_SHIFT)) 253#define I_TXDONE_MASK 0xf8000000 /* Transmit complete (31:27) */ 254#define I_TXDONE_SHIFT 27 255#define I_TXDONE(n) (1L << ((n) + I_TXDONE_SHIFT)) 256 257/* Interrupt receive lazy */ 258#define IRL_TO_MASK 0x00ffffff /* TimeOut (23:0) */ 259#define IRL_FC_MASK 0xff000000 /* Frame Count (31:24) */ 260#define IRL_FC_SHIFT 24 261#define IRL_FC(n) (((uint32)(n) << IRL_FC_SHIFT) & IRL_FC_MASK) 262 263/* ClkCtlStatus bits defined in sbconfig.h */ 264/* External Resource Requests */ 265#define CCS_USBCLKREQ 0x00000100 /* USB Clock Request */ 266 267/* External Resource Status */ 268#define CCS_USB_CLK_AVAIL 0x01000000 /* RO: USB Phy clock avail */ 269 270/* hsicphyctrl1 "PLL lock count" and "PLL reset count" bits */ 271#define HSIC_PULLDISABLE_MASK 0x00020000 /* Pull disable/force_buskeeper_off */ 272#define HSIC_PULLDISABLE_SHIFT 17 273#define PLL_LOCK_CT_MASK 0x0f000000 274#define PLL_LOCK_CT_SHIFT 24 275#define PLL_RESET_CT_MASK 0x30000000 276#define PLL_RESET_CT_SHIFT 28 277 278/* phymiscctrl */ 279#define PMC_PLL_SUSP_EN (1 << 0) 280#define PMC_PLL_CAL_EN (1 << 1) 281 282/* Endpoint status bits */ 283#define EPS_ERROR_MASK 0x0000001f /* Error direction: IN vs. OUT (4:0) */ 284#define EPS_ERROR_SHIFT 0 285#define EPS_ERROR(n) (1L << ((n) + EPS_ERROR_SHIFT)) 286#define EPS_STALL_MASK 0x00003fe0 /* Stall on endpoint (13:5) */ 287#define EPS_STALL_SHIFT 5 288#define EPS_STALL(n) (1L << ((n) + EPS_STALL_SHIFT)) 289#define EPS_SETUP_LOST_MASK 0x0007c000 /* Setup Lost (18:14) */ 290#define EPS_SETUP_LOST_SHIFT 14 291#define EPS_SETUP_LOST(n) (1L << ((n) + EPS_SETUP_LOST_SHIFT)) 292#define EPS_DONE_MASK 0x00f80000 /* Stop NAKing Status IN (23:19) */ 293#define EPS_DONE_SHIFT 19 294#define EPS_DONE(n) (1L << ((n) + EPS_DONE_SHIFT)) 295 296/* Endpoint info bits */ 297#define EP_EN_MASK 0x0000000f /* Endpoint Number (logical) */ 298#define EP_EN_SHIFT 0 299#define EP_EN(n) (((uint32)(n) << EP_EN_SHIFT) & EP_EN_MASK) 300#define EP_DIR_MASK 0x00000010 /* Endpoint Direction (4) */ 301#define EP_DIR_OUT 0x00000000 /* OUT Endpoint */ 302#define EP_DIR_IN 0x00000010 /* IN Endpoint */ 303#define EP_TYPE_MASK 0x00000060 /* Endpoint Type (6:5) */ 304#define EP_CONTROL 0x00000000 /* Control Endpoint */ 305#define EP_ISO 0x00000020 /* Isochronous Endpoint */ 306#define EP_BULK 0x00000040 /* Bulk Endpoint */ 307#define EP_INTR 0x00000060 /* Interrupt Endpoint */ 308#define EP_CF_MASK 0x00000780 /* Configuration Number (10:7) */ 309#define EP_CF_SHIFT 7 310#define EP_CF(n) (((uint32)(n) << EP_CF_SHIFT) & EP_CF_MASK) 311#define EP_IF_MASK 0x00007800 /* Interface Number (14:11) */ 312#define EP_IF_SHIFT 11 313#define EP_IF(n) (((uint32)(n) << EP_IF_SHIFT) & EP_IF_MASK) 314#define EP_AI_MASK 0x00078000 /* Alternate Interface Number (18:15) */ 315#define EP_AI_SHIFT 15 316#define EP_AI(n) (((uint32)(n) << EP_AI_SHIFT) & EP_AI_MASK) 317#define EP_MPS_MASK 0x1ff80000 /* Maximum Packet Size (28:19) */ 318#define EP_MPS_SHIFT 19 319#define EP_MPS(n) (((uint32)(n) << EP_MPS_SHIFT) & EP_MPS_MASK) 320 321/* AI chips-only: SFLAG originating from dmp regs DmpStatus/iostatus register */ 322#define SFLAG_HSIC 0x00000001 /* set=USB operating in HSIC mode */ 323 324/* AI chips-only: dmp regs DmpControl/ioctrl register bit definitions */ 325#define DMPIOC_CPULESS 0x00000004 /* set=reset will put core into CPULess mode */ 326 327/* CPULess mode direct backplane access Setup token bRequest field definitions */ 328#define CPULESS_INCR_ADDR 0x00 /* autoincrement by 1 or 4 bytes, depending on access len */ 329#define CPULESS_FIFO_ADDR 0xff /* fixed, FIFO-mode address access */ 330 331/* rx header */ 332typedef volatile struct { 333 uint16 len; 334 uint16 flags; 335} usbdev_sb_rxh_t; 336 337/* rx header flags */ 338#define RXF_SETUP 0x0001 /* rev 2 */ 339#define RXF_BAD 0x0002 /* rev 2 */ 340#define SETUP_TAG_SHIFT 2 /* rev 3 */ 341#define SETUP_TAG_MASK 0x000c /* rev 3 */ 342#define EP_ID_SHIFT 4 /* rev 3 */ 343#define EP_ID_MASK 0x00f0 /* rev 3 */ 344 345#define USB20DREV_IS(var, val) ((var) == (val)) 346#define USB20DREV_GE(var, val) ((var) >= (val)) 347#define USB20DREV_GT(var, val) ((var) > (val)) 348#define USB20DREV_LT(var, val) ((var) < (val)) 349#define USB20DREV_LE(var, val) ((var) <= (val)) 350 351#define USB20DDMAREG(ch, direction, fifonum) (USB20DREV_LT(ch->rev, 7) ? \ 352 ((direction == DMA_TX) ? \ 353 (void*)(uintptr)&(ch->regs->dmaregs[fifonum].xmt) : \ 354 (void*)(uintptr)&(ch->regs->dmaregs[fifonum].rcv)) : \ 355 ((direction == DMA_TX) ? \ 356 (void*)(uintptr)&(ch->regs->dma64regs[fifonum].dmaxmt) : \ 357 (void*)(uintptr)&(ch->regs->dma64regs[fifonum].dmarcv))) 358 359/* 360 * MDIO Phy Interface 361 */ 362#define USB_MDIOCTL_SMSEL_SHIFT 0 363#define USB_MDIOCTL_SMSEL_CLKEN 1 364#define USB_MDIOCTL_ID_SHIFT 1 365#define USB_MDIOCTL_ID_MASK 0x0000003E 366 367#define USB_MDIOCTL_WR_SHIFT 6 368#define USB_MDIOCTL_WR_EN 0x40 369#define USB_MDIOCTL_RD_SHIFT 7 370#define USB_MDIOCTL_RD_EN 0x80 371#define USB_MDIOCTL_REGADDR_SHIFT 8 372#define USB_MDIOCTL_REGADDR_MASK 0x00001F00 373#define USB_MDIOCTL_WRDATA_SHIFT 13 374#define USB_MDIOCTL_WRDATA_MASK 0x1FFFE000 375 376#define USB_MDIODAT_RDDATA_SHIFT 0 377#define USB_MDIODAT_RDDATA_MASK 0x0000FFFF 378 379#define USB_MDIO_ADDR_MAX 32 380 381/* HSIC Phy Slave */ 382#define HSIC_MDIO_SLAVE_ADDR 0x15 383#define HSIC_MDIO_REG_PHY_CFG0 0 384#define HSIC_MDIO_REG_PHY_CFG1 1 385#define HSIC_MDIO_REG_TST_CTL1 3 386#define HSIC_MDIO_REG_BERT_CNT 4 387#define HSIC_MDIO_REG_BERT_SZ 5 388#define HSIC_MDIO_REG_BERT_CFG0 6 389#define HSIC_MDIO_REG_BERT_CFG1 7 390#define HSIC_MDIO_REG_TST_CTL2 8 391#define HSIC_MDIO_REG_TST_CTL2_XWR_EN 0x40 392 393/* HSIC Phy Register Extensions */ 394#define HSIC_MDIO_REGEX_UNUSED 0 395#define HSIC_MDIO_REGEX_CTL0 1 396#define HSIC_MDIO_REGEX_CTL0_RST 0 397#define HSIC_MDIO_REGEX_CTL0_DIS 0x1 398#define HSIC_MDIO_REGEX_CTL0_EN 0x3 399#define HSIC_MDIO_REGEX_DIV_R0 2 400#define HSIC_MDIO_REGEX_DIV_R0_FREQ_MASK 0x000F 401#define HSIC_MDIO_REGEX_DIV_R1 3 402#define HSIC_MDIO_REGEX_DIV_R1_FREQ_MASK 0xFFFF 403 404#endif /* _usbdev_sb_h_ */ 405