1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * DRAM Startup Module File: sb1250_draminit.c 5 * 6 * This module contains code to initialize and start the DRAM 7 * controller on the SB1250. 8 * 9 * This is the fancy new init module, written in "C". 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions 27 * as they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. The "Broadcom Corporation" 31 * name may not be used to endorse or promote products derived 32 * from this software without the prior written permission of 33 * Broadcom Corporation. 34 * 35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 39 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 43 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 44 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 45 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 46 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 47 * THE POSSIBILITY OF SUCH DAMAGE. 48 ********************************************************************* */ 49 50/* 51 * This code can be linked into non-CFE, non-SB1250 things like SOCVIEW, a JTAG 52 * tool. In that case it's not even running on a 1250, but we can 53 * borrow the code to generate timing values for us. 54 * 55 * The _MCSTANDALONE_ ifdef is normally turned *off* for firmware use, 56 * but programs like "memconfig" (CFE host tool) or SOCVIEW use it 57 * to allow us to run the memory initialization outside a 1250. 58 */ 59 60#ifdef _MCSTANDALONE_ 61#include <stdio.h> 62#else 63#include "sbmips.h" 64#endif 65 66#include "sb1250_regs.h" 67#include "sb1250_mc.h" 68#include "sb1250_smbus.h" 69#include "sb1250_scd.h" 70 71/* 72 * Uncomment to use data mover to zero memory 73 * Note: this is not a good idea in Pass1, since we'll 74 * be running cacheable noncoherent at this point in the 75 * CFE init sequence. 76 */ 77/* #define _DMZERO_ */ 78 79#ifdef _DMZERO_ 80#include "sb1250_dma.h" 81#endif 82 83/* ********************************************************************* 84 * Magic Constants 85 ********************************************************************* */ 86 87/* 88 * This constant represents the "round trip" time of your board. 89 * Measured from the pins on the BCM1250, it is the time from the 90 * rising edge of the MCLK pin to the rising edge of the DQS coming 91 * back from the memory. 92 * 93 * It is used in the calculation of which cycle responses are expected 94 * from the memory for a given request. The units are in tenths of 95 * nanoseconds. 96 */ 97 98#define DEFAULT_MEMORY_ROUNDTRIP_TIME 25 /* 2.5ns (default) */ 99#define DEFAULT_MEMORY_ROUNDTRIP_TIME_FCRAM 20 /* 2.0ns for FCRAM */ 100 101 102#define PASS1_DLL_SCALE_NUMERATOR 30 /* 30/400 = 0.075 */ 103#define PASS1_DLL_SCALE_DENOMINATOR 400 104#define PASS1_DLL_OFFSET 63 /* 63/400 = 0.1575 */ 105 106#define PASS2_DLL_SCALE_NUMERATOR 30 /* 30/400 = 0.075 */ 107#define PASS2_DLL_SCALE_DENOMINATOR 400 108#define PASS2_DLL_OFFSET 63 /* 63/400 = 0.1575 */ 109 110 111/* 112 * The constants below were created by careful measurement of 113 * BCM1250 parts. The units are in tenths of nanoseconds 114 * to be compatible with the rest of the calculations in sb1250_auto_timing. 115 */ 116 117#define SB1250_MIN_R2W_TIME 30 /* 3.0 ns */ 118#define SB1250_MIN_DQS_MARGIN 25 119#define SB1250_WINDOW_OPEN_OFFSET 18 120#define SB1250_CLOSE_01_OFFSET 34 121#define SB1250_CLOSE_02_OFFSET 22 122#define SB1250_CLOSE_12_OFFSET 24 123 124 125 126/* ********************************************************************* 127 * Basic types 128 ********************************************************************* */ 129 130#ifdef _CFE_ 131#include "lib_types.h" 132#else 133typedef unsigned char uint8_t; 134typedef unsigned short uint16_t; 135typedef unsigned int uint32_t; 136typedef unsigned long long uint64_t; 137#endif 138 139/* 140 * For SOCVIEW and non-CFE, non-MIPS stuff, make sure the "port" 141 * data type is 64 bits. Otherwise we take our cue from 'long' 142 * which will be pointer-sized. 143 */ 144 145#if defined(_MCSTANDALONE_) 146typedef long long sbport_t; 147#else 148typedef long sbport_t; 149#endif 150 151#ifdef _CFE_ 152#include "bsp_config.h" 153#endif 154 155#define TRUE 1 156#define FALSE 0 157 158/* ********************************************************************* 159 * Configuration 160 ********************************************************************* */ 161 162/* 163 * This module needs to be compiled with mips64 to ensure that 64-bit 164 * values are in 64-bit registers and that reads/writes of 64-bit numbers 165 * are done with the ld/sd instructions. 166 */ 167#if !defined(__mips64) && !defined(_MCSTANDALONE_) 168#error "This module MUST be compiled with __mips64. See the comments for details." 169#endif 170 171/* 172 * Configure some stuff here if not running under the firmware. 173 */ 174 175#ifndef _CFE_ 176#define CFG_DRAM_ECC 0 177#define CFG_DRAM_SMBUS_CHANNEL 0 178#define CFG_DRAM_SMBUS_BASE 0x54 179#define CFG_DRAM_BLOCK_SIZE 32 180#endif 181 182 183/* 184 * Clock configuration parameters, except for the MCLK ratio 185 * which is set according to the value of the PLL divide ratio. 186 */ 187 188#define V_MC_CLKCONFIG_VALUE_PASS1 V_MC_ADDR_SKEW(0x0F) | \ 189 V_MC_DQO_SKEW(0x8) | \ 190 V_MC_DQI_SKEW(0x8) | \ 191 V_MC_ADDR_DRIVE(0xF) | \ 192 V_MC_DATA_DRIVE(0xF) | \ 193 V_MC_CLOCK_DRIVE(0) 194 195#define V_MC_CLKCONFIG_VALUE V_MC_ADDR_SKEW(0x08) | \ 196 V_MC_DQO_SKEW(0x8) | \ 197 V_MC_DQI_SKEW(0x8) | \ 198 V_MC_ADDR_DRIVE(0xF) | \ 199 V_MC_DATA_DRIVE(0xF) | \ 200 V_MC_CLOCK_DRIVE(0xF) 201 202/* 203 * These belong in some SB1250-specific file I'm sure. 204 */ 205 206#define MC_CHANNELS 2 /* we have two channels */ 207#define MC_CHIPSELS 4 /* and four chipsels per channel */ 208 209 210/* ********************************************************************* 211 * Reference Clock 212 ********************************************************************* */ 213 214#ifdef _MAGICWID_ 215 /* 216 * You really don't want to know about this. During testing, we futz 217 * with the 100mhz clock and store the actual speed of the clock 218 * in the PromICE so we can make the calculations work out correctly 219 * (and automatically) 220 */ 221 #define SB1250_REFCLK (*((uint64_t *) PHYS_TO_K1(0x1FC00018))) 222 #undef K_SMB_FREQ_100KHZ 223 #define K_SMB_FREQ_100KHZ ((SB1250_REFCLK*10)/8) 224#else 225 /* 226 * If non-CFE, non-MIPS, make the refclk an input parameter. 227 */ 228 #if defined(_MCSTANDALONE_) 229 int sb1250_refclk = 100; 230 int dram_cas_latency; 231 int dram_tMemClk; 232 #define SB1250_REFCLK sb1250_refclk 233 #endif 234#endif 235 236/* 237 * Define our reference clock. The default is 100MHz unless 238 * overridden. You can override this in your bsp_config.h file. 239 */ 240 241#ifdef SB1250_REFCLK_HZ 242 #define SB1250_REFCLK ((SB1250_REFCLK_HZ)/1000000) 243#endif 244 245#ifndef SB1250_REFCLK 246 #define SB1250_REFCLK 100 /* speed of refclk, in Mhz */ 247#endif 248 249/* ********************************************************************* 250 * Macros 251 ********************************************************************* */ 252 253/* 254 * For the general case, reads/writes to MC CSRs are just pointer 255 * references. In SOCVIEW and other non-CFE, non-MIPS programs, we hook the 256 * read/write calls to let us supply the data from somewhere else. 257 */ 258 259#if defined(_MCSTANDALONE_) 260 #define PHYS_TO_K1(x) (x) 261 #define WRITECSR(csr,val) sbwritecsr(csr,val) 262 #define READCSR(csr) sbreadcsr(csr) 263 extern void sbwritecsr(uint64_t,uint64_t); 264 extern uint64_t sbreadcsr(uint64_t); 265#else /* normal case */ 266 #define WRITECSR(csr,val) *((volatile uint64_t *) (csr)) = (val) 267 #define READCSR(csr) (*((volatile uint64_t *) (csr))) 268#endif 269 270/* ********************************************************************* 271 * JEDEC values 272 ********************************************************************* */ 273 274 275#define JEDEC_SDRAM_MRVAL_CAS15 0x52 /* 4-byte bursts, sequential, CAS 1.5 */ 276#define JEDEC_SDRAM_MRVAL_CAS2 0x22 /* 4-byte bursts, sequential, CAS 2 */ 277#define JEDEC_SDRAM_MRVAL_CAS25 0x62 /* 4-byte bursts, sequential, CAS 2.5 */ 278#define JEDEC_SDRAM_MRVAL_CAS3 0x32 /* 4-byte bursts, sequential, CAS 3 */ 279#define JEDEC_SDRAM_MRVAL_CAS35 0x72 /* 4-byte bursts, sequential, CAS 3.5 */ 280#define JEDEC_SDRAM_MRVAL_RESETDLL 0x100 281#define JEDEC_SDRAM_EMRVAL 0x00 282 283#define FCRAM_MRVAL 0x32 284#define FCRAM_EMRVAL 0 285 286#define SGRAM_MRVAL 0x32 /* 4-byte bursts, sequential, CAS 3 */ 287#define SGRAM_MRVAL_RESETDLL 0x400 288#define SGRAM_EMRVAL 0x02 289 290/* 291 * DECTO10THS(x) - this converts a BCD-style number found in 292 * JEDEC SPDs to a regular number. So, 0x75 might mean "7.5ns" 293 * and we convert this into tenths (75 decimal). Many of the 294 * calculations for the timing are done in terms of tenths of nanoseconds 295 */ 296 297#define DECTO10THS(x) ((((x) >> 4)*10)+((x) & 0x0F)) 298 299/* ********************************************************************* 300 * Configuration parameter values 301 ********************************************************************* */ 302 303#ifndef CFG_DRAM_MIN_tMEMCLK 304#define CFG_DRAM_MIN_tMEMCLK DRT10(8,0) /* 8 ns, 125Mhz */ 305#endif 306 307#ifndef CFG_DRAM_INTERLEAVE 308#define CFG_DRAM_INTERLEAVE 0 309#endif 310 311#ifndef CFG_DRAM_SMBUS_CHANNEL 312#define CFG_DRAM_SMBUS_CHANNEL 0 313#endif 314 315#ifndef CFG_DRAM_SMBUS_BASE 316#define CFG_DRAM_SMBUS_BASE 0x54 317#endif 318 319#ifndef CFG_DRAM_ECC 320#define CFG_DRAM_ECC 0 321#endif 322 323#ifndef CFG_DRAM_BLOCK_SIZE 324#define CFG_DRAM_BLOCK_SIZE 32 325#endif 326 327#ifndef CFG_DRAM_CSINTERLEAVE 328#define CFG_DRAM_CSINTERLEAVE 0 329#endif 330 331/* ********************************************************************* 332 * Memory region sizes (SB1250-specific) 333 ********************************************************************* */ 334 335#define REGION0_LOC 0x0000 336#define REGION0_SIZE 256 337 338#define REGION1_LOC 0x0800 339#define REGION1_SIZE 512 340 341#define REGION2_LOC 0x0C00 342#define REGION2_SIZE 256 343 344#define REGION3_LOC 0x1000 345#define REGION3_SIZE (508*1024) /* 508 GB! */ 346 347/* ********************************************************************* 348 * Global Data structure 349 * 350 * This is a hideous hack. We're going to actually use "memory" 351 * before it is configured. The L1 DCache will be clean before 352 * we get here, so we'll just locate this structure in memory 353 * (at 0, for example) and "hope" we don't need to evict anything. 354 * If we keep the data below 256 cache lines, we'll only use one way 355 * of each cache line. That's 8K, more than enough. 356 * 357 * This data structure needs to be used both for our data and the 358 * "C" stack, so be careful when you edit it! 359 ********************************************************************* */ 360 361typedef struct csdata_s { /* Geometry information from table */ 362 uint8_t rows; /* or SMBbus */ 363 uint8_t cols; 364 uint8_t banks; 365 uint8_t flags; 366 367 uint8_t spd_dramtype; /* SPD[2] */ 368 uint8_t spd_tCK_25; /* SPD[9] tCK @ CAS 2.5 */ 369 uint8_t spd_tCK_20; /* SPD[23] tCK @ CAS 2.0 */ 370 uint8_t spd_tCK_10; /* SPD[25] tCK @ CAS 1.0 */ 371 uint8_t spd_rfsh; /* SPD[12] Refresh Rate */ 372 uint8_t spd_caslatency; /* SPD[18] CAS Latencies Supported */ 373 uint8_t spd_attributes; /* SPD[21] Attributes */ 374 uint8_t spd_tRAS; /* SPD[30] */ 375 uint8_t spd_tRP; /* SPD[27] */ 376 uint8_t spd_tRRD; /* SPD[28] */ 377 uint8_t spd_tRCD; /* SPD[29] */ 378 uint8_t spd_tRFC; /* SPD[42] */ 379 uint8_t spd_tRC; /* SPD[41] */ 380 381} csdata_t; /* total size: 16 bytes */ 382 383#define CS_PRESENT 1 /* chipsel is present (in use) */ 384#define CS_AUTO_TIMING 2 /* chipsel has timing information */ 385 386#define CS_CASLAT_10 0x20 /* upper four bits are the CAS latency */ 387#define CS_CASLAT_15 0x30 /* we selected. bits 7..5 are the */ 388#define CS_CASLAT_20 0x40 /* whole number and bit 4 is the */ 389#define CS_CASLAT_25 0x50 /* fraction. */ 390#define CS_CASLAT_30 0x60 391#define CS_CASLAT_MASK 0xF0 392#define CS_CASLAT_SHIFT 4 393 394typedef struct mcdata_s { /* Information per memory controller */ 395 uint32_t cfgcsint; /* try to interleave this many CS bits */ 396 uint32_t csint; /* # of chip select interleave bits */ 397 uint16_t mintmemclk; /* minimum tMemClk */ 398 uint16_t roundtrip; /* Round trip time from CLK to returned DQS at BCM1250 pin */ 399 uint32_t dramtype; /* DRAM Type */ 400 uint32_t pagepolicy; /* Page policy */ 401 uint32_t blksize; /* Block Size */ 402 uint32_t flags; /* ECC enabled */ 403 uint16_t tCK; /* tCK for manual timing */ 404 uint16_t rfsh; /* refresh rate for manual timing */ 405 uint64_t clkconfig; /* default clock config */ 406 uint64_t mantiming; /* manual timing */ 407 csdata_t csdata[MC_CHIPSELS]; /* Total size: 48 + 16*4 = 112 bytes */ 408} mcdata_t; 409 410typedef struct initdata_s { 411 uint64_t dscr[4]; /* Data Mover descriptor (one cache line)*/ 412 uint32_t flags; /* various flags */ 413 uint32_t inuse; /* indicates MC is in use */ 414 uint32_t pintbit; /* port interleave bit */ 415 uint16_t firstchan; /* first channel */ 416 uint16_t soctype; /* SOC type */ 417 uint64_t ttlbytes; /* total bytes */ 418 mcdata_t mc[MC_CHANNELS]; /* data per memory controller */ 419} initdata_t; /* Total size: 56 + 112*2 = 280 bytes */ 420 421#define M_MCINIT_TRYPINTLV 1 /* Try to do port interleaving */ 422#define M_MCINIT_PINTLV 2 /* Actually do port interleaving */ 423 424 425 426/* ********************************************************************* 427 * Configuration data structure 428 ********************************************************************* */ 429 430#include "sb1250_draminit.h" 431 432/* ********************************************************************* 433 * Initialized data 434 * 435 * WARNING WARNING WARNING! 436 * 437 * This module is *very magical*! We are using the cache as 438 * SRAM, and we're running as relocatable code *before* the code 439 * is relocated and *before* the GP register is set up. 440 * 441 * Therefore, there should be NO data declared in the data 442 * segment - all data must be allocated in the .text segment 443 * and references to this data must be calculated by an inline 444 * assembly stub. 445 * 446 * If you grep the disassembly of this file, you should not see 447 * ANY references to the GP register. 448 ********************************************************************* */ 449 450 451#ifdef _MCSTANDALONE_NOISY_ 452static char *sb1250_rectypes[] = {"MCR_GLOBALS","MCR_CHCFG","MCR_TIMING", 453 "MCR_CLKCFG","MCR_GEOM","MCR_CFG", 454 "MCR_MANTIMING"}; 455#endif 456 457/* ********************************************************************* 458 * Module Description 459 * 460 * This module attempts to initialize the DRAM controllers on 461 * the SB1250. Each DRAM controller can control four chip 462 * selects, or two double-sided DDR SDRAM DIMMs. Therefore, at 463 * most four DIMMs can be attached. 464 * 465 * We will assume that all of the DIMMs are connected to the same 466 * SMBUS serial bus, and are addressed sequentially starting from 467 * module 0. The first two DIMMs will be assigned to memory 468 * controller #0 and the second two DIMMs will be assigned to 469 * memory controller #1. 470 * 471 * There is one serial ROM per DIMM, and we will assume that the 472 * front and back of the DIMM are the same memory configuration. 473 * The first DIMM will be configured for CS0 and CS1, and the 474 * second DIMM will be configured for CS2 and CS3. If the DIMM 475 * has only one side, it will be assigned to CS0 or CS2. 476 * 477 * No interleaving will be configured by this routine, but it 478 * should not be difficult to modify it should that be necessary. 479 * 480 * This entire routine needs to run from registers (no read/write 481 * data is allowed). 482 * 483 * The steps to initialize the DRAM controller are: 484 * 485 * * Read the SPD, verify DDR SDRAMs or FCRAMs 486 * * Obtain #rows, #cols, #banks, and module size 487 * * Calculate row, column, and bank masks 488 * * Calculate chip selects 489 * * Calculate timing register. Note that we assume that 490 * all banks will use the same timing. 491 * * Repeat for each DRAM. 492 * 493 * DIMM0 -> MCTL0 : CS0, CS1 SPD Addr = 0x54 494 * DIMM1 -> MCTL0 : CS2, CS3 SPD Addr = 0x55 495 * DIMM2 -> MCTL1 : CS0, CS1 SPD Addr = 0x56 496 * DIMM3 -> MCTL1 : CS2, CS3 SPD Addr = 0x57 497 * 498 * DRAM Controller registers are programmed in the following order: 499 * 500 * MC_CS_INTERLEAVE 501 * MC_CS_ATTR 502 * MC_TEST_DATA, MC_TEST_ECC 503 * 504 * MC_CSx_ROWS, MC_CSx_COLS 505 * (repeated for each bank) 506 * 507 * MC_CS_START, MC_CS_END 508 * 509 * MC_CLOCK_CFG 510 * (delay) 511 * MC_TIMING 512 * MC_CONFIG 513 * (delay) 514 * MC_DRAMMODE 515 * (delay after each mode setting ??) 516 * 517 * Once the registers are initialized, the DRAM is activated by 518 * sending it the following sequence of commands: 519 * 520 * PRE (precharge) 521 * EMRS (extended mode register set) 522 * MRS (mode register set) 523 * PRE (precharge) 524 * AR (auto-refresh) 525 * AR (auto-refresh again) 526 * MRS (mode register set) 527 * 528 * then wait 200 memory clock cycles without accessing DRAM. 529 * 530 * Following initialization, the ECC bits must be cleared. This 531 * can be accomplished by disabling ECC checking on both memory 532 * controllers, and then zeroing all memory via the mapping 533 * in xkseg. 534 ********************************************************************* */ 535 536/* ********************************************************************* 537 * 538 * Address Bit Assignment Algorithm: 539 * 540 * Good performance can be achieved by taking the following steps 541 * when assigning address bits to the row, column, and interleave 542 * masks. You will need to know the following: 543 * 544 * - The number of rows, columns, and banks on the memory devices 545 * - The block size (larger tends to be better for sequential 546 * access) 547 * - Whether you will interleave chip-selects 548 * - Whether you will be using both memory controllers and want 549 * to interleave between them 550 * 551 * By choosing the masks carefully you can maximize the number of 552 * open SDRAM banks and reduce access times for nearby and sequential 553 * accesses. 554 * 555 * The diagram below depicts a physical address and the order 556 * that the bits should be placed into the masks. Start with the 557 * least significant bit and assign bits to the row, column, bank, 558 * and interleave registers in the following order: 559 * 560 * <------------Physical Address---------------> 561 * Bits: RRRRRRR..R CCCCCCCC..C NN BB P CC xx000 562 * Step: 7 6 5 4 3 2 1 563 * 564 * Where: 565 * R = Row Address Bit (MC_CSX_ROW register) 566 * C = Column Address Bit (MC_CSX_COL register) 567 * N = Chip Select (MC_CS_INTERLEAVE) 568 * (when interleaving via chip selects) 569 * B = Bank Bit (MC_CSX_BA register) 570 * P = Port Select bit (MC_CONFIG register) 571 * (when interleaving memory channels) 572 * x = Does not matter (MC_CSX_COL register) 573 * (internally driven by controller) 574 * 0 = must be zero 575 * 576 * When an address bit is "assigned" it is set in one of the masks 577 * in the MC_CSX_ROW, MC_CSX_COL, MC_CSX_BA, or MC_CS_INTERLEAVE 578 * registers. 579 * 580 * 581 * 1. The bottom 3 bits are ignored and should be set to zero. 582 * The next two bits are also ignored, but are considered 583 * to be column bits, so they should be taken from the 584 * total column bits supported by the device. 585 * 586 * 2. The next two bits are used for column interleave. For 587 * 32-byte blocks (and no column interleave), do not use 588 * any column bits. For 64-byte blocks, use one column 589 * bit, and for 128 byte blocks, use two column bits. Subtract 590 * the column bits assigned in this step from the total. 591 * 592 * 3. If you are using both memory controllers and wish to interleave 593 * between them, assign one bit for the controller interleave. The 594 * bit number is assigned in the MC_CONFIG register. 595 * 596 * 4. These bits represent the bank bits on the memory device. 597 * If the device has 4 banks, assign 2 bits in the MC_CSX_BA 598 * register. 599 * 600 * 5. If you are interleaving via chip-selects, set one or two 601 * bits in the MC_CS_INTERLEAVE register for the bits that will 602 * be interleaved. 603 * 604 * 6. The remaining column bits are assigned in the MC_CSX_COL 605 * register. 606 * 607 * 7. The row bits are assigned in the MC_CSX_ROW register. 608 * 609 ********************************************************************* */ 610 611 612 613/* ********************************************************************* 614 * sb1250_find_timingcs(mc) 615 * 616 * For a given memory controller, choose the chip select whose 617 * timing values will be used to base the TIMING and MCLOCK_CFG 618 * registers on. 619 * 620 * Input parameters: 621 * mc - memory controller 622 * 623 * Return value: 624 * chip select index, or -1 if no active chip selects. 625 ********************************************************************* */ 626 627 628static int sb1250_find_timingcs(mcdata_t *mc) 629{ 630 int idx; 631 632 /* for now, the first one with data is the one we pick */ 633 634 for (idx = 0; idx < MC_CHIPSELS; idx++) { 635 if (mc->csdata[idx].flags & CS_PRESENT) return idx; 636 } 637 638 return -1; 639} 640 641/* ********************************************************************* 642 * sb1250_auto_timing(mcidx,tdata) 643 * 644 * Program the memory controller's timing registers based on the 645 * timing information stored with the chip select data. For DIMMs 646 * this information comes from the SPDs, otherwise it was entered 647 * from the datasheets into the tables in the init modules. 648 * 649 * Input parameters: 650 * mcidx - memory controller index (0 or 1) 651 * tdata - a chip select data (csdata_t) 652 * 653 * Return value: 654 * nothing 655 ********************************************************************* */ 656 657static void sb1250_auto_timing(int mcidx,mcdata_t *mc,csdata_t *tdata) 658{ 659 unsigned int res; 660 661 unsigned int plldiv; 662 unsigned int clk_ratio; 663 unsigned int refrate; 664 unsigned int ref_freq; 665 unsigned int caslatency; 666 667 unsigned int spd_tCK_25; 668 unsigned int spd_tCK_20; 669 unsigned int spd_tCK_10; 670 unsigned int tCpuClk; 671 unsigned int tMemClk; 672 673 unsigned int w2rIdle,r2wIdle,r2rIdle; 674 unsigned int tCrD,tCrDh,tFIFO; 675 unsigned int tCwD; 676 unsigned int tRAS; 677 unsigned int tRP,tRRD,tRCD,tRCw,tRCr,tCwCr,tRFC; 678 679 uint64_t timing1; 680 uint64_t mclkcfg; 681 sbport_t base; 682 uint64_t sysrev; 683 684 /* Timing window variables */ 685 686 int addrSkew,dqiSkew,dqoSkew,clkDrive; 687 int n01_open,n02_open,n12_open; 688 int n01_close,n02_close,n12_close; 689 int dqsArrival; 690 int addrAdjust,dqiAdjust,dqoAdjust; 691 int minDqsMargin; 692 int dllScaleNum,dllScaleDenom,dllOffset; 693 694 695 /* 696 * We need our cpu clock for all sorts of things. 697 */ 698 699 sysrev = READCSR(PHYS_TO_K1(A_SCD_SYSTEM_REVISION)); 700#if defined(_VERILOG_) || defined(_FUNCSIM_) 701 plldiv = 16; /* 800MHz CPU for RTL simulation */ 702#else 703 plldiv = G_SYS_PLL_DIV(READCSR(PHYS_TO_K1(A_SCD_SYSTEM_CFG))); 704#endif 705 if (plldiv == 0) { 706 plldiv = 6; 707 } 708 709 /* 710 * Compute tCpuClk, in picoseconds to avoid rounding errors. 711 * 712 * Calculation: 713 * tCpuClk = 1/fCpuClk 714 * = 1/(100MHz * plldiv/2) 715 * = 2/(100MHz*plldiv) 716 * = 2/(100*plldiv) us 717 * = 20/plldiv ns 718 * = 2000000/plldiv 10ths of ns 719 * 720 * If SB1250_REFCLK is in MHz, then: 721 * 2/(SB1250_REFCLK*plldiv) us 722 * = 2000/(SB1250_REFCLK*plldiv) ns 723 * = 2000000/(SB1250_REFCLK*plldiv) ps 724 * 725 * However, we want to round the result to the nearest integer, 726 * so we double the numerator (to 4000000) to get one more bit 727 * of precision in the quotient, then add one and scale it back down 728 */ 729 730 /* tCpuClk is in picoseconds */ 731 tCpuClk = ((4000000/(SB1250_REFCLK*plldiv))+1)/2; 732 733 spd_tCK_25 = DECTO10THS(tdata->spd_tCK_25); 734 spd_tCK_20 = DECTO10THS(tdata->spd_tCK_20); 735 spd_tCK_10 = DECTO10THS(tdata->spd_tCK_10); 736 737 /* 738 * Compute the target tMemClk, in units of tenths of nanoseconds 739 * to be similar to the JEDEC SPD values. This will be 740 * 741 * MAX(MIN_tMEMCLK,spd_tCK_25) 742 */ 743 744 tMemClk = spd_tCK_25; 745 if (mc->mintmemclk > tMemClk) tMemClk = mc->mintmemclk; 746 747 /* 748 * Now compute our clock ratio (the amount we'll divide tCpuClk by 749 * to get as close as possible to tMemClk without exceeding it 750 * 751 * It's (tMemClk*100) here because tCpuClk is in picoseconds 752 */ 753 754 clk_ratio = ((tMemClk*100) + tCpuClk - 1) / tCpuClk; 755 if (clk_ratio < 4) clk_ratio = 4; 756 if (clk_ratio > 9) clk_ratio = 9; 757 758 /* 759 * BCM112x A1 parts do not function properly with MC ratio 5. 760 * (This is fixed in A2 parts.) On BCM112x before A2, When 761 * that ratio would be used, back off to 6. 762 */ 763 if ((SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1120 || 764 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125 || 765 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125H) && 766 G_SYS_REVISION(sysrev) < K_SYS_REVISION_BCM112x_A2 && 767 clk_ratio == 5) { 768 clk_ratio = 6; 769 } 770 771 /* 772 * Now, recompute tMemClk using the new clk_ratio. This gives us 773 * the actual tMemClk that the memory controller will generate 774 * 775 * Calculation: 776 * fMemClk = SB1250_REFCLK * plldiv / (2 * clk_ratio) Mhz 777 * 778 * tMemClk = 1/fMemClk us 779 * = (2 * clk_ratio) / (SB1250_REFCLK * plldiv) us 780 * = 10000 * (2 * clk_ratio) / (SB1250_REFCLK * plldiv) 0.1ns 781 * 782 * The resulting tMemClk is in tenths of nanoseconds so we 783 * can compare it with the SPD values. The x10000 converts 784 * us to 0.1ns 785 */ 786 787 tMemClk = (10000 * 2 * clk_ratio)/(SB1250_REFCLK * plldiv); 788 789 /* Calculate the refresh rate */ 790 791 switch (tdata->spd_rfsh & JEDEC_RFSH_MASK) { 792 case JEDEC_RFSH_64khz: ref_freq = 64; break; 793 case JEDEC_RFSH_256khz: ref_freq = 256; break; 794 case JEDEC_RFSH_128khz: ref_freq = 128; break; 795 case JEDEC_RFSH_32khz: ref_freq = 32; break; 796 case JEDEC_RFSH_8khz: ref_freq = 16; break; 797 default: ref_freq = 8; break; 798 } 799 800 /* 801 * Compute the target refresh value, in Khz/16. We know 802 * the rate that the DIMMs expect (in Khz, above). So we need 803 * to calculate what the MemClk is divided by to get that value. 804 * There is an internal divide-by-16 in the 1250 in the refresh 805 * generation. 806 * 807 * Calculation: 808 * refrate = (plldiv/2)*SB1250_REFCLK*1000 Khz /(ref_freq*16*clk_ratio) 809 */ 810 811 refrate = ((plldiv * SB1250_REFCLK * 1000 / 2) / (ref_freq*16*clk_ratio)) - 1; 812 813 /* 814 * Calculate CAS Latency in half cycles. The low bit indicates 815 * half a cycle, so 2 (0010) = 1 cycle and 3 (0011) = 1.5 cycles 816 */ 817 818 res = tdata->spd_caslatency; 819 if (res & JEDEC_CASLAT_35) caslatency = (3 << 1) + 1; /* 3.5 */ 820 else if (res & JEDEC_CASLAT_30) caslatency = (3 << 1); /* 3.0 */ 821 else if (res & JEDEC_CASLAT_25) caslatency = (2 << 1) + 1; /* 2.5 */ 822 else if (res & JEDEC_CASLAT_20) caslatency = (2 << 1); /* 2.0 */ 823 else if (res & JEDEC_CASLAT_15) caslatency = (1 << 1) + 1; /* 1.5 */ 824 else caslatency = (1 << 1); /* 1.0 */ 825 826 if ((spd_tCK_10 != 0) && (spd_tCK_10 <= tMemClk)) { 827 caslatency -= (1 << 1); /* subtract 1.0 */ 828 } 829 else if ((spd_tCK_20 != 0) && (spd_tCK_20 <= tMemClk)) { 830 caslatency -= 1; /* subtract 0.5 */ 831 } 832 833 /* 834 * Store the CAS latency in the chip select info 835 */ 836 837 tdata->flags &= ~CS_CASLAT_MASK; 838 tdata->flags |= (((caslatency << CS_CASLAT_SHIFT)) & CS_CASLAT_MASK); 839#ifdef _MCSTANDALONE_ 840 dram_cas_latency = caslatency; 841 dram_tMemClk = tMemClk; 842#endif 843 844 /* 845 * Now, on to the timing parameters. 846 */ 847 848 w2rIdle = 1; /* Needs to be set on all parts. */ 849 r2rIdle = 0; 850 851 /* ======================================================================== */ 852 853 /* 854 * New "Window" calculations 855 */ 856 857 n01_open = -SB1250_WINDOW_OPEN_OFFSET; 858 n02_open = -SB1250_WINDOW_OPEN_OFFSET; 859 n12_open = tMemClk/2 - SB1250_WINDOW_OPEN_OFFSET; 860 n01_close = tMemClk - SB1250_CLOSE_01_OFFSET; 861 n02_close = 3*tMemClk/2 - SB1250_CLOSE_02_OFFSET; 862 n12_close = 7*tMemClk/4 - SB1250_CLOSE_12_OFFSET; 863 minDqsMargin = SB1250_MIN_DQS_MARGIN; 864 865 if (SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250 && 866 G_SYS_REVISION(sysrev) >= K_SYS_REVISION_PASS1 && 867 G_SYS_REVISION(sysrev) < K_SYS_REVISION_PASS2) { 868 /* pass1 bcm1250 */ 869 dllScaleNum = PASS1_DLL_SCALE_NUMERATOR; 870 dllScaleDenom = PASS1_DLL_SCALE_DENOMINATOR; 871 dllOffset = PASS1_DLL_OFFSET; 872 } 873 else { 874 /* pass2+ BCM1250, or BCM112x */ 875 dllScaleNum = PASS2_DLL_SCALE_NUMERATOR; 876 dllScaleDenom = PASS2_DLL_SCALE_DENOMINATOR; 877 dllOffset = PASS2_DLL_OFFSET; 878 } 879 880 881 /* 882 * Get fields out of the clock config register 883 */ 884 885 dqiSkew = (int) G_MC_DQI_SKEW(mc->clkconfig); 886 dqoSkew = (int) G_MC_DQO_SKEW(mc->clkconfig); 887 addrSkew = (int) G_MC_ADDR_SKEW(mc->clkconfig); 888 clkDrive = (int) G_MC_CLOCK_DRIVE(mc->clkconfig); 889 890 /* 891 * get initial values for tCrD and dqsArrival 892 */ 893 894 tCrD = (caslatency >> 1); 895 dqsArrival = mc->roundtrip; 896 if (caslatency & 1) { 897 dqsArrival += tMemClk/2; 898 } 899 900 /* 901 * need to adjust for settings of skew values. 902 * can either add to dqsArrival or subtract from 903 * all the windows. 904 */ 905 906 addrAdjust = (addrSkew - 8) * ((int)tMemClk * dllScaleNum - dllOffset) / (8 * dllScaleDenom); 907 dqiAdjust = (dqiSkew - 8) * ((int)tMemClk * dllScaleNum - dllOffset) / (8 * dllScaleDenom); 908 dqsArrival += addrAdjust + dqiAdjust; 909 910 /* for pass 2, dqoAdjust applies only to n12_Close */ 911 dqoAdjust = (dqoSkew - 8) * (tMemClk * dllScaleNum - dllOffset) / (8 * dllScaleDenom); 912 n12_close += dqoAdjust; 913 914 /* 915 * adjust window for clock drive strength 916 * Don't be tempted to turn this into an array. It will break the 917 * relocation stuff! 918 */ 919 switch (clkDrive) { 920 case 0: dqsArrival += 10; break; 921 case 1: dqsArrival += 4; break; 922 case 2: dqsArrival += 3; break; 923 case 3: dqsArrival += 2; break; 924 case 4: dqsArrival += 2; break; 925 case 5: dqsArrival += 1; break; 926 case 6: dqsArrival += 1; break; 927 case 7: dqsArrival += 1; break; 928 case 8: dqsArrival += 8; break; 929 case 9: dqsArrival += 2; break; 930 case 0xa: dqsArrival += 1; break; 931 case 0xb: break; 932 case 0xc: break; 933 case 0xd: break; 934 case 0xe: break; 935 case 0xf: break; 936 default: 937 /* shouldn't get here */ 938 break; 939 } 940 941 while ((n02_close - dqsArrival < minDqsMargin) && 942 (n12_close - dqsArrival < minDqsMargin)) { 943 /* very late DQS arrival; shift latency by one tick */ 944#ifdef _MCSTANDALONE_NOISY_ 945 printf("DRAM: Very late DQS arrival, shift latency one tick\n"); 946#endif 947 ++tCrD; 948 dqsArrival -= tMemClk; 949 } 950 951 if ((dqsArrival - n01_open >= minDqsMargin) && 952 (n01_close - dqsArrival >= minDqsMargin)) { 953 /* use n,0,1 */ 954 tCrDh = 0; 955 tFIFO = 1; 956#ifdef _MCSTANDALONE_NOISY_ 957 printf("DRAM: DQS arrival in n,0,1 window\n"); 958#endif 959 } 960 else if ((dqsArrival - n02_open >= minDqsMargin) && 961 (n02_close - dqsArrival >= minDqsMargin)) { 962 /* use n,0,2 */ 963 tCrDh = 0; 964 tFIFO = 2; 965#ifdef _MCSTANDALONE_NOISY_ 966 printf("DRAM: DQS arrival in n,0,2 window\n"); 967#endif 968 } 969 else if ((dqsArrival - n12_open >= minDqsMargin) && 970 (n12_close - dqsArrival >= minDqsMargin)) { 971 /* use n,1,2 */ 972 tCrDh = 1; 973 tFIFO = 2; 974#ifdef _MCSTANDALONE_NOISY_ 975 printf("DRAM: DQS arrival in n,1,2 window\n"); 976#endif 977 } 978 else { 979 /* 980 * minDqsMargin is probably set too high 981 * try using n,0,2 982 */ 983 tCrDh = 0; 984 tFIFO = 2; 985#ifdef _MCSTANDALONE_NOISY_ 986 printf("DRAM: Default: DQS arrival in n,0,2 window\n"); 987#endif 988 } 989 990 r2wIdle = ((tMemClk - dqsArrival) < SB1250_MIN_R2W_TIME); 991 992 /* 993 * Pass1 BCM112x parts do not function properly with 994 * M_MC_r2wIDLE_TWOCYCLES clear, so we set r2wIdle here for them 995 * so that that flag will be set later. 996 */ 997 if ((SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1120 || 998 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125 || 999 SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1125H) && 1000 1 /* XXXCGD: When fixed, check revision! */) { 1001 r2wIdle = 1; 1002 } 1003 1004 /* 1005 * Above stuff just calculated tCrDh, tCrD, and tFIFO 1006 */ 1007 1008 /* ======================================================================== */ 1009 1010 /* Recompute tMemClk as a fixed-point 6.2 value */ 1011 1012 tMemClk = (4000 * 2 * clk_ratio) / (SB1250_REFCLK * plldiv); 1013 1014 tRAS = ( ((unsigned int)(tdata->spd_tRAS))*4 + tMemClk-1) / tMemClk; 1015 1016 tRP = ( ((unsigned int)(tdata->spd_tRP)) + tMemClk-1) / tMemClk; 1017 tRRD = ( ((unsigned int)(tdata->spd_tRRD)) + tMemClk-1) / tMemClk; 1018 tRCD = ( ((unsigned int)(tdata->spd_tRCD)) + tMemClk-1) / tMemClk; 1019 1020 /* 1021 * Check for registered DIMMs, or if we are "forcing" registered 1022 * DIMMs, as might be the case of regular unregistered DIMMs 1023 * behind an external register. 1024 */ 1025 1026 switch (mc->dramtype) { 1027 case FCRAM: 1028 /* For FCRAMs, tCwD is always caslatency - 1 */ 1029 tCwD = (caslatency >> 1) - 1; 1030 tRCD = 1; /* always 1 for FCRAM */ 1031 tRP = 1; /* always 1 for FCRAM */ 1032 break; 1033 default: 1034 /* Otherwise calculate based on registered attribute */ 1035 if ((tdata->spd_attributes & JEDEC_ATTRIB_REG) || 1036 (mc->flags & MCFLG_FORCEREG)) { /* registered DIMM */ 1037 tCwD = 2; 1038 tCrD++; 1039 } 1040 else { /* standard unbuffered DIMM */ 1041 tCwD = 1; 1042 } 1043 break; 1044 } 1045 1046 /* 1047 * Calculate the rest of the timing parameters based on above values. 1048 */ 1049 1050 if (tdata->spd_tRFC == 0) { 1051 tRFC = 1 + tRP + tRAS; 1052 } 1053 else { 1054 tRFC = ( ((unsigned int) tdata->spd_tRFC)*4 + tMemClk-1) / tMemClk; 1055 } 1056 1057 if (tRFC > 15) tRFC = 15; 1058 1059 if (tdata->spd_tRC == 0) { 1060 tRCw = (tRAS + tRP + 2) - 1; 1061 tRCr = (tRAS + tRP) - 1; 1062 } 1063 else { 1064 tRCw = ( (((unsigned int)(tdata->spd_tRC))*4 + tMemClk-1) / tMemClk) + 2 - 1; 1065 tRCr = ( (((unsigned int)(tdata->spd_tRC))*4 + tMemClk-1) / tMemClk) - 1; 1066 } 1067 1068 tCwCr = tRCw + 1 - (tRCD + tCwD + 2 + 1); 1069 1070 /* 1071 * Finally, put it all together in the timing register. 1072 */ 1073 1074 1075 timing1 = V_MC_tRCD(tRCD) | 1076 V_MC_tCrD(tCrD) | 1077 (tCrDh ? M_tCrDh : 0) | 1078 V_MC_tRP(tRP) | 1079 V_MC_tRRD(tRRD) | 1080 V_MC_tRCw(tRCw) | 1081 V_MC_tRCr(tRCr) | 1082 V_MC_tCwCr(tCwCr) | 1083 V_MC_tRFC(tRFC) | 1084 V_MC_tFIFO(tFIFO) | 1085 V_MC_tCwD(tCwD) | 1086 (w2rIdle ? M_MC_w2rIDLE_TWOCYCLES : 0) | 1087 (r2wIdle ? M_MC_r2wIDLE_TWOCYCLES : 0) | 1088 (r2rIdle ? M_MC_r2rIDLE_TWOCYCLES : 0); 1089 1090 mclkcfg = V_MC_CLK_RATIO(clk_ratio) | 1091 V_MC_REF_RATE(refrate); 1092 1093 /* Merge in drive strengths from the MC structure */ 1094 mclkcfg |= mc->clkconfig; 1095 1096 base = PHYS_TO_K1(A_MC_BASE(mcidx)); 1097 WRITECSR(base+R_MC_TIMING1,timing1); 1098 1099#ifdef _VERILOG_ 1100 /* Smash in some defaults for Verilog simulation */ 1101 mclkcfg &= ~(M_MC_CLK_RATIO | M_MC_DLL_DEFAULT | M_MC_REF_RATE); 1102 mclkcfg |= V_MC_CLK_RATIO_3X | V_MC_REF_RATE(K_MC_REF_RATE_200MHz) | 1103 V_MC_DLL_DEFAULT(0x18); 1104#endif 1105 1106 WRITECSR(base+R_MC_MCLK_CFG,mclkcfg); 1107 1108} 1109 1110 1111/* ********************************************************************* 1112 * SB1250_MANUAL_TIMING(mcidx,mc) 1113 * 1114 * Program the timing registers, for the case of user-specified 1115 * timing parameters (don't calculate values based on datasheet 1116 * values, just stuff the info into the MC registers) 1117 * 1118 * Input parameters: 1119 * mcidx - memory controller index 1120 * mc - memory controller data 1121 * 1122 * Return value: 1123 * nothing 1124 ********************************************************************* */ 1125 1126static void sb1250_manual_timing(int mcidx,mcdata_t *mc) 1127{ 1128 unsigned int plldiv; 1129 unsigned int clk_ratio; 1130 unsigned int refrate; 1131 unsigned int ref_freq; 1132 unsigned int tCpuClk; 1133 unsigned int tMemClk; 1134 1135 uint64_t timing1; 1136 uint64_t mclkcfg; 1137 1138 sbport_t base; 1139 1140 /* 1141 * We need our cpu clock for all sorts of things. 1142 */ 1143 1144#if defined(_VERILOG_) || defined(_FUNCSIM_) 1145 plldiv = 16; /* 800MHz CPU for RTL simulation */ 1146#else 1147 plldiv = G_SYS_PLL_DIV(READCSR(PHYS_TO_K1(A_SCD_SYSTEM_CFG))); 1148#endif 1149 if (plldiv == 0) { 1150 plldiv = 6; 1151 } 1152 1153 /* See comments in auto_timing for details */ 1154 tCpuClk = 2000000/(SB1250_REFCLK*plldiv); /* tCpuClk is in picoseconds */ 1155 1156 /* Compute MAX(MIN_tMEMCLK,spd_tCK_25) */ 1157 tMemClk = DECTO10THS(mc->tCK); 1158 if (mc->mintmemclk > tMemClk) tMemClk = mc->mintmemclk; 1159 1160 clk_ratio = ((tMemClk*100) + tCpuClk - 1) / tCpuClk; 1161 if (clk_ratio < 4) clk_ratio = 4; 1162 if (clk_ratio > 9) clk_ratio = 9; 1163 1164 /* recompute tMemClk using the new clk_ratio */ 1165 1166 tMemClk = (10000 * 2 * clk_ratio)/(SB1250_REFCLK * plldiv); 1167 1168 /* Calculate the refresh rate */ 1169 1170 switch (mc->rfsh & JEDEC_RFSH_MASK) { 1171 case JEDEC_RFSH_64khz: ref_freq = 64; break; 1172 case JEDEC_RFSH_256khz: ref_freq = 256; break; 1173 case JEDEC_RFSH_128khz: ref_freq = 128; break; 1174 case JEDEC_RFSH_32khz: ref_freq = 32; break; 1175 case JEDEC_RFSH_8khz: ref_freq = 16; break; 1176 default: ref_freq = 8; break; 1177 } 1178 1179 refrate = ((plldiv * SB1250_REFCLK * 1000 / 2) / (ref_freq*16*clk_ratio)) - 1; 1180 1181 timing1 = mc->mantiming; 1182 mclkcfg = V_MC_CLK_RATIO(clk_ratio) | 1183 V_MC_REF_RATE(refrate); 1184 1185 /* Merge in drive strengths from the MC structure */ 1186 mclkcfg |= mc->clkconfig; 1187 1188 base = PHYS_TO_K1(A_MC_BASE(mcidx)); 1189 WRITECSR(base+R_MC_TIMING1,timing1); 1190 1191#ifdef _VERILOG_ 1192 /* Smash in some defaults for Verilog simulation */ 1193 mclkcfg &= ~(M_MC_CLK_RATIO | M_MC_DLL_DEFAULT | M_MC_REF_RATE); 1194 mclkcfg |= V_MC_CLK_RATIO_3X | V_MC_REF_RATE(K_MC_REF_RATE_200MHz) | 1195 V_MC_DLL_DEFAULT(0x18); 1196#endif 1197 1198 WRITECSR(base+R_MC_MCLK_CFG,mclkcfg); 1199 1200} 1201 1202 1203 1204/* ********************************************************************* 1205 * Default DRAM init table 1206 * 1207 * This is just here to make SB1250 BSPs easier to write. 1208 * If you've hooked up standard JEDEC SDRAMs in a standard 1209 * way with all your SPD ROMs on one SMBus channel, 1210 * This table is for you. 1211 * 1212 * Otherwise, copy it into your board_init.S file and 1213 * modify it, and return a pointer to the table from 1214 * the board_draminfo routine. 1215 * 1216 * (See the CFE manual for more details) 1217 ********************************************************************* */ 1218 1219#if !defined(_MCSTANDALONE_) /* no tables in the non-CFE, non-MIPS version */ 1220 1221#ifdef _VERILOG_ 1222static const mc_initrec_t draminittab_11xx[5] __attribute__ ((section(".text"))) = { 1223 1224 /* 1225 * Globals: No interleaving 1226 */ 1227 1228 DRAM_GLOBALS(MC_NOPORTINTLV), 1229 1230 /* 1231 * Memory channel 0: manually configure for verilog runs 1232 * Configure chip select 0. 1233 */ 1234 1235 DRAM_CHAN_CFG(MC_CHAN0, 80, JEDEC, CASCHECK, BLKSIZE32, NOCSINTLV, ECCDISABLE, 0), 1236 1237 DRAM_CS_GEOM(MC_CS0, 12, 8, 2), 1238 DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0, 45, DRT4(20,0), DRT4(15,0), DRT4(20,0), 0, 0), 1239 1240 DRAM_EOT 1241}; 1242 1243static const mc_initrec_t draminittab_12xx[5] __attribute__ ((section(".text"))) = { 1244 1245 /* 1246 * Globals: No interleaving 1247 */ 1248 1249 DRAM_GLOBALS(MC_NOPORTINTLV), 1250 1251 /* 1252 * Memory channel 0: manually configure for verilog runs 1253 * Configure chip select 0. 1254 */ 1255 1256 DRAM_CHAN_CFG(MC_CHAN0, 80, JEDEC, CASCHECK, BLKSIZE32, NOCSINTLV, ECCDISABLE, 0), 1257 1258 DRAM_CS_GEOM(MC_CS0, 12, 8, 2), 1259 DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0, 45, DRT4(20,0), DRT4(15,0), DRT4(20,0), 0, 0), 1260 1261 DRAM_EOT 1262}; 1263 1264 1265#else 1266#define DEVADDR (CFG_DRAM_SMBUS_BASE) 1267#define DEFCHAN (CFG_DRAM_SMBUS_CHANNEL) 1268static const mc_initrec_t draminittab_12xx[8] __attribute__ ((section(".text"))) = { 1269 1270 /* 1271 * Global data: Interleave mode from bsp_config.h 1272 */ 1273 1274 DRAM_GLOBALS(CFG_DRAM_INTERLEAVE), /* do port interleaving if possible */ 1275 1276 /* 1277 * Memory channel 0: Configure via SMBUS, Automatic Timing 1278 * Assumes SMBus device numbers are arranged such 1279 * that the first two addresses are CS0,1 and CS2,3 on MC0 1280 * and the second two addresses are CS0,1 and CS2,3 on MC1 1281 */ 1282 1283 DRAM_CHAN_CFG(MC_CHAN0, CFG_DRAM_MIN_tMEMCLK, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0), 1284 1285 DRAM_CS_SPD(MC_CS0, 0, DEFCHAN, DEVADDR+0), 1286 DRAM_CS_SPD(MC_CS2, 0, DEFCHAN, DEVADDR+1), 1287 1288 /* 1289 * Memory channel 1: Configure via SMBUS 1290 */ 1291 1292 DRAM_CHAN_CFG(MC_CHAN1, CFG_DRAM_MIN_tMEMCLK, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0), 1293 1294 DRAM_CS_SPD(MC_CS0, 0, DEFCHAN, DEVADDR+2), 1295 DRAM_CS_SPD(MC_CS2, 0, DEFCHAN, DEVADDR+3), 1296 1297 /* 1298 * End of Table 1299 */ 1300 1301 DRAM_EOT 1302 1303}; 1304 1305static const mc_initrec_t draminittab_11xx[5] __attribute__ ((section(".text"))) = { 1306 1307 /* 1308 * Global data: Interleave mode from bsp_config.h 1309 */ 1310 1311 DRAM_GLOBALS(0), /* no port interleaving on 11xx */ 1312 1313 /* 1314 * Memory channel 1: Configure via SMBUS 1315 */ 1316 1317 DRAM_CHAN_CFG(MC_CHAN1, CFG_DRAM_MIN_tMEMCLK, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0), 1318 1319 DRAM_CS_SPD(MC_CS0, 0, DEFCHAN, DEVADDR+0), 1320 DRAM_CS_SPD(MC_CS2, 0, DEFCHAN, DEVADDR+1), 1321 1322 /* 1323 * End of Table 1324 */ 1325 1326 DRAM_EOT 1327 1328}; 1329#endif 1330 1331#endif 1332 1333 1334/* ********************************************************************* 1335 * SB1250_SMBUS_INIT() 1336 * 1337 * Initialize SMBUS channel 1338 * 1339 * Input parameters: 1340 * chan - SMBus channel number, 0 or 1 1341 * 1342 * Return value: 1343 * smbus_base - KSEG1 address of SMBus channel 1344 * 1345 * Registers used: 1346 * tmp0 1347 ********************************************************************* */ 1348 1349static sbport_t sb1250_smbus_init(int chan) 1350{ 1351 sbport_t base; 1352 1353 base = PHYS_TO_K1(A_SMB_BASE(chan)); 1354 1355 WRITECSR(base+R_SMB_FREQ,K_SMB_FREQ_100KHZ); 1356 WRITECSR(base+R_SMB_CONTROL,0); 1357 1358 return base; 1359} 1360 1361 1362/* ********************************************************************* 1363 * SB1250_SMBUS_WAITREADY() 1364 * 1365 * Wait for SMBUS channel to be ready. 1366 * 1367 * Input parameters: 1368 * smbus_base - SMBus channel base (K1seg addr) 1369 * 1370 * Return value: 1371 * ret0 - 0 if no error occured, else -1 1372 * 1373 * Registers used: 1374 * tmp0,tmp1 1375 ********************************************************************* */ 1376 1377static int sb1250_smbus_waitready(sbport_t base) 1378{ 1379 uint64_t status; 1380 1381 /* 1382 * Wait for busy bit to clear 1383 */ 1384 1385 for (;;) { 1386 status = READCSR(base+R_SMB_STATUS); 1387 if (!(status & M_SMB_BUSY)) break; 1388 } 1389 1390 /* 1391 * Isolate error bit and clear error status 1392 */ 1393 1394 status &= M_SMB_ERROR; 1395 WRITECSR(base+R_SMB_STATUS,status); 1396 1397 /* 1398 * Return status 1399 */ 1400 1401 return (status) ? -1 : 0; 1402} 1403 1404 1405 1406/* ********************************************************************* 1407 * SB1250_SMBUS_READBYTE() 1408 * 1409 * Read a byte from a serial ROM attached to an SMBus channel 1410 * 1411 * Input parameters: 1412 * base - SMBus channel base address (K1seg addr) 1413 * dev - address of device on SMBUS 1414 * offset - address of byte within device on SMBUS 1415 * 1416 * Return value: 1417 * byte from device (-1 indicates an error) 1418 ********************************************************************* */ 1419 1420 1421static int sb1250_smbus_readbyte(sbport_t base,unsigned int dev,unsigned int offset) 1422{ 1423 int res; 1424 1425 /* 1426 * Wait for channel to be ready 1427 */ 1428 1429 res = sb1250_smbus_waitready(base); 1430 if (res < 0) return res; 1431 1432 /* 1433 * Set up a READ BYTE command. This command has no associated 1434 * data field, the command code is the data 1435 */ 1436 1437 WRITECSR(base+R_SMB_CMD,offset); 1438 WRITECSR(base+R_SMB_START,dev | V_SMB_TT(K_SMB_TT_CMD_RD1BYTE)); 1439 1440 /* 1441 * Wait for the command to complete 1442 */ 1443 1444 res = sb1250_smbus_waitready(base); 1445 if (res < 0) return res; 1446 1447 /* 1448 * Return the data byte 1449 */ 1450 1451 return (int) ((READCSR(base+R_SMB_DATA)) & 0xFF); 1452} 1453 1454 1455/* ********************************************************************* 1456 * SB1250_DRAM_GETINFO 1457 * 1458 * Process a single init table entry and move data into the 1459 * memory controller's data structure. 1460 * 1461 * Input parameters: 1462 * smbase - points to base of SMbus device to read from 1463 * mc - memory controller data 1464 * init - pointer to current user init table entry 1465 * 1466 * Return value: 1467 * nothing 1468 ********************************************************************* */ 1469 1470static void sb1250_dram_getinfo(unsigned int smbchan, 1471 unsigned int smbdev, 1472 mcdata_t *mc, 1473 int chipsel) 1474 1475{ 1476 int res; 1477 unsigned char spd[JEDEC_SPD_MAX]; 1478 int idx; 1479 csdata_t *cs = &(mc->csdata[chipsel]); 1480 sbport_t smbase; 1481 1482 smbase = sb1250_smbus_init(smbchan); 1483 1484 /* 1485 * Read just the memory type to see if the RAM is present. 1486 */ 1487 1488 res = sb1250_smbus_readbyte(smbase,smbdev,JEDEC_SPD_MEMTYPE); 1489 1490 if ((res < 0) || ((res != JEDEC_MEMTYPE_DDRSDRAM) && 1491 (res != JEDEC_MEMTYPE_DDRSDRAM2) && 1492 (res != SPD_MEMTYPE_FCRAM))) { 1493 return; /* invalid or no memory installed */ 1494 } 1495 1496 /* 1497 * Now go back and read everything. 1498 */ 1499 1500 res = 0; 1501 for (idx = 0; idx < JEDEC_SPD_MAX; idx++) { 1502 res = sb1250_smbus_readbyte(smbase,smbdev,idx); 1503 if (res < 0) break; 1504 spd[idx] = res; 1505 } 1506 1507 if (res < 0) return; /* some SMBus error */ 1508 1509 1510 cs->rows = spd[JEDEC_SPD_ROWS]; 1511 cs->cols = spd[JEDEC_SPD_COLS]; 1512 1513 /* 1514 * Determine how many bits the banks represent. Unlike 1515 * the rows/columns, the bank byte says how *many* banks 1516 * there are, not how many bits represent banks 1517 */ 1518 1519 switch (spd[JEDEC_SPD_BANKS]) { 1520 case 2: /* 2 banks = 1 bits */ 1521 cs->banks = 1; 1522 break; 1523 1524 case 4: /* 4 banks = 2 bits */ 1525 cs->banks = 2; 1526 break; 1527 1528 case 8: /* 8 banks = 3 bits */ 1529 cs->banks = 3; 1530 break; 1531 1532 case 16: /* 16 banks = 4 bits */ 1533 cs->banks = 4; 1534 break; 1535 1536 default: /* invalid bank count */ 1537 return; 1538 } 1539 1540 1541 /* 1542 * Read timing parameters from the DIMM. By this time we kind of trust 1543 */ 1544 1545 cs->spd_dramtype = spd[JEDEC_SPD_MEMTYPE]; 1546 cs->spd_tCK_25 = spd[JEDEC_SPD_tCK25]; 1547 cs->spd_tCK_20 = spd[JEDEC_SPD_tCK20]; 1548 cs->spd_tCK_10 = spd[JEDEC_SPD_tCK10]; 1549 cs->spd_rfsh = spd[JEDEC_SPD_RFSH]; 1550 cs->spd_caslatency = spd[JEDEC_SPD_CASLATENCIES]; 1551 cs->spd_attributes = spd[JEDEC_SPD_ATTRIBUTES]; 1552 cs->spd_tRAS = spd[JEDEC_SPD_tRAS]; 1553 cs->spd_tRP = spd[JEDEC_SPD_tRP]; 1554 cs->spd_tRRD = spd[JEDEC_SPD_tRRD]; 1555 cs->spd_tRCD = spd[JEDEC_SPD_tRCD]; 1556 cs->spd_tRFC = spd[JEDEC_SPD_tRFC]; 1557 cs->spd_tRC = spd[JEDEC_SPD_tRC]; 1558 1559 /* 1560 * Okay, we got all the required data. mark this CS present. 1561 */ 1562 1563 cs->flags = CS_PRESENT | CS_AUTO_TIMING; 1564 1565 /* 1566 * If the module width is not 72 for any DIMM, disable ECC for this 1567 * channel. All DIMMs must support ECC for us to enable it. 1568 */ 1569 1570 if (spd[JEDEC_SPD_WIDTH] != 72) mc->flags &= ~MCFLG_ECC_ENABLE; 1571 1572 /* 1573 * If it was a double-sided DIMM, also mark the odd chip select 1574 * present. 1575 */ 1576 1577 if ((spd[JEDEC_SPD_SIDES] == 2) && !(mc->flags & MCFLG_BIGMEM)) { 1578 csdata_t *oddcs = &(mc->csdata[chipsel | 1]); 1579 1580 oddcs->rows = cs->rows; 1581 oddcs->cols = cs->cols; 1582 oddcs->banks = cs->banks; 1583 oddcs->flags = CS_PRESENT; 1584 1585 oddcs->spd_dramtype = spd[JEDEC_SPD_MEMTYPE]; 1586 oddcs->spd_tCK_25 = spd[JEDEC_SPD_tCK25]; 1587 oddcs->spd_tCK_20 = spd[JEDEC_SPD_tCK20]; 1588 oddcs->spd_tCK_10 = spd[JEDEC_SPD_tCK10]; 1589 oddcs->spd_rfsh = spd[JEDEC_SPD_RFSH]; 1590 oddcs->spd_caslatency = spd[JEDEC_SPD_CASLATENCIES]; 1591 oddcs->spd_attributes = spd[JEDEC_SPD_ATTRIBUTES]; 1592 oddcs->spd_tRAS = spd[JEDEC_SPD_tRAS]; 1593 oddcs->spd_tRP = spd[JEDEC_SPD_tRP]; 1594 oddcs->spd_tRRD = spd[JEDEC_SPD_tRRD]; 1595 oddcs->spd_tRCD = spd[JEDEC_SPD_tRCD]; 1596 oddcs->spd_tRFC = spd[JEDEC_SPD_tRFC]; 1597 oddcs->spd_tRC = spd[JEDEC_SPD_tRC]; 1598 } 1599 1600} 1601 1602 1603/* ********************************************************************* 1604 * SB1250_DRAM_READPARAMS(d,init) 1605 * 1606 * Read all the parameters from the user parameter table and 1607 * digest them into our local data structure. This routine basically 1608 * walks the table and calls the routine above to handle each 1609 * entry. 1610 * 1611 * Input parameters: 1612 * d - our data structure (our RAM data) 1613 * init - pointer to user config table 1614 * 1615 * Return value: 1616 * nothing 1617 ********************************************************************* */ 1618 1619static void sb1250_dram_readparams(initdata_t *d,const draminittab_t *init) 1620{ 1621 mcdata_t *mc; 1622 csdata_t *cs; 1623 uint64_t sysrev; 1624 1625 sysrev = READCSR(PHYS_TO_K1(A_SCD_SYSTEM_REVISION)); 1626 1627 /* 1628 * Assume we're starting on the first channel. We should have a CHCFG record 1629 * to set the initial channel number, this is just in case. 1630 */ 1631 mc = &(d->mc[d->firstchan]); 1632 1633 /* Default clock config unless overridden */ 1634 if (G_SYS_REVISION(sysrev) >= K_SYS_REVISION_PASS1 && 1635 G_SYS_REVISION(sysrev) < K_SYS_REVISION_PASS2) { 1636 /* pass1 */ 1637 mc->clkconfig = V_MC_CLKCONFIG_VALUE_PASS1; 1638 } 1639 else { 1640 /* pass2 */ 1641 mc->clkconfig = V_MC_CLKCONFIG_VALUE; 1642 } 1643 1644 cs = &(mc->csdata[0]); 1645 1646 while (init->mcr.mcr_type != MCR_EOT) { 1647 1648#ifdef _MCSTANDALONE_NOISY_ 1649 printf("DRAM: Processing record '%s'\n",sb1250_rectypes[init->mcr.mcr_type]); 1650#endif 1651 1652 switch (init->mcr.mcr_type) { 1653 1654 case MCR_GLOBALS: 1655 if (init->gbl.gbl_intlv_ch) d->flags |= M_MCINIT_TRYPINTLV; 1656 break; 1657 1658 case MCR_CHCFG: 1659 mc = &(d->mc[init->cfg.cfg_chan]); 1660 mc->mintmemclk = DECTO10THS(init->cfg.cfg_mintmemclk); 1661 mc->dramtype = init->cfg.cfg_dramtype; 1662 mc->pagepolicy = init->cfg.cfg_pagepolicy; 1663 mc->blksize = init->cfg.cfg_blksize; 1664 mc->cfgcsint = init->cfg.cfg_intlv_cs; 1665 1666 /* Default clock config unless overridden */ 1667 if (G_SYS_REVISION(sysrev) >= K_SYS_REVISION_PASS1 && 1668 G_SYS_REVISION(sysrev) < K_SYS_REVISION_PASS2) { 1669 /* pass1 */ 1670 mc->clkconfig = V_MC_CLKCONFIG_VALUE_PASS1; 1671 } 1672 else { 1673 /* pass2 */ 1674 mc->clkconfig = V_MC_CLKCONFIG_VALUE; 1675 } 1676 1677 mc->flags = (init->cfg.cfg_ecc & MCFLG_ECC_ENABLE) | 1678 (init->cfg.cfg_flags & (MCFLG_FORCEREG | MCFLG_BIGMEM)); 1679 mc->roundtrip = DECTO10THS(init->cfg.cfg_roundtrip); 1680 if (mc->roundtrip == 0 && mc->dramtype != DRAM_TYPE_SPD) { 1681 /* 1682 * Only set default roundtrip if mem type is specified, else wait 1683 * to get type from SPD 1684 */ 1685 mc->roundtrip = (mc->dramtype == FCRAM) ? 1686 DEFAULT_MEMORY_ROUNDTRIP_TIME_FCRAM : DEFAULT_MEMORY_ROUNDTRIP_TIME; 1687 } 1688 if (mc->dramtype == FCRAM) mc->pagepolicy = CLOSED; /*FCRAM must be closed page policy*/ 1689 cs = &(mc->csdata[0]); 1690 break; 1691 1692 case MCR_TIMING: 1693 cs->spd_tCK_25 = init->tmg.tmg_tCK; 1694 cs->spd_tCK_20 = 0; 1695 cs->spd_tCK_10 = 0; 1696 cs->spd_rfsh = init->tmg.tmg_rfsh; 1697 cs->spd_caslatency = init->tmg.tmg_caslatency; 1698 cs->spd_attributes = init->tmg.tmg_attributes; 1699 cs->spd_tRAS = init->tmg.tmg_tRAS; 1700 cs->spd_tRP = init->tmg.tmg_tRP; 1701 cs->spd_tRRD = init->tmg.tmg_tRRD; 1702 cs->spd_tRCD = init->tmg.tmg_tRCD; 1703 cs->spd_tRFC = init->tmg.tmg_tRFC; 1704 cs->spd_tRC = init->tmg.tmg_tRC; 1705 break; 1706 1707 case MCR_CLKCFG: 1708 mc->clkconfig = 1709 V_MC_ADDR_SKEW((uint64_t)(init->clk.clk_addrskew)) | 1710 V_MC_DQO_SKEW((uint64_t)(init->clk.clk_dqoskew)) | 1711 V_MC_DQI_SKEW((uint64_t)(init->clk.clk_dqiskew)) | 1712 V_MC_ADDR_DRIVE((uint64_t)(init->clk.clk_addrdrive)) | 1713 V_MC_DATA_DRIVE((uint64_t)(init->clk.clk_datadrive)) | 1714 V_MC_CLOCK_DRIVE((uint64_t)(init->clk.clk_clkdrive)); 1715 break; 1716 1717 case MCR_GEOM: 1718 cs = &(mc->csdata[init->geom.geom_csel]); 1719 cs->rows = init->geom.geom_rows; 1720 cs->cols = init->geom.geom_cols; 1721 cs->banks = init->geom.geom_banks; 1722 cs->flags |= CS_PRESENT; 1723 break; 1724 1725 case MCR_SPD: 1726 cs = &(mc->csdata[init->spd.spd_csel]); 1727 sb1250_dram_getinfo(init->spd.spd_smbuschan, 1728 init->spd.spd_smbusdev, 1729 mc, 1730 init->spd.spd_csel); 1731 1732 if (mc->dramtype == DRAM_TYPE_SPD) { 1733 /* Use the DRAM type we get from the SPD */ 1734 if (cs->spd_dramtype == SPD_MEMTYPE_FCRAM){ 1735 mc->dramtype = FCRAM; 1736 mc->pagepolicy = CLOSED; 1737 if (mc->roundtrip == 0) mc->roundtrip = DEFAULT_MEMORY_ROUNDTRIP_TIME_FCRAM; 1738 } 1739 else { 1740 mc->dramtype = JEDEC; 1741 if (mc->roundtrip == 0) mc->roundtrip = DEFAULT_MEMORY_ROUNDTRIP_TIME; 1742 } 1743 } 1744 mc->rfsh = cs->spd_rfsh; 1745 break; 1746 1747 case MCR_MANTIMING: 1748 /* Manual timing - pick record up as bytes because we cannot 1749 guarantee the alignment of the "mtm_timing" field in our 1750 structure -- each row is 12 bytes, not good */ 1751 mc->rfsh = (uint16_t) init->mtm.mtm_rfsh; /* units: JEDEC refresh value */ 1752 mc->tCK = (uint16_t) init->mtm.mtm_tCK; /* units: BCD, like SPD */ 1753 mc->mantiming = 1754 (((uint64_t) init->mtm.mtm_timing[0]) << 56) | 1755 (((uint64_t) init->mtm.mtm_timing[1]) << 48) | 1756 (((uint64_t) init->mtm.mtm_timing[2]) << 40) | 1757 (((uint64_t) init->mtm.mtm_timing[3]) << 32) | 1758 (((uint64_t) init->mtm.mtm_timing[4]) << 24) | 1759 (((uint64_t) init->mtm.mtm_timing[5]) << 16) | 1760 (((uint64_t) init->mtm.mtm_timing[6]) << 8) | 1761 (((uint64_t) init->mtm.mtm_timing[7]) << 0); 1762 break; 1763 1764 default: 1765 break; 1766 } 1767 1768 init++; 1769 } 1770 1771 /* 1772 * Okay, now we've internalized all the data from the SPDs 1773 * and/or the init table. 1774 */ 1775 1776} 1777 1778 1779 1780/* ********************************************************************* 1781 * SB1250_DRAMINIT_DELAY 1782 * 1783 * This little routine delays at least 200 microseconds. 1784 * 1785 * Input parameters: 1786 * nothing 1787 * 1788 * Return value: 1789 * nothing. 1790 * 1791 * Registers used: 1792 * tmp0,tmp1 1793 ********************************************************************* */ 1794 1795/* 200 microseconds = 5KHz, so delay 1GHz/5Khz = 200,000 cycles */ 1796 1797#ifdef _FASTEMUL_ 1798#define DRAMINIT_DELAY_CNT "50" 1799#else 1800#define DRAMINIT_DELAY_CNT "(1000000000/5000)" 1801#endif 1802 1803#if defined(_MCSTANDALONE_) 1804#define DRAMINIT_DELAY() /* not running on a 1250, no delays */ 1805#else 1806#define DRAMINIT_DELAY() sb1250_draminit_delay() 1807 1808static void sb1250_draminit_delay(void) 1809{ 1810 __asm(" li $9," DRAMINIT_DELAY_CNT " ; " 1811 " mtc0 $0,$9 ; " 1812 "1: mfc0 $8,$9 ; " 1813 " .set push ; .set mips64 ; ssnop ; ssnop ; .set pop ;" 1814 " blt $8,$9,1b ;"); 1815} 1816#endif 1817 1818 1819 1820 1821/* ********************************************************************* 1822 * MAKEDRAMMASK(dest,width,pos) 1823 * 1824 * Create a 64-bit mask for the DRAM config registers 1825 * 1826 * Input parameters: 1827 * width - number of '1' bits to set 1828 * pos - position (from the right) of the first '1' bit 1829 * 1830 * Return value: 1831 * mask with specified with at specified position 1832 ********************************************************************* */ 1833 1834#define MAKEDRAMMASK(width,pos) _SB_MAKEMASK(width,pos) 1835 1836 1837/* ********************************************************************* 1838 * SB1250_JEDEC_INITCMDS 1839 * 1840 * Issue the sequence of DRAM init commands (JEDEC SDRAMs) 1841 * 1842 * Input parameters: 1843 * mcnum - memory controller index (0/1) 1844 * mc - pointer to data for this memory controller 1845 * csel - which chip select to send init commands for 1846 * lmbank - for largemem systems, the cs qualifiers to be 1847 * output on CS[2:3] 1848 * tdata - chip select to use as a template for timing data 1849 * 1850 * Return value: 1851 * nothing 1852 ********************************************************************* */ 1853 1854static void sb1250_jedec_initcmds(int mcnum,mcdata_t *mc,int csel, 1855 int lmbank,csdata_t *tdata) 1856{ 1857 uint64_t csmask; 1858 sbport_t cmd; 1859 sbport_t mode; 1860 uint64_t modebits; 1861 uint64_t casbits; 1862 1863 csmask = M_MC_CS0 << csel; /* convert chip select # to mask */ 1864 1865 if (mc->flags & MCFLG_BIGMEM) { 1866 /* 1867 * so that the banks will all get their precharge signals, 1868 * put the CS qualifiers out on CS[2:3]. 1869 */ 1870 csmask |= (uint64_t)(lmbank << 6); 1871 } 1872 1873 cmd = (sbport_t) PHYS_TO_K1(A_MC_REGISTER(mcnum,R_MC_DRAMCMD)); 1874 mode = (sbport_t) PHYS_TO_K1(A_MC_REGISTER(mcnum,R_MC_DRAMMODE)); 1875 1876 /* 1877 * Using the data in the timing template, figure out which 1878 * CAS latency command to issue. 1879 */ 1880 1881 switch (tdata->flags & CS_CASLAT_MASK) { 1882 case CS_CASLAT_30: 1883 casbits = V_MC_MODE(JEDEC_SDRAM_MRVAL_CAS3); 1884 break; 1885 default: 1886 case CS_CASLAT_25: 1887 casbits = V_MC_MODE(JEDEC_SDRAM_MRVAL_CAS25); 1888 break; 1889 case CS_CASLAT_20: 1890 casbits = V_MC_MODE(JEDEC_SDRAM_MRVAL_CAS2); 1891 break; 1892 case CS_CASLAT_15: 1893 casbits = V_MC_MODE(JEDEC_SDRAM_MRVAL_CAS15); 1894 break; 1895 } 1896 1897 /* 1898 * Set up for doing mode register writes to the SDRAMs 1899 * 1900 * First time, we set bit 8 to reset the DLL 1901 */ 1902 1903 modebits = V_MC_EMODE(JEDEC_SDRAM_EMRVAL) | 1904 V_MC_MODE(JEDEC_SDRAM_MRVAL_RESETDLL) | 1905 V_MC_DRAM_TYPE(JEDEC); 1906 1907 WRITECSR(mode,modebits | casbits); 1908 1909 WRITECSR(cmd,csmask | V_MC_COMMAND_CLRPWRDN); 1910 DRAMINIT_DELAY(); 1911 1912 WRITECSR(cmd,csmask | V_MC_COMMAND_PRE); 1913 DRAMINIT_DELAY(); 1914 1915 WRITECSR(cmd,csmask | V_MC_COMMAND_EMRS); 1916 DRAMINIT_DELAY(); 1917 1918 WRITECSR(cmd,csmask | V_MC_COMMAND_MRS); 1919 DRAMINIT_DELAY(); 1920 1921 WRITECSR(cmd,csmask | V_MC_COMMAND_PRE); 1922 DRAMINIT_DELAY(); 1923 1924 WRITECSR(cmd,csmask | V_MC_COMMAND_AR); 1925 DRAMINIT_DELAY(); 1926 1927 WRITECSR(cmd,csmask | V_MC_COMMAND_AR); 1928 DRAMINIT_DELAY(); 1929 1930 /* 1931 * This time, clear bit 8 to start the DLL 1932 */ 1933 1934 modebits = V_MC_EMODE(JEDEC_SDRAM_EMRVAL) | 1935 V_MC_DRAM_TYPE(JEDEC); 1936 1937 WRITECSR(mode,modebits | casbits); 1938 WRITECSR(cmd,csmask | V_MC_COMMAND_MRS); 1939 DRAMINIT_DELAY(); 1940 1941} 1942 1943/* ********************************************************************* 1944 * SB1250_SGRAM_INITCMDS 1945 * 1946 * Issue the sequence of DRAM init commands. (SGRAMs) 1947 * Note: this routine does not support "big memory" (external decode) 1948 * 1949 * Input parameters: 1950 * mcnum - memory controller index (0/1) 1951 * mc - pointer to data for this memory controller 1952 * csel - which chip select to send init commands for 1953 * tdata - chip select to use as a template for timing data 1954 * 1955 * Return value: 1956 * nothing 1957 ********************************************************************* */ 1958 1959static void sb1250_sgram_initcmds(int mcnum,mcdata_t *mc,int csel,csdata_t *tdata) 1960{ 1961 uint64_t csmask; 1962 sbport_t cmd; 1963 sbport_t mode; 1964 1965 csmask = M_MC_CS0 << csel; /* convert chip select # to mask */ 1966 cmd = (sbport_t) PHYS_TO_K1(A_MC_REGISTER(mcnum,R_MC_DRAMCMD)); 1967 mode = (sbport_t) PHYS_TO_K1(A_MC_REGISTER(mcnum,R_MC_DRAMMODE)); 1968 1969 1970 WRITECSR(cmd,csmask | V_MC_COMMAND_CLRPWRDN); 1971 DRAMINIT_DELAY(); 1972 1973 WRITECSR(cmd,csmask | V_MC_COMMAND_PRE); 1974 DRAMINIT_DELAY(); 1975 1976 /* 1977 * Set up for doing mode register writes to the SDRAMs 1978 * 1979 * mode 0x62 is "sequential 4-byte bursts, CAS Latency 2.5" 1980 * mode 0x22 is "sequential 4-byte bursts, CAS Latency 2" 1981 * 1982 * First time, we set bit 8 to reset the DLL 1983 */ 1984 1985 WRITECSR(mode,V_MC_EMODE(SGRAM_EMRVAL) | 1986 V_MC_MODE(SGRAM_MRVAL) | 1987 V_MC_MODE(SGRAM_MRVAL_RESETDLL) | 1988 V_MC_DRAM_TYPE(SGRAM)); 1989 1990 WRITECSR(cmd,csmask | V_MC_COMMAND_EMRS); 1991 DRAMINIT_DELAY(); 1992 1993 WRITECSR(cmd,csmask | V_MC_COMMAND_MRS); 1994 DRAMINIT_DELAY(); 1995 1996 WRITECSR(cmd,csmask | V_MC_COMMAND_PRE); 1997 DRAMINIT_DELAY(); 1998 1999 WRITECSR(cmd,csmask | V_MC_COMMAND_AR); 2000 DRAMINIT_DELAY(); 2001 2002 WRITECSR(cmd,csmask | V_MC_COMMAND_AR); 2003 DRAMINIT_DELAY(); 2004 2005 /* 2006 * This time, clear bit 8 to start the DLL 2007 */ 2008 2009 WRITECSR(mode,V_MC_EMODE(SGRAM_EMRVAL) | 2010 V_MC_MODE(SGRAM_MRVAL) | 2011 V_MC_DRAM_TYPE(SGRAM)); 2012 WRITECSR(cmd,csmask | V_MC_COMMAND_MRS); 2013 DRAMINIT_DELAY(); 2014 2015} 2016 2017/* ********************************************************************* 2018 * SB1250_FCRAM_INITCMDS 2019 * 2020 * Issue the sequence of DRAM init commands. (FCRAMs) 2021 * Note: this routine does not support "big memory" (external decode) 2022 * 2023 * Input parameters: 2024 * mcnum - memory controller index (0/1) 2025 * mc - pointer to data for this memory controller 2026 * csel - which chip select to send init commands for 2027 * tdata - chip select to use as a template for timing data 2028 * 2029 * Return value: 2030 * nothing 2031 ********************************************************************* */ 2032 2033static void sb1250_fcram_initcmds(int mcnum,mcdata_t *mc,int csel,csdata_t *tdata) 2034{ 2035 uint64_t csmask; 2036 sbport_t cmd; 2037 sbport_t mode; 2038 2039 csmask = M_MC_CS0 << csel; /* convert chip select # to mask */ 2040 cmd = (sbport_t) PHYS_TO_K1(A_MC_REGISTER(mcnum,R_MC_DRAMCMD)); 2041 mode = (sbport_t) PHYS_TO_K1(A_MC_REGISTER(mcnum,R_MC_DRAMMODE)); 2042 2043 2044 /* 2045 * For FCRAMs the type must be set first, since much of the 2046 * init state machine is done in hardware. 2047 */ 2048 2049 WRITECSR(mode, V_MC_DRAM_TYPE(FCRAM)); 2050 DRAMINIT_DELAY(); /* Required delay for FCRAM */ 2051 2052 WRITECSR(cmd,csmask | V_MC_COMMAND_CLRPWRDN); 2053 DRAMINIT_DELAY(); 2054 2055 WRITECSR(cmd,csmask | K_MC_COMMAND_PRE); 2056 DRAMINIT_DELAY(); 2057 2058 /* 2059 * Set up for doing mode register writes to the FCRAMs 2060 * 2061 * mode 0x32 is "sequential 4-byte bursts, CAS Latency 3.0" 2062 */ 2063 2064 WRITECSR(mode,V_MC_EMODE(FCRAM_EMRVAL) | 2065 V_MC_MODE(FCRAM_MRVAL) | 2066 V_MC_DRAM_TYPE(FCRAM)); 2067 2068 WRITECSR(cmd,csmask | V_MC_COMMAND_EMRS); 2069 DRAMINIT_DELAY(); 2070 2071 WRITECSR(cmd,csmask | V_MC_COMMAND_MRS); 2072 DRAMINIT_DELAY(); 2073 2074 WRITECSR(cmd,csmask | V_MC_COMMAND_AR); 2075 DRAMINIT_DELAY(); 2076 2077 WRITECSR(cmd,csmask | V_MC_COMMAND_AR); 2078 DRAMINIT_DELAY(); 2079 2080 /* 2081 * Do 4 dummy writes, one to each bank, to get the 2082 * memory started. 2083 */ 2084 2085#ifndef _MCSTANDALONE_ /* only on real hardware */ 2086 do { 2087 volatile uint64_t *ptr; 2088 2089 ptr = (volatile uint64_t *) PHYS_TO_K1(0); 2090 *(ptr+(0x00>>3)) = 0; 2091 *(ptr+(0x20>>3)) = 0; 2092 *(ptr+(0x40>>3)) = 0; 2093 *(ptr+(0x60>>3)) = 0; 2094 } while (0); 2095#endif 2096 2097} 2098 2099 2100 2101 2102/* ********************************************************************* 2103 * SB1250_DRAM_INTLV 2104 * 2105 * Do row/column/bank initialization for 128-byte interleaved 2106 * mode, and also interleave across ports. You need to have 2107 * the same geometry DIMMs installed on both memory 2108 * channels for this to work. 2109 * 2110 * Interleaved modes will assign address bits in the following 2111 * order: 2112 * 2113 * RRRRRRRR...R CCCCCCCC...C NN BB P CC xx000 2114 * 2115 * Where 'R' are row address bits, 2116 * 'C' are column address bits 2117 * 'N' are chip-select bits 2118 * 'B' are bank select bits 2119 * 'P' is the channel (port) select 2120 * 'x' is ignored by the MC, but will be set to '1'. 2121 * 2122 * Input parameters: 2123 * lots of stuff 2124 * 2125 * Return value: 2126 * lots of stuff 2127 ********************************************************************* */ 2128static void sb1250_dram_intlv(initdata_t *d) 2129{ 2130 int ttlbits; /* bit counter */ 2131 int rows,columns,banks; 2132 int csidx; 2133 sbport_t mc0base; 2134 sbport_t mc1base; 2135 sbport_t csx0base; 2136 sbport_t csx1base; 2137 uint64_t mask; 2138 uint64_t colmask; 2139 int t; 2140 uint64_t dimmsize; 2141 int num_csint = 1 << d->mc[0].csint; 2142 uint64_t tmp; 2143 2144 d->ttlbytes = 0; /* start with zero memory */ 2145 2146 /* 2147 * Loop through each chip select 2148 */ 2149 2150 mc0base = PHYS_TO_K1(A_MC_BASE(0)); 2151 mc1base = PHYS_TO_K1(A_MC_BASE(1)); 2152 2153 for (csidx = 0; csidx < MC_CHIPSELS; csidx++) { 2154 2155 /* 2156 * Address of CS-specific registers 2157 */ 2158 2159 csx0base = mc0base + R_MC_CSX_BASE + csidx*MC_CSX_SPACING; 2160 csx1base = mc1base + R_MC_CSX_BASE + csidx*MC_CSX_SPACING; 2161 2162 /* 2163 * Ignore this chipsel if we're not using it 2164 */ 2165 2166 if (!(d->mc[0].csdata[csidx].flags & CS_PRESENT)) continue; 2167 if (!(d->mc[1].csdata[csidx].flags & CS_PRESENT)) continue; 2168 2169 /* 2170 * Remember we did something to this MC. We won't bother 2171 * activating controllers we don't use. 2172 */ 2173 2174 d->inuse |= 3; /* we're using both controllers 0 and 1 */ 2175 2176 /* 2177 * Dig the geometry out of the structure 2178 */ 2179 2180 columns = d->mc[0].csdata[csidx].cols; 2181 rows = d->mc[0].csdata[csidx].rows; 2182 banks = d->mc[0].csdata[csidx].banks; 2183 2184 /* 2185 * The lowest 3 bits are never set in any mask. 2186 * They represent the byte width of the DIMM. 2187 */ 2188 2189 ttlbits = 3; 2190 2191 /* 2192 * The first two bits are always set and are part of the 2193 * column bits. Actually, the MC ignores these bits 2194 * but we set them here for clarity. 2195 * 2196 * Depending on the block size, 0, 1, or 2 additional 2197 * bits are used for column interleave. 2198 * 2199 * When interleaving ports, we always have a block 2200 * size of 128. It will work to use other block sizes, 2201 * but performance will suffer. 2202 */ 2203 2204 switch (d->mc[0].blksize) { 2205 case 32: t = 2; break; /* 32-byte interleave */ 2206 case 64: t = 3; break; /* 64-byte interleave */ 2207 default: t = 4; break; /* 128-byte interleave */ 2208 } 2209 2210 columns -= t; 2211 colmask = MAKEDRAMMASK(t,ttlbits); 2212 ttlbits += t; 2213 2214 /* 2215 * add 1 to 'ttlbits' to account for the bit we're 2216 * using for port intleave. The current value 2217 * of 'ttlbits' also happens to be the 2218 * bit number for port interleaving. 2219 */ 2220 2221 d->pintbit = ttlbits; /* interleave bit is right here */ 2222 2223 ttlbits++; 2224 2225 /* 2226 * Now do the bank mask 2227 */ 2228 2229 mask = MAKEDRAMMASK(banks,ttlbits); 2230 ttlbits += banks; 2231 WRITECSR(csx0base+R_MC_CSX_BA,mask); 2232 WRITECSR(csx1base+R_MC_CSX_BA,mask); 2233 2234 /* 2235 * Now do the chip select mask 2236 */ 2237 2238 if ((d->mc[0].csint > 0) && 2239 (csidx < num_csint)) { 2240 mask = MAKEDRAMMASK(d->mc[0].csint,ttlbits); 2241 ttlbits += d->mc[0].csint; 2242 WRITECSR(mc0base+R_MC_CS_INTERLEAVE,mask); 2243 WRITECSR(mc1base+R_MC_CS_INTERLEAVE,mask); 2244 } 2245 2246 /* 2247 * Do the rest of the column bits 2248 */ 2249 2250 mask = MAKEDRAMMASK(columns,ttlbits); 2251 colmask |= mask; 2252 WRITECSR(csx0base+R_MC_CSX_COL,colmask); 2253 WRITECSR(csx1base+R_MC_CSX_COL,colmask); 2254 ttlbits += columns; 2255 2256 /* 2257 * Finally, do the rows. If we're in "big" memory 2258 * mode, two additional row bits are used for the 2259 * chip select bits. 2260 */ 2261 2262 if (d->mc[0].flags & MCFLG_BIGMEM) { 2263 rows += 2; /* add two bits for chip select */ 2264 /* 2265 * The "bigmem" bit will be set in the MC_CONFIG 2266 * register back in the main routine. 2267 */ 2268 } 2269 2270 mask = MAKEDRAMMASK(rows,ttlbits); 2271 ttlbits += rows; 2272 WRITECSR(csx0base+R_MC_CSX_ROW,mask); 2273 WRITECSR(csx1base+R_MC_CSX_ROW,mask); 2274 2275 /* 2276 * The total size of this DIMM is 1 << ttlbits, which is inflated by a 2277 * factor of num_csint to cover all interleaved chip selects. 2278 */ 2279 2280 dimmsize = ((uint64_t) 1) << ttlbits; 2281 2282 /* 2283 * Program the start and end registers. The start address is 0 2284 * our if csidx is cs-interleaved; otherwise, the start address 2285 * is the current "ttlbytes". 2286 */ 2287 2288 if (csidx < num_csint) { 2289 d->ttlbytes += dimmsize >> d->mc[0].csint; 2290 } 2291 else { 2292 mask = READCSR(mc0base+R_MC_CS_START); 2293 tmp = d->ttlbytes >> 24; 2294 if (tmp >= 0x40) tmp = (0x100 + (tmp - 0x40)); /* Adj for exp space */ 2295 mask |= (tmp << (16*csidx)); 2296 WRITECSR(mc0base+R_MC_CS_START,mask); 2297 2298 mask = READCSR(mc1base+R_MC_CS_START); 2299 tmp = d->ttlbytes >> 24; 2300 if (tmp >= 0x40) tmp = (0x100 + (tmp - 0x40)); /* Adj for exp space */ 2301 mask |= (tmp << (16*csidx)); 2302 WRITECSR(mc1base+R_MC_CS_START,mask); 2303 2304 d->ttlbytes += dimmsize; 2305 dimmsize = d->ttlbytes; /* setup dimmsize for cs_end below */ 2306 } 2307 2308 mask = READCSR(mc0base+R_MC_CS_END); 2309 tmp = dimmsize >> 24; 2310 if (tmp > 0x40) tmp = (0x100 + (tmp - 0x40)); /* Adj for exp space */ 2311 mask |= (tmp << (16*csidx)); 2312 WRITECSR(mc0base+R_MC_CS_END,mask); 2313 2314 mask = READCSR(mc1base+R_MC_CS_END); 2315 tmp = dimmsize >> 24; 2316 if (tmp > 0x40) tmp = (0x100 + (tmp - 0x40)); /* Adj for exp space */ 2317 mask |= (tmp << (16*csidx)); 2318 WRITECSR(mc1base+R_MC_CS_END,mask); 2319 } 2320} 2321 2322 2323 2324 2325/* ********************************************************************* 2326 * SB1250_DRAM_MSBCS 2327 * 2328 * Do row/column/bank initialization for MSB-CS (noninterleaved) 2329 * mode. This is only separated out of the main loop to make things 2330 * read easier, it's not a generally useful subroutine by itself. 2331 * 2332 * Input parameters: 2333 * initdata_t structure 2334 * 2335 * Return value: 2336 * memory controller initialized 2337 ********************************************************************* */ 2338 2339static void sb1250_dram_msbcs(initdata_t *d) 2340{ 2341 int ttlbits; /* bit counter */ 2342 int rows,columns,banks; 2343 int mcidx,csidx; 2344 sbport_t mcbase; 2345 sbport_t csxbase; 2346 uint64_t mask; 2347 uint64_t colmask; 2348 int t; 2349 uint64_t dimmsize; 2350 2351 d->ttlbytes = 0; /* start with zero memory */ 2352 2353 /* 2354 * Loop through each memory controller and each chip select 2355 * within each memory controller. 2356 */ 2357 2358 for (mcidx = d->firstchan; mcidx < MC_CHANNELS; mcidx++) { 2359 int num_csint = 1 << d->mc[mcidx].csint; 2360 uint64_t channel_start = d->ttlbytes; 2361 uint64_t end_addr; 2362 uint64_t tmp; 2363 2364 mcbase = PHYS_TO_K1(A_MC_BASE(mcidx)); 2365 2366 for (csidx = 0; csidx < MC_CHIPSELS; csidx++) { 2367 2368 /* 2369 * Address of CS-specific registers 2370 */ 2371 2372 csxbase = mcbase + R_MC_CSX_BASE + csidx * MC_CSX_SPACING; 2373 2374 /* 2375 * Ignore this chipsel if we're not using it 2376 */ 2377 2378 if (!(d->mc[mcidx].csdata[csidx].flags & CS_PRESENT)) continue; 2379 2380 /* 2381 * Remember we did something to this MC. We won't bother 2382 * activating controllers we don't use. 2383 */ 2384 2385 d->inuse |= (1 << mcidx); 2386 2387 /* 2388 * Dig the geometry out of the structure 2389 */ 2390 2391 columns = d->mc[mcidx].csdata[csidx].cols; 2392 rows = d->mc[mcidx].csdata[csidx].rows; 2393 banks = d->mc[mcidx].csdata[csidx].banks; 2394 2395 /* 2396 * The lowest 3 bits are never set in any mask. 2397 * They represent the byte width of the DIMM. 2398 */ 2399 2400 ttlbits = 3; 2401 2402 /* 2403 * The first two bits are always set and are part of the 2404 * column bits. Actually, the MC ignores these bits 2405 * but we set them here for clarity. 2406 * 2407 * Depending on the block size, 0, 1, or 2 additional 2408 * bits are used for column interleave. 2409 */ 2410 2411 switch (d->mc[mcidx].blksize) { 2412 case 32: t = 2; break; /* 32-byte interleave */ 2413 case 64: t = 3; break; /* 64-byte interleave */ 2414 default: t = 4; break; /* 128-byte interleave */ 2415 } 2416 2417 columns -= t; 2418 colmask = MAKEDRAMMASK(t,ttlbits); 2419 ttlbits += t; 2420 2421 /* 2422 * Now do the bank mask 2423 */ 2424 2425 mask = MAKEDRAMMASK(banks,ttlbits); 2426 ttlbits += banks; 2427 WRITECSR(csxbase+R_MC_CSX_BA,mask); 2428 2429 /* 2430 * Now do the chip select mask 2431 */ 2432 2433 if ((d->mc[mcidx].csint > 0) && 2434 (csidx < num_csint)) { 2435 mask = MAKEDRAMMASK(d->mc[mcidx].csint,ttlbits); 2436 ttlbits += d->mc[mcidx].csint; 2437 WRITECSR(mcbase+R_MC_CS_INTERLEAVE,mask); 2438 } 2439 2440 /* 2441 * Do the rest of the column bits 2442 */ 2443 2444 mask = MAKEDRAMMASK(columns,ttlbits); 2445 colmask |= mask; 2446 WRITECSR(csxbase+R_MC_CSX_COL,colmask); 2447 ttlbits += columns; 2448 2449 /* 2450 * Finally, do the rows. If we're in "big" memory 2451 * mode, two additional row bits are used for the 2452 * chip select bits. 2453 */ 2454 2455 if (d->mc[mcidx].flags & MCFLG_BIGMEM) { 2456 rows += 2; /* add two bits for chip select */ 2457 /* 2458 * The "bigmem" bit will be set in the MC_CONFIG 2459 * register back in the main routine. 2460 */ 2461 } 2462 2463 mask = MAKEDRAMMASK(rows,ttlbits); 2464 ttlbits += rows; 2465 WRITECSR(csxbase+R_MC_CSX_ROW,mask); 2466 2467 /* 2468 * The total size of this DIMM is 1 << ttlbits, which is inflated 2469 * by a factor of num_csint to cover all interleaved chip selects. 2470 */ 2471 2472 dimmsize = ((uint64_t) 1) << ttlbits; 2473 2474 /* 2475 * Program the start and end registers. The start address is 2476 * channel_start if csidx is cs-interleaved; otherwise, the 2477 * start address is the current "ttlbytes". 2478 */ 2479 2480 if (csidx < num_csint) { 2481 mask = READCSR(mcbase+R_MC_CS_START); 2482 tmp = (channel_start >> 24); 2483 if (tmp >= 0x40) tmp = (0x100 + (tmp - 0x40)); /* Adj for exp space */ 2484 mask |= (tmp << (16*csidx)); 2485 WRITECSR(mcbase+R_MC_CS_START,mask); 2486 2487 d->ttlbytes += dimmsize >> d->mc[mcidx].csint; 2488 end_addr = channel_start + dimmsize; 2489 } 2490 else { 2491 mask = READCSR(mcbase+R_MC_CS_START); 2492 tmp = d->ttlbytes >> 24; 2493 if (tmp >= 0x40) tmp = (0x100 + (tmp - 0x40)); /* Adj for exp space */ 2494 mask |= (tmp << (16*csidx)); 2495 WRITECSR(mcbase+R_MC_CS_START,mask); 2496 2497 d->ttlbytes += dimmsize; 2498 end_addr = d->ttlbytes; 2499 } 2500 2501 mask = READCSR(mcbase+R_MC_CS_END); 2502 tmp = end_addr >> 24; 2503 if (tmp > 0x40) tmp = (0x100 + (tmp - 0x40)); /* Adj for exp space */ 2504 mask |= (tmp << (16*csidx)); 2505 WRITECSR(mcbase+R_MC_CS_END,mask); 2506 } 2507 } 2508} 2509 2510 2511/* ********************************************************************* 2512 * SB1250_DRAM_ANALYZE(d) 2513 * 2514 * Analyze the DRAM parameters, determine if we can do 2515 * port interleaving mode 2516 * 2517 * Input parameters: 2518 * d - init data 2519 * 2520 * Return value: 2521 * nothing (fields in initdata are updated) 2522 ********************************************************************* */ 2523 2524static void sb1250_dram_analyze(initdata_t *d) 2525{ 2526 int csidx; 2527 int mcidx; 2528 int csint; 2529 2530 /* 2531 * Determine if we can do port interleaving. This is possible if 2532 * the DIMMs on each channel are the same. 2533 */ 2534 2535 for (csidx = 0; csidx < MC_CHIPSELS; csidx++) { 2536 if (d->mc[0].csdata[csidx].rows != d->mc[1].csdata[csidx].rows) break; 2537 if (d->mc[0].csdata[csidx].cols != d->mc[1].csdata[csidx].cols) break; 2538 if (d->mc[0].csdata[csidx].banks != d->mc[1].csdata[csidx].banks) break; 2539 if (d->mc[0].csdata[csidx].flags != d->mc[1].csdata[csidx].flags) break; 2540 } 2541 2542 /* 2543 * If the per-controller flags don't match, no port interleaving. 2544 * I.e., you can't mix and match ECC, big memory, etc. 2545 */ 2546 2547 if (d->mc[0].flags != d->mc[1].flags) csidx = 0; 2548 2549 /* 2550 * Done with checks, see if we can do it. 2551 */ 2552 2553 if (csidx == MC_CHIPSELS) { 2554 /* 2555 * All channels are the same, we can interleave. If we were asked 2556 * to try it, then enable it. 2557 */ 2558 if (d->flags & M_MCINIT_TRYPINTLV) d->flags |= M_MCINIT_PINTLV; 2559 } 2560 2561 /* 2562 * Determine how many CS interleave bits (0, 1, or 2) will work. 2563 * Memory channels are checked separately. If port (i.e., channel) 2564 * interleaving is allowed, each channel will end up with the same number 2565 * of CS interleave bits. 2566 * Note: No support for interleaving only chip selects 2 & 3. 2567 */ 2568 2569 for (mcidx = d->firstchan; mcidx < MC_CHANNELS; mcidx++) { 2570 /* Forbid CS interleaving if any of: 2571 - not requested 2572 - in large mem mode 2573 - CS 0 is absent */ 2574 if ((d->mc[mcidx].cfgcsint > 0) && 2575 !(d->mc[mcidx].flags & MCFLG_BIGMEM) && 2576 (d->mc[mcidx].csdata[0].flags & CS_PRESENT)) { 2577 2578 for (csidx = 1; csidx < MC_CHIPSELS; csidx++) { 2579 /* CS csidx must be present */ 2580 if (!(d->mc[mcidx].csdata[csidx].flags & CS_PRESENT)) break; 2581 /* CS csidx must match geometry of CS 0 */ 2582 if (d->mc[mcidx].csdata[0].rows != d->mc[mcidx].csdata[csidx].rows) 2583 break; 2584 if (d->mc[mcidx].csdata[0].cols != d->mc[mcidx].csdata[csidx].cols) 2585 break; 2586 if (d->mc[mcidx].csdata[0].banks != 2587 d->mc[mcidx].csdata[csidx].banks) 2588 break; 2589 } 2590 /* csidx = 1st CS index that can't be interleaved; 2591 Convert csidx to a number of CS interleave address bits */ 2592 csint = csidx >> 1; 2593 /* Cap csint by the csinterleave attribute on the channel */ 2594 if (csint > d->mc[mcidx].cfgcsint) { 2595 csint = d->mc[mcidx].cfgcsint; 2596 } 2597 /* Forbid CS interleaving into the hole in the memory address 2598 space; i,e., cap the port-and-CS-interleaved CS size at 1 GB. 2599 Remove this code when sb1250_dram_intlv() can deal with CS 2600 sizes that span the hole. */ 2601 { 2602 int addr_bits = 30; /* 1 GB */ 2603 addr_bits -= 3; /* 8 byte data bus width */ 2604 addr_bits -= d->mc[mcidx].csdata[0].rows; 2605 addr_bits -= d->mc[mcidx].csdata[0].cols; 2606 addr_bits -= d->mc[mcidx].csdata[0].banks; 2607 if (d->flags & M_MCINIT_PINTLV) addr_bits -= 1; 2608 if (addr_bits < 0) addr_bits = 0; 2609 if (addr_bits < csint) csint = addr_bits; 2610 } 2611 /* Return csint to caller */ 2612 d->mc[mcidx].csint = csint; 2613 } 2614 } 2615} 2616 2617 2618 2619 2620#if !defined(_MCSTANDALONE_) /* When not linked into firmware, no RAM zeroing */ 2621 2622/* ********************************************************************* 2623 * SB1250_DRAM_ZERO1MB(d,addr) 2624 * 2625 * Zero one megabyte of memory starting at the specified address. 2626 * 'addr' is in megabytes. 2627 * 2628 * Input parameters: 2629 * d - initdata structure 2630 * addr - starting address, expressed as a megabyte index 2631 * 2632 * Return value: 2633 * nothing 2634 ********************************************************************* */ 2635 2636#ifndef _DMZERO_ 2637static void sb1250_dram_zero1mb(initdata_t *d,uint64_t addr) 2638{ 2639 __asm(" .set push ; .set noreorder ; .set mips64 ; " 2640 " mfc0 $9,$12 ; " 2641 " ori $8,$9,0x80 ; " 2642 " mtc0 $8,$12 ; " 2643 " bnel $0,$0,.+4 ; " 2644 " ssnop ; " 2645 " lui $10,0xB800 ; " 2646 " dsll32 $10,$10,0 ; " 2647 " dsll $12,%0,20 ;" 2648 " or $10,$10,$12 ; " 2649 " lui $11,0x10 ; " 2650 "ClrLoop: " 2651 " sd $0,0($10) ; " 2652 " sd $0,8($10) ; " 2653 " sd $0,16($10) ; " 2654 " sd $0,24($10) ; " 2655 " sd $0,32($10) ; " 2656 " sd $0,40($10) ; " 2657 " sd $0,48($10) ; " 2658 " sd $0,56($10) ; " 2659 " sub $11,$11,64 ; " 2660 " bne $11,$0,ClrLoop ; " 2661 " dadd $10,64 ; " 2662 " mtc0 $9,$12 ; " 2663 " bnel $0,$0,.+4 ;" 2664 " ssnop ; " 2665 " .set pop" 2666 : : "r"(addr) : "$8","$9","$10","$11","$12"); 2667} 2668 2669 2670/* ********************************************************************* 2671 * SB1250_DRAM_ZERO1MB(d,addr) 2672 * 2673 * Zero one megabyte of memory starting at the specified address. 2674 * 'addr' is in megabytes. 2675 * 2676 * Input parameters: 2677 * d - initdata structure 2678 * addr - starting address, expressed as a megabyte index 2679 * 2680 * Return value: 2681 * nothing 2682 ********************************************************************* */ 2683 2684#ifdef _DMZERO_ 2685static void sb1250_dram_zero1mb(initdata_t *d,uint64_t addr) 2686{ 2687 sbport_t dmreg; 2688 uint64_t baseaddr; 2689 volatile int idx; 2690 2691 /* 2692 * Build the descriptor 2693 */ 2694 2695 d->dscr[0] = (addr << 20) | 2696 M_DM_DSCRA_ZERO_MEM | 2697 M_DM_DSCRA_UN_DEST | M_DM_DSCRA_UN_SRC | 2698 V_DM_DSCRA_DIR_SRC_CONST | 2699 V_DM_DSCRA_DIR_DEST_INCR; 2700 d->dscr[1] = V_DM_DSCRB_SRC_LENGTH(0); 2701 2702 /* Flush the descriptor out. We need to do this in Pass1 2703 because we're in cacheable noncoherent mode right now and 2704 the core will not respond to the DM's request for the descriptor. */ 2705 2706 __asm __volatile ("cache 0x15,0(%0) ; " :: "r"(d)); 2707 2708 /* 2709 * Give the descriptor to the data mover 2710 */ 2711 2712 dmreg = PHYS_TO_K1(A_DM_REGISTER(0,R_DM_DSCR_BASE)); 2713 baseaddr = (uint64_t) K0_TO_PHYS((long)d->dscr) | 2714 V_DM_DSCR_BASE_PRIORITY(0) | 2715 V_DM_DSCR_BASE_RINGSZ(4) | 2716 M_DM_DSCR_BASE_ENABL | 2717 M_DM_DSCR_BASE_RESET; 2718 WRITECSR(dmreg,baseaddr); 2719 2720 dmreg = PHYS_TO_K1(A_DM_REGISTER(0,R_DM_DSCR_COUNT)); 2721 WRITECSR(dmreg,1); 2722 2723 /* 2724 * Wait for the request to complete 2725 */ 2726 2727 while ((READCSR(dmreg) & 0xFFFF) > 0) { 2728 /* Do something that doesn't involve the ZBBus to give 2729 the DM some extra time */ 2730 for (idx = 0; idx < 10000; idx++) ; /* NULL LOOP */ 2731 } 2732 2733} 2734#endif 2735 2736 2737/* ********************************************************************* 2738 * SB1250_DRAM_ZERO(d) 2739 * 2740 * Zero memory, using the data mover. 2741 * 2742 * Input parameters: 2743 * d - initdata structure 2744 * 2745 * Return value: 2746 * nothing 2747 ********************************************************************* */ 2748static void sb1250_dram_zero(initdata_t *d) 2749{ 2750 int idx; 2751 int maxmem; 2752 uint64_t curmb; /* current address in megabytes */ 2753 2754 maxmem = (int) (d->ttlbytes >> 20); 2755 curmb = 0; 2756 2757 for (idx = 0; idx < (int) maxmem; idx++) { 2758 sb1250_dram_zero1mb(d,curmb); 2759 curmb++; 2760 if (curmb == (REGION0_LOC+REGION0_SIZE)) curmb = REGION1_LOC; 2761 else if (curmb == (REGION1_LOC+REGION1_SIZE)) curmb = REGION2_LOC; 2762 else if (curmb == (REGION2_LOC+REGION2_SIZE)) curmb = REGION3_LOC; 2763 } 2764} 2765 2766#endif 2767 2768#endif 2769 2770/* ********************************************************************* 2771 * SB1250_DRAM_INIT() 2772 * 2773 * Initialize DRAM connected to the specified DRAM controller 2774 * The DRAM will be configured without interleaving, as sequential 2775 * blocks of memory. 2776 * 2777 * Input parameters: 2778 * a0 - zero to use default memconfig table 2779 * or KSEG1 address of mem config table 2780 * 2781 * Return value: 2782 * v0 - total amount of installed DRAM 2783 * 2784 * Registers used: 2785 * all 2786 ********************************************************************* */ 2787 2788uint64_t sb1250_dram_init_real(const draminittab_t *init,initdata_t *d); 2789uint64_t sb1250_dram_init_real(const draminittab_t *init,initdata_t *d) 2790{ 2791 uint64_t reg; 2792 sbport_t mcbase; 2793 uint64_t cfgbits; 2794 int mcidx; 2795 int csidx; 2796 int dramtype; 2797 csdata_t *tdata; 2798 mcdata_t *mc; 2799 uint32_t *d32; 2800 int idx; 2801 const draminittab_t *init_11xx; 2802 const draminittab_t *init_12xx; 2803 2804#if !defined(_MCSTANDALONE_) 2805#if CFG_EMBEDDED_PIC 2806 __asm(".set push ; .set noreorder ; " 2807 " bal LoadREL1 ; " 2808 " nop ; " 2809 "LoadREL1: la %0,draminittab_11xx-LoadREL1 ; " 2810 " add %0,$31 ; " 2811 " .set pop " 2812 : "=r"(init_11xx) :: "$31"); 2813 2814 __asm(".set push ; .set noreorder ; " 2815 " bal LoadREL2 ; " 2816 " nop ; " 2817 "LoadREL2: la %0,draminittab_12xx-LoadREL2 ; " 2818 " add %0,$31 ; " 2819 " .set pop " 2820 : "=r"(init_12xx) :: "$31"); 2821#else 2822 init_11xx = (draminittab_t *) draminittab_11xx; 2823 init_12xx = (draminittab_t *) draminittab_12xx; 2824#endif 2825#endif 2826 2827 /* 2828 * Zero the entire initdata structure 2829 */ 2830 2831 d32 = (uint32_t *) d; 2832 for (idx = 0; idx < sizeof(initdata_t)/sizeof(uint32_t); idx++) { 2833 *d32++ = 0; 2834 } 2835 2836 /* 2837 * Determine system SOC type so we will know what channels 2838 * to initialize. The hybrid parts have 1250s inside, 2839 * so even though there are only pins for 1 channel the 2840 * registers are there for both, so we need to initialize them. 2841 * The "real" 1125s only have one channel. 2842 */ 2843 2844 cfgbits = READCSR(PHYS_TO_K1(A_SCD_SYSTEM_REVISION)); 2845 d->soctype = SYS_SOC_TYPE(cfgbits); 2846 2847 switch (d->soctype) { 2848 case K_SYS_SOC_TYPE_BCM1120: 2849 case K_SYS_SOC_TYPE_BCM1125: 2850 d->firstchan = 1; 2851#if !defined(_MCSTANDALONE_) 2852 if (!init) init = init_11xx; 2853#endif 2854 break; 2855 2856 case K_SYS_SOC_TYPE_BCM1250: 2857 case K_SYS_SOC_TYPE_BCM1125H: 2858 default: 2859 d->firstchan = 0; 2860#if !defined(_MCSTANDALONE_) 2861 if (!init) init = init_12xx; 2862#endif 2863 } 2864 2865 /* 2866 * Begin by initializing the memory channels to some known state. 2867 * Set the "BERR_DISABLE" bit for now while we initialize the channels, 2868 * this will be cleared again before the routine exits. 2869 */ 2870 2871#ifdef _MCSTANDALONE_NOISY_ 2872 printf("DRAM: Initializing memory controller.\n"); 2873#endif 2874 2875 for (mcidx = d->firstchan; mcidx < MC_CHANNELS; mcidx++) { 2876 mcbase = PHYS_TO_K1(A_MC_BASE(mcidx)); 2877 2878 WRITECSR(mcbase+R_MC_CONFIG,V_MC_CONFIG_DEFAULT | M_MC_ECC_DISABLE | 2879 V_MC_CS_MODE_MSB_CS | M_MC_BERR_DISABLE); 2880 WRITECSR(mcbase+R_MC_CS_START,0); 2881 WRITECSR(mcbase+R_MC_CS_END,0); 2882 WRITECSR(mcbase+R_MC_CS_INTERLEAVE,0); 2883 WRITECSR(mcbase+R_MC_CS_ATTR,0); 2884 WRITECSR(mcbase+R_MC_TEST_DATA,0); 2885 WRITECSR(mcbase+R_MC_TEST_ECC,0); 2886 } 2887 2888 /* 2889 * Read the parameters 2890 */ 2891 2892 sb1250_dram_readparams(d,init); 2893 2894 /* 2895 * Analyze parameters 2896 */ 2897 2898 sb1250_dram_analyze(d); 2899 2900 /* 2901 * Configure chip selects 2902 */ 2903 2904 if (d->flags & M_MCINIT_PINTLV) { 2905 sb1250_dram_intlv(d); 2906 cfgbits = V_MC_CHANNEL_SEL(d->pintbit); 2907 } 2908 else { 2909 sb1250_dram_msbcs(d); 2910 cfgbits = 0; 2911 } 2912 2913 /* 2914 * Okay, initialize the DRAM controller(s) 2915 */ 2916 2917 for (mcidx = d->firstchan; mcidx < MC_CHANNELS; mcidx++) { 2918 2919 uint64_t mc_cfgbits = cfgbits; 2920 2921 /* 2922 * Skip this controller if we did nothing 2923 */ 2924 if (!(d->inuse & (1 << mcidx))) continue; 2925 2926 /* 2927 * Get the base address of the controller 2928 */ 2929 mcbase = PHYS_TO_K1(A_MC_BASE(mcidx)); 2930 2931 /* 2932 * Get our MC data 2933 */ 2934 2935 mc = &(d->mc[mcidx]); 2936 2937 /* 2938 * Program the clock config register. This starts the clock to the 2939 * SDRAMs. Need to wait 200us after doing this. (6.4.6.1) 2940 * 2941 * Find the slowest chip/dimm among the chip selects on this 2942 * controller and use that for computing the timing values. 2943 */ 2944 2945 csidx = sb1250_find_timingcs(mc); 2946 if (csidx < 0) continue; /* should not happen */ 2947 2948 tdata = &(d->mc[mcidx].csdata[csidx]); /* remember for use below */ 2949 2950 if (mc->mantiming) { 2951 sb1250_manual_timing(mcidx,mc); 2952 } 2953 else { 2954 sb1250_auto_timing(mcidx,mc,tdata); 2955 } 2956 2957 DRAMINIT_DELAY(); 2958 2959 /* 2960 * Set up the memory controller config and timing registers. 2961 */ 2962 2963 switch(mc->csint) { 2964 case 0: mc_cfgbits |= V_MC_CS_MODE_MSB_CS; break; 2965 case 1: mc_cfgbits |= V_MC_CS_MODE_MIXED_CS_32; break; 2966 case 2: mc_cfgbits |= V_MC_CS_MODE_INTLV_CS; break; 2967 } 2968 2969 mc_cfgbits |= V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | 2970 V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | 2971 V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | 2972 V_MC_QUEUE_SIZE_DEFAULT; 2973 2974 /* Give IOB1 priority (config bit is only on channel 1) */ 2975 2976 if (mcidx == 1) mc_cfgbits |= M_MC_IOB1HIGHPRIORITY; 2977 2978 WRITECSR(mcbase+R_MC_CONFIG,mc_cfgbits | M_MC_ECC_DISABLE | M_MC_BERR_DISABLE); 2979 2980 2981 dramtype = d->mc[mcidx].dramtype; 2982 2983 /* 2984 * Set the page policy 2985 */ 2986 2987 WRITECSR(mcbase+R_MC_CS_ATTR, 2988 V_MC_CS0_PAGE(mc->pagepolicy) | 2989 V_MC_CS1_PAGE(mc->pagepolicy) | 2990 V_MC_CS2_PAGE(mc->pagepolicy) | 2991 V_MC_CS3_PAGE(mc->pagepolicy)); 2992 2993 /* 2994 * Okay, now do the following sequence: 2995 * PRE-EMRS-MRS-PRE-AR-AR-MRS. Do this for each chip select, 2996 * one at a time for each enabled chip select. 2997 */ 2998 2999 for (csidx = 0; csidx < MC_CHIPSELS; csidx++) { 3000 if (mc->csdata[csidx].flags & CS_PRESENT) { 3001 3002 switch (dramtype) { 3003 case JEDEC: 3004 if (mc->flags & MCFLG_BIGMEM) { 3005 sb1250_jedec_initcmds(mcidx,mc,csidx,0,tdata); 3006 sb1250_jedec_initcmds(mcidx,mc,csidx,1,tdata); 3007 sb1250_jedec_initcmds(mcidx,mc,csidx,2,tdata); 3008 sb1250_jedec_initcmds(mcidx,mc,csidx,3,tdata); 3009 /* 3010 * If in "big memory mode" turn on the "external decode" 3011 * switch here. We never turn it off. 3012 */ 3013 3014 if (mc->flags & MCFLG_BIGMEM) { 3015 sbport_t port; 3016 port = PHYS_TO_K1(A_MC_REGISTER(mcidx,R_MC_DRAMMODE)); 3017 WRITECSR(port,M_MC_EXTERNALDECODE); 3018 } 3019 } 3020 else { 3021 sb1250_jedec_initcmds(mcidx,mc,csidx,0,tdata); 3022 } 3023 break; 3024 case SGRAM: 3025 sb1250_sgram_initcmds(mcidx,mc,csidx,tdata); 3026 break; 3027 case FCRAM: 3028 sb1250_fcram_initcmds(mcidx,mc,csidx,tdata); 3029 break; 3030 default: 3031#ifdef _MCSTANDALONE_NOISY_ 3032 printf("DRAM: Channel DRAM type declared as DRAM_TYPE_SPD, but no SPD DRAM type found.\n"); 3033#endif 3034 break; 3035 } 3036 3037 } 3038 } 3039 3040 /* 3041 * Kill the BERR_DISABLE bit for this controller 3042 */ 3043 3044 reg = READCSR(mcbase+R_MC_CONFIG); 3045 reg &= ~M_MC_BERR_DISABLE; 3046 WRITECSR(mcbase+R_MC_CONFIG,reg); 3047 } 3048 3049#if !defined(_MCSTANDALONE_) 3050 /* 3051 * Zero the contents of memory to set the ECC bits correctly. 3052 * Do it for all memory if either channel is enabled for ECC. 3053 */ 3054 3055 for (mcidx = d->firstchan; mcidx < MC_CHANNELS; mcidx++) { 3056 if (!(d->inuse & (1 << mcidx))) continue; 3057 if (d->mc[mcidx].flags & MCFLG_ECC_ENABLE) { 3058 sb1250_dram_zero(d); 3059 break; 3060 } 3061 } 3062#endif 3063 3064 /* 3065 * Turn on the ECC in the memory controller for those channels 3066 * that we've specified. 3067 */ 3068 3069 for (mcidx = d->firstchan; mcidx < MC_CHANNELS; mcidx++) { 3070 if (!(d->inuse & (1 << mcidx))) continue; 3071 if (!(d->mc[mcidx].flags & MCFLG_ECC_ENABLE)) continue; /* ecc not enabled */ 3072 mcbase = PHYS_TO_K1(A_MC_BASE(mcidx)); 3073 reg = READCSR(mcbase+R_MC_CONFIG); 3074 reg &= ~M_MC_ECC_DISABLE; 3075 WRITECSR(mcbase+R_MC_CONFIG,reg); 3076 } 3077 3078 /* 3079 * Return the total amount of memory initialized, in megabytes 3080 */ 3081 3082#ifdef _MCSTANDALONE_NOISY_ 3083 printf("DRAM: Total memory: %dMB.\n",(unsigned int)(d->ttlbytes >> 20)); 3084#endif 3085 3086 return (d->ttlbytes >> 20); 3087} 3088 3089 3090/* ********************************************************************* 3091 * XXSB1250_DRAMINIT() 3092 * 3093 * This is a hideous hack. To help keep things all in one module, 3094 * and to aid in relocation (remember, it's tough to do a 3095 * PC-relative branch to an external symbol), here is an 3096 * assembly stub to get things ready to call the above C routine. 3097 * We turn off the bus errors on both memory controllers, set up 3098 * a small stack, and branch to the C routine to handle the rest. 3099 * 3100 * Input parameters: 3101 * register a0 - user initialization table 3102 * 3103 * Return value: 3104 * register v0 - size of memory, in bytes 3105 ********************************************************************* */ 3106 3107#if !defined(_MCSTANDALONE_) 3108static void __attribute__ ((unused)) xxsb1250_draminit(const draminittab_t *init) 3109{ 3110 __asm(" .globl sb1250_dram_init ; " 3111 "sb1250_dram_init: ; " 3112 " dli $10,0x30158A00C9800000 ; " /* Set the BERR_DISABLE bits */ 3113 " lui $8,0xb005 ; " /* and ECC_DISABLE bits */ 3114 " sd $10,0x1100($8) ; " /* do MC 0 */ 3115 " sd $10,0x2100($8) ; " /* do MC 1 */ 3116#ifdef _VERILOG_ 3117 " li $29,0x9FFFFFF0 ; " /* Set up a stack pointer */ 3118 " li $5,0x9FFFFC00 ; " /* Pass pointer to data area */ 3119#else 3120 " li $29,0x80000400 ; " /* Set up a stack pointer */ 3121 " li $5,0x80000000 ; " /* Pass pointer to data area */ 3122#endif 3123 " b sb1250_dram_init_real ; "); /* Branch to real init routine */ 3124 3125} 3126 3127#else /* _MCSTANDALONE_ */ 3128 3129/* 3130 * SOCVIEW and non-CFE, non-MIPS things don't need any magic since they 3131 * are not running on the 1250. Just call the main routine. 3132 */ 3133uint64_t sb1250_dram_init(const draminittab_t *init,initdata_t *d) 3134{ 3135 initdata_t initdata; 3136 return sb1250_dram_init_real(init,&initdata); 3137} 3138#endif 3139 3140 3141/* ********************************************************************* 3142 * End (yes, 3000 lines of memory controller init code. Sheesh!) 3143 ********************************************************************* */ 3144