1 2 3/* 4 * I/O Address assignments for the PTSWARM board 5 * 6 * Summary of address map: 7 * 8 * Address Size CSel Description 9 * --------------- ---- ------ -------------------------------- 10 * 0x1FC00000 16MB CS0 Boot ROM 11 * 0x1CC00000 2MB CS1 Alternate boot ROM 12 * 0x1B000000 64KB CS2 External UART 13 * 0x1B0A0000 64KB CS3 LED display 14 * CS4 Unused 15 * CS5 Unused 16 * CS6 Unused 17 * CS7 Unused 18 * 19 * GPIO assignments 20 * 21 * GPIO# Direction Description 22 * ------- --------- ------------------------------------------ 23 * GPIO0 Output Debug LED 24 * GPIO1 Input UART interrupt (interrupt) 25 * GPIO2 Input PHY interrupt (interrupt) 26 * GPIO3 N/A fpga interface 27 * GPIO4 N/A fpga interface 28 * GPIO5 Input Temperature Sensor Alert (interrupt) 29 * GPIO6 N/A fpga interface 30 * GPIO7 N/A fpga interface 31 * GPIO8 N/A fpga interface 32 * GPIO9 N/A fpga interface 33 * GPIO10 N/A fpga interface 34 * GPIO11 N/A fpga interface 35 * GPIO12 N/A fpga interface 36 * GPIO13 N/A fpga interface 37 * GPIO14 N/A fpga interface 38 * GPIO15 N/A fpga interface 39 */ 40 41/* ********************************************************************* 42 * Macros 43 ********************************************************************* */ 44 45#define MB (1024*1024) 46#define K64 65536 47#define NUM64K(x) (((x)+(K64-1))/K64) 48 49 50/* ********************************************************************* 51 * GPIO pins 52 ********************************************************************* */ 53 54#define GPIO_DEBUG_LED 0 55#define GPIO_UART_INT 1 56#define GPIO_PHY_INT 2 57#define GPIO_TEMP_SENSOR_INT 5 58 59#define M_GPIO_DEBUG_LED _SB_MAKEMASK1(GPIO_DEBUG_LED) 60 61#define GPIO_OUTPUT_MASK (_SB_MAKEMASK1(GPIO_DEBUG_LED)) 62 63#define GPIO_INTERRUPT_MASK ((V_GPIO_INTR_TYPEX(GPIO_PHY_INT,K_GPIO_INTR_LEVEL)) | \ 64 (V_GPIO_INTR_TYPEX(GPIO_UART_INT,K_GPIO_INTR_LEVEL))| \ 65 (V_GPIO_INTR_TYPEX(GPIO_TEMP_SENSOR_INT,K_GPIO_INTR_LEVEL))) 66 67 68/* ********************************************************************* 69 * Generic Bus 70 ********************************************************************* */ 71 72/* 73 * Boot ROM: Using default parameters until CFE has been copied from 74 * ROM to RAM and is executing in RAM 75 */ 76#define BOOTROM_CS 0 77#define BOOTROM_SIZE NUM64K(16*MB) /* size of boot ROM */ 78#define BOOTROM_PHYS 0x1FC00000 /* address of boot ROM (CS0) */ 79#define BOOTROM_NCHIPS 8 80#define BOOTROM_CHIPSIZE 2*MB 81 82 83#define ALT_BOOTROM_CS 1 84#define ALT_BOOTROM_PHYS 0x1CC00000 /* address of alternate boot ROM (CS1) */ 85#define ALT_BOOTROM_SIZE NUM64K(2*MB) /* size of alternate boot ROM */ 86#define ALT_BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 87 V_IO_ALE_TO_CS(2) | \ 88 V_IO_CS_WIDTH(24) | \ 89 V_IO_RDY_SMPLE(1) 90#define ALT_BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 91 V_IO_WRITE_WIDTH(7) | \ 92 V_IO_IDLE_CYCLE(6) | \ 93 V_IO_CS_TO_OE(0) | \ 94 V_IO_OE_TO_CS(0) 95#define ALT_BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 96#define ALT_BOOTROM_NCHIPS 1 97#define ALT_BOOTROM_CHIPSIZE 2*MB 98 99/* 100 * External UART: non-multiplexed, byte width, no parity, no ack 101 */ 102#define UART_CS 2 103#define UART_PHYS 0x1B000000 /* address of UART (CS2) */ 104#define UART_SIZE NUM64K(8) /* size allocated for UART access. minimum is 64KB */ 105#define UART_TIMING0 V_IO_ALE_WIDTH(4) | \ 106 V_IO_ALE_TO_CS(2) | \ 107 V_IO_CS_WIDTH(24) | \ 108 V_IO_RDY_SMPLE(1) 109#define UART_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 110 V_IO_WRITE_WIDTH(7) | \ 111 V_IO_IDLE_CYCLE(6) | \ 112 V_IO_CS_TO_OE(0) | \ 113 V_IO_OE_TO_CS(0) 114#define UART_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 115 116/* 117 * LEDs: non-multiplexed, byte width, no parity, no ack 118 */ 119#define LEDS_CS 3 120#define LEDS_PHYS 0x1B0A0000 121#define LEDS_SIZE NUM64K(4) 122#define LEDS_TIMING0 V_IO_ALE_WIDTH(4) | \ 123 V_IO_ALE_TO_CS(2) | \ 124 V_IO_CS_WIDTH(13) | \ 125 V_IO_RDY_SMPLE(1) 126#define LEDS_TIMING1 V_IO_ALE_TO_WRITE(2) | \ 127 V_IO_WRITE_WIDTH(8) | \ 128 V_IO_IDLE_CYCLE(6) | \ 129 V_IO_CS_TO_OE(0) | \ 130 V_IO_OE_TO_CS(0) 131#define LEDS_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 132 133 134/* ********************************************************************* 135 * SMBus Devices 136 ********************************************************************* */ 137 138#define TEMPSENSOR_SMBUS_CHAN 0 139#define TEMPSENSOR_SMBUS_DEV 0x2A 140#define DRAM_SMBUS_CHAN 0 141#define DRAM_SMBUS_DEV 0x54 142#define BIGEEPROM_SMBUS_CHAN 0 143#define BIGEEPROM_SMBUS_DEV 0x50 144#define X1240_SMBUS_CHAN 1 145#define X1240_SMBUS_DEV 0x50 146