1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Lausanne Definitions File: lausanne.h 5 * 6 * This file contains I/O, chip select, and GPIO assignments 7 * for the Lausanne checkout board. 8 * 9 * Author: Mitch Lichtenberg (mpl@broadcom.com) 10 * Edits for Lausanne: Jeffrey Cheng (chengj@broadcom.com) 11 * 12 ********************************************************************* 13 * 14 * Copyright 2000,2001,2002,2003 15 * Broadcom Corporation. All rights reserved. 16 * 17 * This software is furnished under license and may be used and 18 * copied only in accordance with the following terms and 19 * conditions. Subject to these conditions, you may download, 20 * copy, install, use, modify and distribute modified or unmodified 21 * copies of this software in source and/or binary form. No title 22 * or ownership is transferred hereby. 23 * 24 * 1) Any source code used, modified or distributed must reproduce 25 * and retain this copyright notice and list of conditions 26 * as they appear in the source file. 27 * 28 * 2) No right is granted to use any trade name, trademark, or 29 * logo of Broadcom Corporation. The "Broadcom Corporation" 30 * name may not be used to endorse or promote products derived 31 * from this software without the prior written permission of 32 * Broadcom Corporation. 33 * 34 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 35 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 36 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 37 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 38 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 39 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 41 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 42 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 43 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 44 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 45 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 46 * THE POSSIBILITY OF SUCH DAMAGE. 47 ********************************************************************* */ 48 49 50/* 51 * I/O Address assignments for the LAUSANNE board 52 * 53 * Summary of address map: 54 * 55 * Address Size CSel Description 56 * --------------- ---- ------ -------------------------------- 57 * 0x1FC00000 2MB CS0 Boot ROM 58 * 0x1F800000 2MB CS1 Alternate boot ROM 59 * 0x100B0000 64KB CS2 CPLD 60 * 0x100A0000 64KB CS3 LED display 61 * CS4 Unused 62 * CS5 Unused 63 * CS6 Unused 64 * CS7 Unused 65 * 66 * GPIO assignments 67 * 68 * GPIO# Direction Description 69 * ------- --------- ------------------------------------------ 70 * GPIO0 N/A Test point 71 * GPIO1 N/A Test point 72 * GPIO2 Input PHY Interrupt (interrupt) 73 * GPIO3 Input Nonmaskable Interrupt (interrupt) 74 * GPIO4 N/A Test point 75 * GPIO5 Input Temperature Sensor Alert (interrupt) 76 * GPIO6 N/A CPLD 77 * GPIO7 N/A CPLD 78 * GPIO8 N/A CPLD 79 * GPIO9 Input Boot Select 80 * GPIO10 N/A Test point 81 * GPIO11 N/A Test point 82 * GPIO12 N/A Test point 83 * GPIO13 N/A Test point 84 * GPIO14 N/A Test point 85 * GPIO15 Output Flash Byte Enable 86 */ 87 88/* ********************************************************************* 89 * Macros 90 ********************************************************************* */ 91 92#define MB (1024*1024) 93#define K64 65536 94#define NUM64K(x) (((x)+(K64-1))/K64) 95 96 97/* ********************************************************************* 98 * GPIO pins 99 ********************************************************************* */ 100 101#define GPIO_PHY_INTERRUPT 2 102#define GPIO_NONMASKABLE_INT 3 103#define GPIO_TEMP_SENSOR_INT 5 104#define GPIO_BOOT_SELECT 9 105#define GPIO_FLASH_BYTE_EN 15 106 107#define GPIO_OUTPUT_MASK (_SB_MAKE64(GPIO_FLASH_BYTE_EN)) 108#define GPIO_INTERRUPT_MASK (V_GPIO_INTR_TYPEX(GPIO_PHY_INTERRUPT,K_GPIO_INTR_LEVEL)) 109 110 111/* ********************************************************************* 112 * Generic Bus 113 ********************************************************************* */ 114 115#define BOOTROM_CS 0 116#define BOOTROM_PHYS 0x1FC00000 /* address of boot ROM (CS0) */ 117#define BOOTROM_SIZE NUM64K(4*MB) /* size of boot ROM */ 118#define BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 119 V_IO_ALE_TO_CS(2) | \ 120 V_IO_CS_WIDTH(24) | \ 121 V_IO_RDY_SMPLE(1) 122#define BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 123 V_IO_WRITE_WIDTH(7) | \ 124 V_IO_IDLE_CYCLE(6) | \ 125 V_IO_CS_TO_OE(0) | \ 126 V_IO_OE_TO_CS(0) 127#define BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 128 129#define ALT_BOOTROM_CS 1 130#define ALT_BOOTROM_PHYS 0x1EC00000 /* address of alternate boot ROM (CS1) */ 131#define ALT_BOOTROM_SIZE NUM64K(16*MB) /* size of alternate boot ROM */ 132#define ALT_BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 133 V_IO_ALE_TO_CS(2) | \ 134 V_IO_CS_WIDTH(24) | \ 135 V_IO_RDY_SMPLE(1) 136#define ALT_BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 137 V_IO_WRITE_WIDTH(7) | \ 138 V_IO_IDLE_CYCLE(6) | \ 139 V_IO_CS_TO_OE(0) | \ 140 V_IO_OE_TO_CS(0) 141#define ALT_BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 142 143/* 144 * CPLD: multiplexed, byte width [io_ad7:io_ad0], no parity, no ack 145 * See documentation: /home/chengj/systems/cpld/lausanne/Chksum.doc 146 */ 147#define CPLD_CS 2 148#define CPLD_PHYS 0x1D0B0000 149#define CPLD_SIZE NUM64K(256) 150#define CPLD_TIMING0 V_IO_ALE_WIDTH(3) | \ 151 V_IO_ALE_TO_CS(1) | \ 152 V_IO_CS_WIDTH(8) | \ 153 V_IO_RDY_SMPLE(2) 154#define CPLD_TIMING1 V_IO_ALE_TO_WRITE(4) | \ 155 V_IO_WRITE_WIDTH(7) | \ 156 V_IO_IDLE_CYCLE(1) | \ 157 V_IO_CS_TO_OE(0) | \ 158 V_IO_OE_TO_CS(0) 159#define CPLD_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1L) 160 161 162/* 163 * LEDs: non-multiplexed, byte width, no parity, no ack 164 */ 165#define LEDS_CS 3 166#define LEDS_PHYS 0x1D0A0000 167#define LEDS_SIZE NUM64K(4) 168#define LEDS_TIMING0 V_IO_ALE_WIDTH(4) | \ 169 V_IO_ALE_TO_CS(2) | \ 170 V_IO_CS_WIDTH(13) | \ 171 V_IO_RDY_SMPLE(1) 172#define LEDS_TIMING1 V_IO_ALE_TO_WRITE(2) | \ 173 V_IO_WRITE_WIDTH(8) | \ 174 V_IO_IDLE_CYCLE(6) | \ 175 V_IO_CS_TO_OE(0) | \ 176 V_IO_OE_TO_CS(0) 177#define LEDS_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 178 179 180 181 182/* ********************************************************************* 183 * SMBus Devices 184 ********************************************************************* */ 185 186#define TEMPSENSOR_SMBUS_CHAN 1 187#define TEMPSENSOR_SMBUS_DEV 0x2A 188#define DRAM_SMBUS_CHAN 0 189#define DRAM_SMBUS_DEV 0x50 190/* The SMBus eeprom is on channel 1 for lausanne */ 191#define BIGEEPROM_SMBUS_CHAN 1 192#define BIGEEPROM_SMBUS_DEV 0x50 193 194/* 195 * REV2 definitions 196 */ 197 198#include "sb1250_pass2.h" 199