1/*************************************************************************** 2 * Copyright (c) 1999-2011, Broadcom Corporation 3 * All Rights Reserved 4 * Confidential Property of Broadcom Corporation 5 * 6 * 7 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 8 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 9 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 10 * 11 * $Id:: ddr40_phy_registers.h 1306 2012-06-21 14:10:10Z jeung $: 12 * $Rev::file = : Global SVN Revision = 1780 $: 13 * 14 * $brcm_Workfile: $ 15 * $brcm_Revision: $ 16 * $brcm_Date: $ 17 * 18 * Module Description: 19 * DO NOT EDIT THIS FILE DIRECTLY 20 * 21 * This module was generated magically with RDB from a source description 22 * file. You must edit the source file for changes to be made to this file. 23 * 24 * 25 * Date: Generated on Tue Aug 2 10:02:05 2011 26 * MD5 Checksum 2190b2b118cb06ca862485cf3f9b3073 27 * 28 * Compiled with: RDB Utility combo_header.pl 29 * RDB Parser 3.0 30 * unknown unknown 31 * Perl Interpreter 5.008008 32 * Operating System linux 33 * 34 * Spec Versions: DDR40_PHY_ADDR_CTL 3 35 * DDR40_PHY_WORD_LANE 04 36 * 37 * RDB Files: /projects/DDR40_4/work/ebleich/phy_d0/design/ddr40_phy/top_32_fc_40lp/rdb/ddr40_phy_top_standalone.rdb 38 * /projects/DDR40_4/work/ebleich/phy_d0/design/ddr40_phy/top_32_fc_40lp/rdb/ddr40_phy_top_blockdef.rdb 39 * /projects/DDR40_4/work/ebleich/phy_d0/design/ddr40_phy/top_32_fc_40lp/rdb/ddr40_phy_addr_ctl.rdb 40 * /projects/DDR40_4/work/ebleich/phy_d0/design/ddr40_phy/top_32_fc_40lp/rdb/ddr40_phy_word_lane.rdb 41 * 42 * Revision History: 43 * 44 * $brcm_Log: $ 45 * 46 ***************************************************************************/ 47 48/* FILE-CSTYLED */ 49 50#ifndef DDR40_PHY_REGISTERS_H__ 51#define DDR40_PHY_REGISTERS_H__ 52 53/** 54 * m = memory, c = core, r = register, f = field, d = data. 55 */ 56#if !defined(GET_FIELD) && !defined(SET_FIELD) 57#define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 58#define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 59#define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 60#define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 61 62#define GET_FIELD(m,c,r,f) \ 63 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 64 65#define SET_FIELD(m,c,r,f,d) \ 66 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 67 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 68 ) 69 70#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 71#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 72#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 73 74#endif /* GET & SET */ 75 76/*************************************************************************** 77 *DDR40_CORE_PHY_CONTROL_REGS - DDR40 CORE DDR40 physical interface control registers 78 ***************************************************************************/ 79#define DDR40_CORE_PHY_CONTROL_REGS_REVISION 0x00000000 /* Address & Control revision register */ 80#define DDR40_CORE_PHY_CONTROL_REGS_CLK_PM_CTRL 0x00000004 /* PHY clock power management control register */ 81#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS 0x00000010 /* PHY PLL status register */ 82#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG 0x00000014 /* PHY PLL configuration register */ 83#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL 0x00000018 /* PHY PLL control register */ 84#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS 0x0000001c /* PHY PLL dividers control register */ 85#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL 0x00000020 /* Aux Control register */ 86#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL 0x00000030 /* Address & Control coarse VDL static override control register */ 87#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL 0x00000034 /* Address & Control fine VDL static override control register */ 88#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x00000038 /* Idle mode SSTL pad control register */ 89#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL 0x0000003c /* PVT Compensation control and status register */ 90#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x00000040 /* SSTL pad drive characteristics control register */ 91#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS 0x00000044 /* PHY Auto Init rd_data_dly result register */ 92#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE 0x00000048 /* PHY VDL calibration control register */ 93#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS 0x0000004c /* PHY VDL calibration status register */ 94#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS 0x00000050 /* PHY DQ VDL calibration status register */ 95#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS 0x00000054 /* PHY Write Channel VDL calibration status register */ 96#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS 0x00000058 /* PHY Read Enable VDL calibration status register */ 97#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL 0x0000005c /* Virtual VTT Control and Status register */ 98#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS 0x00000060 /* Virtual VTT Control and Status register */ 99#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS 0x00000064 /* Virtual VTT Connections register */ 100#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE 0x00000068 /* Virtual VTT Override register */ 101#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL 0x0000006c /* VREF DAC Control register */ 102#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL 0x00000070 /* PhyBist Control Register */ 103#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_SEED 0x00000074 /* PhyBist Seed Register */ 104#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS 0x00000078 /* PhyBist General Status Register */ 105#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS 0x0000007c /* PhyBist Per-Bit Control Pad Status Register */ 106#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_DQ_STATUS 0x00000080 /* PhyBist Per-Bit DQ Pad Status Register */ 107#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS 0x00000084 /* PhyBist Per-Bit DM and CK Pad Status Register */ 108#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG 0x00000090 /* DRAM Command Register */ 109#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0 0x00000094 /* Mode Register 0 */ 110#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1 0x00000098 /* Mode Register 1 */ 111#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2 0x0000009c /* Mode Register 2 */ 112#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3 0x000000a0 /* Mode Register 3 */ 113#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL 0x000000a4 /* Standby Control register */ 114#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL 0x000000b0 /* Strap Control register */ 115#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2 0x000000b4 /* Strap Control register */ 116#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS 0x000000b8 /* Strap Status register */ 117#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2 0x000000bc /* Strap Status register */ 118#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE 0x000000c0 /* Freeze-on-error enable register */ 119 120/*************************************************************************** 121 *DDR40_CORE_PHY_WORD_LANE_0 - DDR40 CORE DDR40 word lane #0 control registers 122 ***************************************************************************/ 123#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN 0x00000200 /* Read Enable Byte VDL static override control register */ 124#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W 0x00000204 /* Write Byte VDL static override control register */ 125#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P 0x00000208 /* Read Byte DQSP VDL static override control register */ 126#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N 0x0000020c /* Read Byte DQSN VDL static override control register */ 127#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W 0x00000210 /* Write Bit VDL static override control register */ 128#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W 0x00000214 /* Write Bit VDL static override control register */ 129#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W 0x00000218 /* Write Bit VDL static override control register */ 130#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W 0x0000021c /* Write Bit VDL static override control register */ 131#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W 0x00000220 /* Write Bit VDL static override control register */ 132#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W 0x00000224 /* Write Bit VDL static override control register */ 133#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W 0x00000228 /* Write Bit VDL static override control register */ 134#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W 0x0000022c /* Write Bit VDL static override control register */ 135#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W 0x00000230 /* Write Bit VDL static override control register */ 136#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x00000234 /* Read DQSP Bit VDL static override control register */ 137#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x00000238 /* Read DQSN Bit VDL static override control register */ 138#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x0000023c /* Read DQSP Bit VDL static override control register */ 139#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x00000240 /* Read DQSN Bit VDL static override control register */ 140#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x00000244 /* Read DQSP Bit VDL static override control register */ 141#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x00000248 /* Read DQSN Bit VDL static override control register */ 142#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x0000024c /* Read DQSP Bit VDL static override control register */ 143#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x00000250 /* Read DQSN Bit VDL static override control register */ 144#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x00000254 /* Read DQSP Bit VDL static override control register */ 145#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x00000258 /* Read DQSN Bit VDL static override control register */ 146#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x0000025c /* Read DQSP Bit VDL static override control register */ 147#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x00000260 /* Read DQSN Bit VDL static override control register */ 148#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x00000264 /* Read DQSP Bit VDL static override control register */ 149#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x00000268 /* Read DQSN Bit VDL static override control register */ 150#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x0000026c /* Read DQSP Bit VDL static override control register */ 151#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x00000270 /* Read DQSN Bit VDL static override control register */ 152#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x00000274 /* Read Enable Bit VDL static override control register */ 153#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W 0x000002a4 /* Write Byte VDL static override control register */ 154#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P 0x000002a8 /* Read Byte DQSP VDL static override control register */ 155#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N 0x000002ac /* Read Byte DQSN VDL static override control register */ 156#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W 0x000002b0 /* Write Bit VDL static override control register */ 157#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W 0x000002b4 /* Write Bit VDL static override control register */ 158#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W 0x000002b8 /* Write Bit VDL static override control register */ 159#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W 0x000002bc /* Write Bit VDL static override control register */ 160#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W 0x000002c0 /* Write Bit VDL static override control register */ 161#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W 0x000002c4 /* Write Bit VDL static override control register */ 162#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W 0x000002c8 /* Write Bit VDL static override control register */ 163#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W 0x000002cc /* Write Bit VDL static override control register */ 164#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W 0x000002d0 /* Write Bit VDL static override control register */ 165#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x000002d4 /* Read DQSP Bit VDL static override control register */ 166#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x000002d8 /* Read DQSN Bit VDL static override control register */ 167#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x000002dc /* Read DQSP Bit VDL static override control register */ 168#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x000002e0 /* Read DQSN Bit VDL static override control register */ 169#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x000002e4 /* Read DQSP Bit VDL static override control register */ 170#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x000002e8 /* Read DQSN Bit VDL static override control register */ 171#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x000002ec /* Read DQSP Bit VDL static override control register */ 172#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x000002f0 /* Read DQSN Bit VDL static override control register */ 173#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x000002f4 /* Read DQSP Bit VDL static override control register */ 174#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x000002f8 /* Read DQSN Bit VDL static override control register */ 175#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x000002fc /* Read DQSP Bit VDL static override control register */ 176#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x00000300 /* Read DQSN Bit VDL static override control register */ 177#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x00000304 /* Read DQSP Bit VDL static override control register */ 178#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x00000308 /* Read DQSN Bit VDL static override control register */ 179#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x0000030c /* Read DQSP Bit VDL static override control register */ 180#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x00000310 /* Read DQSN Bit VDL static override control register */ 181#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x00000314 /* Read Enable Bit VDL static override control register */ 182#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x00000328 /* Read DQSP VDL dynamic override control register */ 183#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x0000032c /* Read DQSN VDL dynamic override control register */ 184#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x00000330 /* Read DQ-P VDL dynamic override control register */ 185#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x00000334 /* Read DQ-N VDL dynamic override control register */ 186#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W 0x00000338 /* Write DQ Byte VDL dynamic override control register */ 187#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x0000033c /* Write DQ Bit VDL dynamic override control register */ 188#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x00000348 /* Read DQSP VDL dynamic override control register */ 189#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x0000034c /* Read DQSN VDL dynamic override control register */ 190#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x00000350 /* Read DQ-P VDL dynamic override control register */ 191#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x00000354 /* Read DQ-N VDL dynamic override control register */ 192#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W 0x00000358 /* Write DQ Byte VDL dynamic override control register */ 193#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x0000035c /* Write DQ Bit VDL dynamic override control register */ 194#define DDR40_CORE_PHY_WORD_LANE_0_READ_DATA_DLY 0x00000360 /* Word Lane read channel control register */ 195#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL 0x00000364 /* Word Lane read channel control register */ 196#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0 0x00000370 /* Read fifo data register, first data */ 197#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1 0x00000374 /* Read fifo data register, second data */ 198#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2 0x00000378 /* Read fifo data register, third data */ 199#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3 0x0000037c /* Read fifo data register, fourth data */ 200#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0 0x00000380 /* Read fifo data register, first data */ 201#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1 0x00000384 /* Read fifo data register, second data */ 202#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2 0x00000388 /* Read fifo data register, third data */ 203#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3 0x0000038c /* Read fifo data register, fourth data */ 204#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS 0x00000390 /* Read fifo status register */ 205#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_CLEAR 0x00000394 /* Read fifo status clear register */ 206#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL 0x000003a0 /* Idle mode SSTL pad control register */ 207#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL 0x000003a4 /* SSTL pad drive characteristics control register */ 208#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE 0x000003a8 /* Clock pad disable register */ 209#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE 0x000003ac /* Write cycle preamble control register */ 210 211/*************************************************************************** 212 *DDR40_CORE_PHY_WORD_LANE_1 - DDR40 CORE DDR40 word lane #1 control registers 213 ***************************************************************************/ 214#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN 0x00000400 /* Read Enable Byte VDL static override control register */ 215#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W 0x00000404 /* Write Byte VDL static override control register */ 216#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P 0x00000408 /* Read Byte DQSP VDL static override control register */ 217#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N 0x0000040c /* Read Byte DQSN VDL static override control register */ 218#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W 0x00000410 /* Write Bit VDL static override control register */ 219#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W 0x00000414 /* Write Bit VDL static override control register */ 220#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W 0x00000418 /* Write Bit VDL static override control register */ 221#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W 0x0000041c /* Write Bit VDL static override control register */ 222#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W 0x00000420 /* Write Bit VDL static override control register */ 223#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W 0x00000424 /* Write Bit VDL static override control register */ 224#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W 0x00000428 /* Write Bit VDL static override control register */ 225#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W 0x0000042c /* Write Bit VDL static override control register */ 226#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W 0x00000430 /* Write Bit VDL static override control register */ 227#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P 0x00000434 /* Read DQSP Bit VDL static override control register */ 228#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N 0x00000438 /* Read DQSN Bit VDL static override control register */ 229#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P 0x0000043c /* Read DQSP Bit VDL static override control register */ 230#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N 0x00000440 /* Read DQSN Bit VDL static override control register */ 231#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P 0x00000444 /* Read DQSP Bit VDL static override control register */ 232#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N 0x00000448 /* Read DQSN Bit VDL static override control register */ 233#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P 0x0000044c /* Read DQSP Bit VDL static override control register */ 234#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N 0x00000450 /* Read DQSN Bit VDL static override control register */ 235#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P 0x00000454 /* Read DQSP Bit VDL static override control register */ 236#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N 0x00000458 /* Read DQSN Bit VDL static override control register */ 237#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P 0x0000045c /* Read DQSP Bit VDL static override control register */ 238#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N 0x00000460 /* Read DQSN Bit VDL static override control register */ 239#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P 0x00000464 /* Read DQSP Bit VDL static override control register */ 240#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N 0x00000468 /* Read DQSN Bit VDL static override control register */ 241#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P 0x0000046c /* Read DQSP Bit VDL static override control register */ 242#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N 0x00000470 /* Read DQSN Bit VDL static override control register */ 243#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x00000474 /* Read Enable Bit VDL static override control register */ 244#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W 0x000004a4 /* Write Byte VDL static override control register */ 245#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P 0x000004a8 /* Read Byte DQSP VDL static override control register */ 246#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N 0x000004ac /* Read Byte DQSN VDL static override control register */ 247#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W 0x000004b0 /* Write Bit VDL static override control register */ 248#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W 0x000004b4 /* Write Bit VDL static override control register */ 249#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W 0x000004b8 /* Write Bit VDL static override control register */ 250#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W 0x000004bc /* Write Bit VDL static override control register */ 251#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W 0x000004c0 /* Write Bit VDL static override control register */ 252#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W 0x000004c4 /* Write Bit VDL static override control register */ 253#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W 0x000004c8 /* Write Bit VDL static override control register */ 254#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W 0x000004cc /* Write Bit VDL static override control register */ 255#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W 0x000004d0 /* Write Bit VDL static override control register */ 256#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P 0x000004d4 /* Read DQSP Bit VDL static override control register */ 257#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N 0x000004d8 /* Read DQSN Bit VDL static override control register */ 258#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P 0x000004dc /* Read DQSP Bit VDL static override control register */ 259#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N 0x000004e0 /* Read DQSN Bit VDL static override control register */ 260#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P 0x000004e4 /* Read DQSP Bit VDL static override control register */ 261#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N 0x000004e8 /* Read DQSN Bit VDL static override control register */ 262#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P 0x000004ec /* Read DQSP Bit VDL static override control register */ 263#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N 0x000004f0 /* Read DQSN Bit VDL static override control register */ 264#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P 0x000004f4 /* Read DQSP Bit VDL static override control register */ 265#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N 0x000004f8 /* Read DQSN Bit VDL static override control register */ 266#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P 0x000004fc /* Read DQSP Bit VDL static override control register */ 267#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N 0x00000500 /* Read DQSN Bit VDL static override control register */ 268#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P 0x00000504 /* Read DQSP Bit VDL static override control register */ 269#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N 0x00000508 /* Read DQSN Bit VDL static override control register */ 270#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P 0x0000050c /* Read DQSP Bit VDL static override control register */ 271#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N 0x00000510 /* Read DQSN Bit VDL static override control register */ 272#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x00000514 /* Read Enable Bit VDL static override control register */ 273#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P 0x00000528 /* Read DQSP VDL dynamic override control register */ 274#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N 0x0000052c /* Read DQSN VDL dynamic override control register */ 275#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x00000530 /* Read DQ-P VDL dynamic override control register */ 276#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x00000534 /* Read DQ-N VDL dynamic override control register */ 277#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W 0x00000538 /* Write DQ Byte VDL dynamic override control register */ 278#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x0000053c /* Write DQ Bit VDL dynamic override control register */ 279#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P 0x00000548 /* Read DQSP VDL dynamic override control register */ 280#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N 0x0000054c /* Read DQSN VDL dynamic override control register */ 281#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x00000550 /* Read DQ-P VDL dynamic override control register */ 282#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x00000554 /* Read DQ-N VDL dynamic override control register */ 283#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W 0x00000558 /* Write DQ Byte VDL dynamic override control register */ 284#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x0000055c /* Write DQ Bit VDL dynamic override control register */ 285#define DDR40_CORE_PHY_WORD_LANE_1_READ_DATA_DLY 0x00000560 /* Word Lane read channel control register */ 286#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL 0x00000564 /* Word Lane read channel control register */ 287#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0 0x00000570 /* Read fifo data register, first data */ 288#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1 0x00000574 /* Read fifo data register, second data */ 289#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2 0x00000578 /* Read fifo data register, third data */ 290#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3 0x0000057c /* Read fifo data register, fourth data */ 291#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0 0x00000580 /* Read fifo data register, first data */ 292#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1 0x00000584 /* Read fifo data register, second data */ 293#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2 0x00000588 /* Read fifo data register, third data */ 294#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3 0x0000058c /* Read fifo data register, fourth data */ 295#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS 0x00000590 /* Read fifo status register */ 296#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_CLEAR 0x00000594 /* Read fifo status clear register */ 297#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL 0x000005a0 /* Idle mode SSTL pad control register */ 298#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL 0x000005a4 /* SSTL pad drive characteristics control register */ 299#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE 0x000005a8 /* Clock pad disable register */ 300#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE 0x000005ac /* Write cycle preamble control register */ 301 302/*************************************************************************** 303 *REVISION - Address & Control revision register 304 ***************************************************************************/ 305/* DDR40_CORE_PHY_CONTROL_REGS :: REVISION :: reserved0 [31:23] */ 306#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_reserved0_MASK 0xff800000 307#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_reserved0_ALIGN 0 308#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_reserved0_BITS 9 309#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_reserved0_SHIFT 23 310 311/* DDR40_CORE_PHY_CONTROL_REGS :: REVISION :: TECHNOLOGY [22:20] */ 312#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_MASK 0x00700000 313#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_ALIGN 0 314#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_BITS 3 315#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_SHIFT 20 316#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_DEFAULT 1 317 318/* DDR40_CORE_PHY_CONTROL_REGS :: REVISION :: WB [19:19] */ 319#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_WB_MASK 0x00080000 320#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_WB_ALIGN 0 321#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_WB_BITS 1 322#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_WB_SHIFT 19 323#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_WB_DEFAULT 0 324 325/* DDR40_CORE_PHY_CONTROL_REGS :: REVISION :: BITS [18:16] */ 326#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_BITS_MASK 0x00070000 327#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_BITS_ALIGN 0 328#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_BITS_BITS 3 329#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_BITS_SHIFT 16 330#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_BITS_DEFAULT 1 331 332/* DDR40_CORE_PHY_CONTROL_REGS :: REVISION :: MAJOR [15:08] */ 333#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_MASK 0x0000ff00 334#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_ALIGN 0 335#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_BITS 8 336#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_SHIFT 8 337#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_DEFAULT 64 338 339/* DDR40_CORE_PHY_CONTROL_REGS :: REVISION :: MINOR [07:00] */ 340#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_MINOR_MASK 0x000000ff 341#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_MINOR_ALIGN 0 342#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_MINOR_BITS 8 343#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_MINOR_SHIFT 0 344#define DDR40_CORE_PHY_CONTROL_REGS_REVISION_MINOR_DEFAULT 4 345 346/*************************************************************************** 347 *CLK_PM_CTRL - PHY clock power management control register 348 ***************************************************************************/ 349/* DDR40_CORE_PHY_CONTROL_REGS :: CLK_PM_CTRL :: reserved0 [31:01] */ 350#define DDR40_CORE_PHY_CONTROL_REGS_CLK_PM_CTRL_reserved0_MASK 0xfffffffe 351#define DDR40_CORE_PHY_CONTROL_REGS_CLK_PM_CTRL_reserved0_ALIGN 0 352#define DDR40_CORE_PHY_CONTROL_REGS_CLK_PM_CTRL_reserved0_BITS 31 353#define DDR40_CORE_PHY_CONTROL_REGS_CLK_PM_CTRL_reserved0_SHIFT 1 354 355/* DDR40_CORE_PHY_CONTROL_REGS :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */ 356#define DDR40_CORE_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001 357#define DDR40_CORE_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_ALIGN 0 358#define DDR40_CORE_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_BITS 1 359#define DDR40_CORE_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0 360#define DDR40_CORE_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0 361 362/*************************************************************************** 363 *PLL_STATUS - PHY PLL status register 364 ***************************************************************************/ 365/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: reserved0 [31:27] */ 366#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_MASK 0xf8000000 367#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_ALIGN 0 368#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_BITS 5 369#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_SHIFT 27 370 371/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK_LOST [26:26] */ 372#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_MASK 0x04000000 373#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_ALIGN 0 374#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_BITS 1 375#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_SHIFT 26 376 377/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: DDR_MHZ [25:14] */ 378#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_DDR_MHZ_MASK 0x03ffc000 379#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_DDR_MHZ_ALIGN 0 380#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_DDR_MHZ_BITS 12 381#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_DDR_MHZ_SHIFT 14 382 383/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_4X [13:13] */ 384#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_MASK 0x00002000 385#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_ALIGN 0 386#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_BITS 1 387#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_SHIFT 13 388 389/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: STATUS [12:01] */ 390#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_MASK 0x00001ffe 391#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_ALIGN 0 392#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_BITS 12 393#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_SHIFT 1 394 395/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK [00:00] */ 396#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_MASK 0x00000001 397#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_ALIGN 0 398#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_BITS 1 399#define DDR40_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_SHIFT 0 400 401/*************************************************************************** 402 *PLL_CONFIG - PHY PLL configuration register 403 ***************************************************************************/ 404/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved0 [31:07] */ 405#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_MASK 0xffffff80 406#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_ALIGN 0 407#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_BITS 25 408#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_SHIFT 7 409 410/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */ 411#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040 412#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_LP40_PLL_POST_RESET_ALIGN 0 413#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_LP40_PLL_POST_RESET_BITS 1 414#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6 415#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0 416 417/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET_POST_DIV [05:05] */ 418#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020 419#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_ALIGN 0 420#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_BITS 1 421#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_SHIFT 5 422#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0 423 424/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: LDO_CTRL [04:03] */ 425#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_LDO_CTRL_MASK 0x00000018 426#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_LDO_CTRL_ALIGN 0 427#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_LDO_CTRL_BITS 2 428#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_LDO_CTRL_SHIFT 3 429#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_LDO_CTRL_DEFAULT 2 430 431/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved1 [02:02] */ 432#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved1_MASK 0x00000004 433#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved1_ALIGN 0 434#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved1_BITS 1 435#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved1_SHIFT 2 436 437/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET [01:01] */ 438#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_MASK 0x00000002 439#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_ALIGN 0 440#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_BITS 1 441#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_SHIFT 1 442#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_DEFAULT 1 443 444/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN [00:00] */ 445#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK 0x00000001 446#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_ALIGN 0 447#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_BITS 1 448#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_SHIFT 0 449#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_DEFAULT 0 450 451/*************************************************************************** 452 *PLL_CONTROL - PHY PLL control register 453 ***************************************************************************/ 454/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONTROL :: reserved0 [31:31] */ 455#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_reserved0_MASK 0x80000000 456#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_reserved0_ALIGN 0 457#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_reserved0_BITS 1 458#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_reserved0_SHIFT 31 459 460/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONTROL :: i_kp [30:27] */ 461#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_kp_MASK 0x78000000 462#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_kp_ALIGN 0 463#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_kp_BITS 4 464#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_kp_SHIFT 27 465#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_kp_DEFAULT 10 466 467/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONTROL :: i_ki [26:24] */ 468#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_ki_MASK 0x07000000 469#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_ki_ALIGN 0 470#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_ki_BITS 3 471#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_ki_SHIFT 24 472#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_ki_DEFAULT 3 473 474/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONTROL :: i_ka [23:21] */ 475#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_ka_MASK 0x00e00000 476#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_ka_ALIGN 0 477#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_ka_BITS 3 478#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_ka_SHIFT 21 479#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_i_ka_DEFAULT 3 480 481/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_CONTROL :: PLL_CONTROL [20:00] */ 482#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff 483#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_PLL_CONTROL_ALIGN 0 484#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_PLL_CONTROL_BITS 21 485#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_PLL_CONTROL_SHIFT 0 486#define DDR40_CORE_PHY_CONTROL_REGS_PLL_CONTROL_PLL_CONTROL_DEFAULT 0 487 488/*************************************************************************** 489 *PLL_DIVIDERS - PHY PLL dividers control register 490 ***************************************************************************/ 491/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved0 [31:16] */ 492#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_MASK 0xffff0000 493#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_ALIGN 0 494#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_BITS 16 495#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_SHIFT 16 496 497/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */ 498#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000 499#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_HI_ALIGN 0 500#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_HI_BITS 1 501#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15 502#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0 503 504/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */ 505#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000 506#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_LO_ALIGN 0 507#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_LO_BITS 1 508#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14 509#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0 510 511/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: POST_DIV [13:11] */ 512#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_POST_DIV_MASK 0x00003800 513#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_POST_DIV_ALIGN 0 514#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_POST_DIV_BITS 3 515#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_POST_DIV_SHIFT 11 516#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_POST_DIV_DEFAULT 2 517 518/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: PDIV [10:08] */ 519#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_MASK 0x00000700 520#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_ALIGN 0 521#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_BITS 3 522#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_SHIFT 8 523#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_DEFAULT 4 524 525/* DDR40_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: NDIV [07:00] */ 526#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_MASK 0x000000ff 527#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_ALIGN 0 528#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_BITS 8 529#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_SHIFT 0 530#define DDR40_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_DEFAULT 32 531 532/*************************************************************************** 533 *AUX_CONTROL - Aux Control register 534 ***************************************************************************/ 535/* DDR40_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved0 [31:10] */ 536#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_MASK 0xfffffc00 537#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_ALIGN 0 538#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_BITS 22 539#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_SHIFT 10 540 541/* DDR40_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: is_cs [09:07] */ 542#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_cs_MASK 0x00000380 543#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_cs_ALIGN 0 544#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_cs_BITS 3 545#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_cs_SHIFT 7 546#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_cs_DEFAULT 0 547 548/* DDR40_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: is_ad [06:04] */ 549#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_ad_MASK 0x00000070 550#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_ad_ALIGN 0 551#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_ad_BITS 3 552#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_ad_SHIFT 4 553#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_ad_DEFAULT 0 554 555/* DDR40_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: is_odt [03:01] */ 556#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_odt_MASK 0x0000000e 557#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_odt_ALIGN 0 558#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_odt_BITS 3 559#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_odt_SHIFT 1 560#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_is_odt_DEFAULT 0 561 562/* DDR40_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: override [00:00] */ 563#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_override_MASK 0x00000001 564#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_override_ALIGN 0 565#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_override_BITS 1 566#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_override_SHIFT 0 567#define DDR40_CORE_PHY_CONTROL_REGS_AUX_CONTROL_override_DEFAULT 0 568 569/*************************************************************************** 570 *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register 571 ***************************************************************************/ 572/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */ 573#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000 574#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_busy_ALIGN 0 575#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_busy_BITS 1 576#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31 577#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0 578 579/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */ 580#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000 581#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved0_ALIGN 0 582#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved0_BITS 14 583#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17 584 585/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */ 586#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000 587#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_ovr_en_ALIGN 0 588#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_ovr_en_BITS 1 589#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16 590#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0 591 592/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */ 593#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00 594#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved1_ALIGN 0 595#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved1_BITS 7 596#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9 597 598/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */ 599#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100 600#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_byte_sel_ALIGN 0 601#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_byte_sel_BITS 1 602#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8 603#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0 604 605/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */ 606#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0 607#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved2_ALIGN 0 608#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved2_BITS 2 609#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6 610 611/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */ 612#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f 613#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_ovr_step_ALIGN 0 614#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_ovr_step_BITS 6 615#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0 616#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0 617 618/*************************************************************************** 619 *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register 620 ***************************************************************************/ 621/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */ 622#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000 623#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_busy_ALIGN 0 624#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_busy_BITS 1 625#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31 626#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0 627 628/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */ 629#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000 630#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved0_ALIGN 0 631#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved0_BITS 14 632#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17 633 634/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */ 635#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000 636#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_ovr_en_ALIGN 0 637#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_ovr_en_BITS 1 638#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16 639#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0 640 641/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */ 642#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00 643#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved1_ALIGN 0 644#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved1_BITS 7 645#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9 646 647/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */ 648#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100 649#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_byte_sel_ALIGN 0 650#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_byte_sel_BITS 1 651#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8 652#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0 653 654/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */ 655#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0 656#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved2_ALIGN 0 657#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved2_BITS 2 658#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6 659 660/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */ 661#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f 662#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_ovr_step_ALIGN 0 663#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_ovr_step_BITS 6 664#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0 665#define DDR40_CORE_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0 666 667/*************************************************************************** 668 *IDLE_PAD_CONTROL - Idle mode SSTL pad control register 669 ***************************************************************************/ 670/* DDR40_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: idle [31:31] */ 671#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK 0x80000000 672#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_ALIGN 0 673#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_BITS 1 674#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_SHIFT 31 675#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_DEFAULT 0 676 677/* DDR40_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved0 [30:09] */ 678#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00 679#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_ALIGN 0 680#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_BITS 22 681#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_SHIFT 9 682 683/* DDR40_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: rxenb [08:08] */ 684#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_MASK 0x00000100 685#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_ALIGN 0 686#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_BITS 1 687#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_SHIFT 8 688#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_DEFAULT 1 689 690/* DDR40_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved1 [07:07] */ 691#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080 692#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved1_ALIGN 0 693#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved1_BITS 1 694#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved1_SHIFT 7 695 696/* DDR40_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */ 697#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040 698#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_ALIGN 0 699#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_BITS 1 700#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6 701#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0 702 703/* DDR40_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */ 704#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020 705#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_reb_ALIGN 0 706#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_reb_BITS 1 707#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5 708#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 1 709 710/* DDR40_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */ 711#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010 712#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_oeb_ALIGN 0 713#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_oeb_BITS 1 714#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4 715#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 1 716 717/* DDR40_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved2 [03:03] */ 718#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008 719#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved2_ALIGN 0 720#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved2_BITS 1 721#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved2_SHIFT 3 722 723/* DDR40_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */ 724#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004 725#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_iddq_ALIGN 0 726#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_iddq_BITS 1 727#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2 728#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0 729 730/* DDR40_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_reb [01:01] */ 731#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002 732#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_ALIGN 0 733#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_BITS 1 734#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_SHIFT 1 735#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_DEFAULT 1 736 737/* DDR40_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */ 738#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001 739#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_oeb_ALIGN 0 740#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_oeb_BITS 1 741#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0 742#define DDR40_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0 743 744/*************************************************************************** 745 *ZQ_PVT_COMP_CTL - PVT Compensation control and status register 746 ***************************************************************************/ 747/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */ 748#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000 749#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_reserved0_ALIGN 0 750#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_reserved0_BITS 6 751#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26 752 753/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */ 754#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000 755#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_update_mode_ALIGN 0 756#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_update_mode_BITS 1 757#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25 758#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0 759 760/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */ 761#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000 762#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_done_ALIGN 0 763#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_done_BITS 1 764#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24 765#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0 766 767/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */ 768#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000 769#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_done_ALIGN 0 770#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_done_BITS 1 771#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23 772#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0 773 774/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */ 775#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000 776#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_ALIGN 0 777#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_BITS 1 778#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22 779#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 1 780 781/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */ 782#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000 783#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_auto_sample_en_ALIGN 0 784#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_auto_sample_en_BITS 1 785#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21 786#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0 787 788/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */ 789#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000 790#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_ALIGN 0 791#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_BITS 1 792#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20 793#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0 794 795/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */ 796#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000 797#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_ovr_en_ALIGN 0 798#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_ovr_en_BITS 1 799#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19 800#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0 801 802/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */ 803#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000 804#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_ovr_en_ALIGN 0 805#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_ovr_en_BITS 1 806#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18 807#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0 808 809/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */ 810#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000 811#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_comp_ALIGN 0 812#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_comp_BITS 3 813#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15 814#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0 815 816/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */ 817#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000 818#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_comp_ALIGN 0 819#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_comp_BITS 3 820#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12 821#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0 822 823/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */ 824#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00 825#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_pd_override_val_ALIGN 0 826#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_pd_override_val_BITS 3 827#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9 828#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0 829 830/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */ 831#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0 832#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_nd_override_val_ALIGN 0 833#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_nd_override_val_BITS 3 834#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6 835#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0 836 837/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */ 838#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038 839#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_pd_override_val_ALIGN 0 840#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_pd_override_val_BITS 3 841#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3 842#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0 843 844/* DDR40_CORE_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */ 845#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007 846#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_nd_override_val_ALIGN 0 847#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_nd_override_val_BITS 3 848#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0 849#define DDR40_CORE_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0 850 851/*************************************************************************** 852 *DRIVE_PAD_CTL - SSTL pad drive characteristics control register 853 ***************************************************************************/ 854/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: reserved0 [31:14] */ 855#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000 856#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_ALIGN 0 857#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_BITS 18 858#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_SHIFT 14 859 860/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: auto_oeb [13:13] */ 861#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_auto_oeb_MASK 0x00002000 862#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_auto_oeb_ALIGN 0 863#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_auto_oeb_BITS 1 864#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_auto_oeb_SHIFT 13 865#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0 866 867/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */ 868#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a15_MASK 0x00001000 869#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a15_ALIGN 0 870#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a15_BITS 1 871#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a15_SHIFT 12 872#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0 873 874/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */ 875#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a14_MASK 0x00000800 876#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a14_ALIGN 0 877#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a14_BITS 1 878#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a14_SHIFT 11 879#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0 880 881/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */ 882#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a13_MASK 0x00000400 883#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a13_ALIGN 0 884#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a13_BITS 1 885#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a13_SHIFT 10 886#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0 887 888/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: iddq_aux [09:07] */ 889#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_aux_MASK 0x00000380 890#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_aux_ALIGN 0 891#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_aux_BITS 3 892#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_aux_SHIFT 7 893#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0 894 895/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: half_strength [06:06] */ 896#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_half_strength_MASK 0x00000040 897#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_half_strength_ALIGN 0 898#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_half_strength_BITS 1 899#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_half_strength_SHIFT 6 900#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_half_strength_DEFAULT 0 901 902/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */ 903#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020 904#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_gddr_symmetry_ALIGN 0 905#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_gddr_symmetry_BITS 1 906#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5 907#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0 908 909/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: vddo_volts [04:03] */ 910#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018 911#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_vddo_volts_ALIGN 0 912#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_vddo_volts_BITS 2 913#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_vddo_volts_SHIFT 3 914#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0 915 916/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: rt60b [02:02] */ 917#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_MASK 0x00000004 918#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_ALIGN 0 919#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_BITS 1 920#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_SHIFT 2 921#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_DEFAULT 0 922 923/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: rt120b_g [01:01] */ 924#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt120b_g_MASK 0x00000002 925#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt120b_g_ALIGN 0 926#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt120b_g_BITS 1 927#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt120b_g_SHIFT 1 928#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1 929 930/* DDR40_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: g_ddr [00:00] */ 931#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_g_ddr_MASK 0x00000001 932#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_g_ddr_ALIGN 0 933#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_g_ddr_BITS 1 934#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_g_ddr_SHIFT 0 935#define DDR40_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_g_ddr_DEFAULT 0 936 937/*************************************************************************** 938 *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register 939 ***************************************************************************/ 940/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */ 941#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000 942#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_reserved0_ALIGN 0 943#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_reserved0_BITS 20 944#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12 945 946/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */ 947#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0 948#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_auto_init_state_ALIGN 0 949#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_auto_init_state_BITS 6 950#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6 951#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0 952 953/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */ 954#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038 955#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_ALIGN 0 956#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_BITS 3 957#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3 958#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0 959 960/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */ 961#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007 962#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_ALIGN 0 963#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_BITS 3 964#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0 965#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 7 966 967/*************************************************************************** 968 *VDL_CALIBRATE - PHY VDL calibration control register 969 ***************************************************************************/ 970/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: reserved0 [31:30] */ 971#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_MASK 0xc0000000 972#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_ALIGN 0 973#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_BITS 2 974#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_SHIFT 30 975 976/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: single_cycle [29:29] */ 977#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_single_cycle_MASK 0x20000000 978#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_single_cycle_ALIGN 0 979#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_single_cycle_BITS 1 980#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_single_cycle_SHIFT 29 981#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_single_cycle_DEFAULT 0 982 983/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: use_straps [28:28] */ 984#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_use_straps_MASK 0x10000000 985#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_use_straps_ALIGN 0 986#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_use_straps_BITS 1 987#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_use_straps_SHIFT 28 988#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_use_straps_DEFAULT 1 989 990/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: auto_init [27:27] */ 991#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_auto_init_MASK 0x08000000 992#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_auto_init_ALIGN 0 993#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_auto_init_BITS 1 994#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_auto_init_SHIFT 27 995#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_auto_init_DEFAULT 0 996 997/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: skip_rst [26:26] */ 998#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_skip_rst_MASK 0x04000000 999#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_skip_rst_ALIGN 0 1000#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_skip_rst_BITS 1 1001#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_skip_rst_SHIFT 26 1002#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_skip_rst_DEFAULT 0 1003 1004/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: exit_in_sr [25:25] */ 1005#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000 1006#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_exit_in_sr_ALIGN 0 1007#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_exit_in_sr_BITS 1 1008#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_exit_in_sr_SHIFT 25 1009#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_exit_in_sr_DEFAULT 0 1010 1011/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: rd_dly_cal [24:24] */ 1012#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000 1013#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_rd_dly_cal_ALIGN 0 1014#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_rd_dly_cal_BITS 1 1015#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_rd_dly_cal_SHIFT 24 1016#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0 1017 1018/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: bit_refresh [23:23] */ 1019#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_bit_refresh_MASK 0x00800000 1020#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_bit_refresh_ALIGN 0 1021#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_bit_refresh_BITS 1 1022#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_bit_refresh_SHIFT 23 1023#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_bit_refresh_DEFAULT 0 1024 1025/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: set_wr_dq [22:22] */ 1026#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000 1027#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_set_wr_dq_ALIGN 0 1028#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_set_wr_dq_BITS 1 1029#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_set_wr_dq_SHIFT 22 1030#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_set_wr_dq_DEFAULT 0 1031 1032/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: dq0_only [21:21] */ 1033#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_dq0_only_MASK 0x00200000 1034#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_dq0_only_ALIGN 0 1035#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_dq0_only_BITS 1 1036#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_dq0_only_SHIFT 21 1037#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_dq0_only_DEFAULT 0 1038 1039/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: set_mr_mpr [20:20] */ 1040#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000 1041#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_set_mr_mpr_ALIGN 0 1042#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_set_mr_mpr_BITS 1 1043#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_set_mr_mpr_SHIFT 20 1044#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0 1045 1046/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: bit_cal [19:19] */ 1047#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_bit_cal_MASK 0x00080000 1048#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_bit_cal_ALIGN 0 1049#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_bit_cal_BITS 1 1050#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_bit_cal_SHIFT 19 1051#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_bit_cal_DEFAULT 0 1052 1053/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: rd_en_cal [18:18] */ 1054#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000 1055#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_rd_en_cal_ALIGN 0 1056#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_rd_en_cal_BITS 1 1057#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_rd_en_cal_SHIFT 18 1058#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_rd_en_cal_DEFAULT 0 1059 1060/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_bit_offset [17:12] */ 1061#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000 1062#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_bit_offset_ALIGN 0 1063#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_bit_offset_BITS 6 1064#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_bit_offset_SHIFT 12 1065#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0 1066 1067/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */ 1068#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800 1069#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_dqs_clocks_ALIGN 0 1070#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_dqs_clocks_BITS 1 1071#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11 1072#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0 1073 1074/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */ 1075#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400 1076#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_dqs_pair_ALIGN 0 1077#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_dqs_pair_BITS 1 1078#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10 1079#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0 1080 1081/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_steps [09:09] */ 1082#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_steps_MASK 0x00000200 1083#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_steps_ALIGN 0 1084#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_steps_BITS 1 1085#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_steps_SHIFT 9 1086#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_steps_DEFAULT 0 1087 1088/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_auto [08:08] */ 1089#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_auto_MASK 0x00000100 1090#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_auto_ALIGN 0 1091#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_auto_BITS 1 1092#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_auto_SHIFT 8 1093#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_auto_DEFAULT 0 1094 1095/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_ftm [07:07] */ 1096#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_ftm_MASK 0x00000080 1097#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_ftm_ALIGN 0 1098#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_ftm_BITS 1 1099#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_ftm_SHIFT 7 1100#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_ftm_DEFAULT 0 1101 1102/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_phybist [06:06] */ 1103#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_phybist_MASK 0x00000040 1104#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_phybist_ALIGN 0 1105#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_phybist_BITS 1 1106#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_phybist_SHIFT 6 1107#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_phybist_DEFAULT 0 1108 1109/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_byte [05:05] */ 1110#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_byte_MASK 0x00000020 1111#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_byte_ALIGN 0 1112#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_byte_BITS 1 1113#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_byte_SHIFT 5 1114#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_byte_DEFAULT 0 1115 1116/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_clocks [04:04] */ 1117#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_clocks_MASK 0x00000010 1118#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_clocks_ALIGN 0 1119#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_clocks_BITS 1 1120#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_clocks_SHIFT 4 1121#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_clocks_DEFAULT 0 1122 1123/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_test [03:03] */ 1124#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_test_MASK 0x00000008 1125#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_test_ALIGN 0 1126#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_test_BITS 1 1127#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_test_SHIFT 3 1128#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_test_DEFAULT 0 1129 1130/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_always [02:02] */ 1131#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_always_MASK 0x00000004 1132#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_always_ALIGN 0 1133#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_always_BITS 1 1134#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_always_SHIFT 2 1135#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_always_DEFAULT 0 1136 1137/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_once [01:01] */ 1138#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_once_MASK 0x00000002 1139#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_once_ALIGN 0 1140#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_once_BITS 1 1141#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_once_SHIFT 1 1142#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_once_DEFAULT 0 1143 1144/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_fast [00:00] */ 1145#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_fast_MASK 0x00000001 1146#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_fast_ALIGN 0 1147#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_fast_BITS 1 1148#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_fast_SHIFT 0 1149#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_calib_fast_DEFAULT 0 1150 1151/*************************************************************************** 1152 *VDL_CALIB_STATUS - PHY VDL calibration status register 1153 ***************************************************************************/ 1154/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: reserved0 [31:30] */ 1155#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000 1156#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_reserved0_ALIGN 0 1157#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_reserved0_BITS 2 1158#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_reserved0_SHIFT 30 1159 1160/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */ 1161#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000 1162#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_auto_init_fail_ALIGN 0 1163#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_auto_init_fail_BITS 1 1164#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29 1165#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0 1166 1167/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: auto_init_done [28:28] */ 1168#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000 1169#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_auto_init_done_ALIGN 0 1170#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_auto_init_done_BITS 1 1171#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_auto_init_done_SHIFT 28 1172#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0 1173 1174/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */ 1175#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000 1176#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_rd_data_dly_error_ALIGN 0 1177#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_rd_data_dly_error_BITS 1 1178#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27 1179#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0 1180 1181/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */ 1182#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000 1183#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_read_en_error_ALIGN 0 1184#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_read_en_error_BITS 4 1185#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23 1186#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0 1187 1188/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */ 1189#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000 1190#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_byte_error_ALIGN 0 1191#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_byte_error_BITS 4 1192#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19 1193#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0 1194 1195/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */ 1196#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000 1197#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_byte_sel_ALIGN 0 1198#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_byte_sel_BITS 1 1199#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18 1200#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0 1201 1202/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */ 1203#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000 1204#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_bit_offset_ALIGN 0 1205#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_bit_offset_BITS 6 1206#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12 1207#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0 1208 1209/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_total [11:02] */ 1210#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc 1211#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_total_ALIGN 0 1212#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_total_BITS 10 1213#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_total_SHIFT 2 1214#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_total_DEFAULT 0 1215 1216/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_lock [01:01] */ 1217#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002 1218#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_lock_ALIGN 0 1219#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_lock_BITS 1 1220#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_lock_SHIFT 1 1221#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_lock_DEFAULT 0 1222 1223/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_idle [00:00] */ 1224#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001 1225#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_idle_ALIGN 0 1226#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_idle_BITS 1 1227#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_idle_SHIFT 0 1228#define DDR40_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS_calib_idle_DEFAULT 1 1229 1230/*************************************************************************** 1231 *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register 1232 ***************************************************************************/ 1233/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */ 1234#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000 1235#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_reserved0_ALIGN 0 1236#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_reserved0_BITS 6 1237#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26 1238 1239/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */ 1240#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000 1241#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_total_ALIGN 0 1242#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_total_BITS 10 1243#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16 1244#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0 1245 1246/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */ 1247#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000 1248#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_reserved1_ALIGN 0 1249#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_reserved1_BITS 2 1250#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14 1251 1252/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */ 1253#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0 1254#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dq_calib_total_ALIGN 0 1255#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dq_calib_total_BITS 10 1256#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4 1257#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0 1258 1259/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */ 1260#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008 1261#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_ALIGN 0 1262#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_BITS 1 1263#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3 1264#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0 1265 1266/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */ 1267#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004 1268#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_mode_ALIGN 0 1269#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_mode_BITS 1 1270#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2 1271#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0 1272 1273/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */ 1274#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002 1275#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_lock_ALIGN 0 1276#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_lock_BITS 1 1277#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1 1278#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0 1279 1280/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */ 1281#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001 1282#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dq_calib_lock_ALIGN 0 1283#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dq_calib_lock_BITS 1 1284#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0 1285#define DDR40_CORE_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0 1286 1287/*************************************************************************** 1288 *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register 1289 ***************************************************************************/ 1290/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */ 1291#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000 1292#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved0_ALIGN 0 1293#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved0_BITS 10 1294#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22 1295 1296/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */ 1297#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000 1298#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_ALIGN 0 1299#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_BITS 6 1300#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16 1301#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0 1302 1303/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */ 1304#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000 1305#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved1_ALIGN 0 1306#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved1_BITS 2 1307#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14 1308 1309/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */ 1310#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0 1311#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_ALIGN 0 1312#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_BITS 10 1313#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4 1314#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0 1315 1316/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */ 1317#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008 1318#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved2_ALIGN 0 1319#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved2_BITS 1 1320#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3 1321 1322/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */ 1323#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004 1324#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_ALIGN 0 1325#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_BITS 1 1326#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2 1327#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0 1328 1329/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */ 1330#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002 1331#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_ALIGN 0 1332#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_BITS 1 1333#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1 1334#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0 1335 1336/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */ 1337#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001 1338#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_ALIGN 0 1339#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_BITS 1 1340#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0 1341#define DDR40_CORE_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0 1342 1343/*************************************************************************** 1344 *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register 1345 ***************************************************************************/ 1346/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */ 1347#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000 1348#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved0_ALIGN 0 1349#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved0_BITS 10 1350#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22 1351 1352/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */ 1353#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000 1354#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_ALIGN 0 1355#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_BITS 6 1356#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16 1357#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0 1358 1359/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */ 1360#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000 1361#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved1_ALIGN 0 1362#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved1_BITS 2 1363#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14 1364 1365/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */ 1366#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0 1367#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_ALIGN 0 1368#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_BITS 10 1369#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4 1370#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0 1371 1372/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */ 1373#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008 1374#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved2_ALIGN 0 1375#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved2_BITS 1 1376#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3 1377 1378/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */ 1379#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004 1380#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_ALIGN 0 1381#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_BITS 1 1382#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2 1383#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0 1384 1385/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */ 1386#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002 1387#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_ALIGN 0 1388#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_BITS 1 1389#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1 1390#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0 1391 1392/* DDR40_CORE_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */ 1393#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001 1394#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_ALIGN 0 1395#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_BITS 1 1396#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0 1397#define DDR40_CORE_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0 1398 1399/*************************************************************************** 1400 *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register 1401 ***************************************************************************/ 1402/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */ 1403#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0 1404#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_ALIGN 0 1405#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_BITS 26 1406#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6 1407 1408/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */ 1409#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020 1410#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_low_vtt_ALIGN 0 1411#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_low_vtt_BITS 1 1412#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5 1413#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0 1414 1415/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */ 1416#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010 1417#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_high_vtt_ALIGN 0 1418#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_high_vtt_BITS 1 1419#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4 1420#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0 1421 1422/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */ 1423#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008 1424#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_error_reset_ALIGN 0 1425#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_error_reset_BITS 1 1426#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3 1427#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0 1428 1429/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */ 1430#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004 1431#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_ctl_idle_ALIGN 0 1432#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_ctl_idle_BITS 1 1433#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2 1434#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0 1435 1436/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */ 1437#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002 1438#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_cs_idle_ALIGN 0 1439#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_cs_idle_BITS 1 1440#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1 1441#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0 1442 1443/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */ 1444#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001 1445#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_cke_idle_ALIGN 0 1446#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_cke_idle_BITS 1 1447#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0 1448#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0 1449 1450/*************************************************************************** 1451 *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register 1452 ***************************************************************************/ 1453/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */ 1454#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000 1455#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_ALIGN 0 1456#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_BITS 13 1457#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19 1458 1459/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: error [18:03] */ 1460#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8 1461#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_ALIGN 0 1462#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_BITS 16 1463#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_SHIFT 3 1464#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_DEFAULT 0 1465 1466/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: error_low [02:02] */ 1467#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004 1468#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_low_ALIGN 0 1469#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_low_BITS 1 1470#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_low_SHIFT 2 1471#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0 1472 1473/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: error_high [01:01] */ 1474#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002 1475#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_high_ALIGN 0 1476#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_high_BITS 1 1477#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_high_SHIFT 1 1478#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0 1479 1480/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ready [00:00] */ 1481#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001 1482#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ready_ALIGN 0 1483#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ready_BITS 1 1484#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ready_SHIFT 0 1485#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ready_DEFAULT 0 1486 1487/*************************************************************************** 1488 *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register 1489 ***************************************************************************/ 1490/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */ 1491#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000 1492#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_ALIGN 0 1493#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_BITS 5 1494#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27 1495 1496/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */ 1497#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff 1498#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_mask_ALIGN 0 1499#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_mask_BITS 27 1500#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0 1501#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 16777215 1502 1503/*************************************************************************** 1504 *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register 1505 ***************************************************************************/ 1506/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */ 1507#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000 1508#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_ALIGN 0 1509#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_BITS 5 1510#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27 1511 1512/* DDR40_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */ 1513#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff 1514#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_mask_ALIGN 0 1515#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_mask_BITS 27 1516#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0 1517#define DDR40_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 262143 1518 1519/*************************************************************************** 1520 *VREF_DAC_CONTROL - VREF DAC Control register 1521 ***************************************************************************/ 1522/* DDR40_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: reserved0 [31:21] */ 1523#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000 1524#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_ALIGN 0 1525#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_BITS 11 1526#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_SHIFT 21 1527 1528/* DDR40_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */ 1529#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000 1530#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK1_GT_INT_ALIGN 0 1531#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK1_GT_INT_BITS 1 1532#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20 1533#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0 1534 1535/* DDR40_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */ 1536#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000 1537#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK0_GT_INT_ALIGN 0 1538#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK0_GT_INT_BITS 1 1539#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19 1540#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0 1541 1542/* DDR40_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */ 1543#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000 1544#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_GT_INT_ALIGN 0 1545#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_GT_INT_BITS 1 1546#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18 1547#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0 1548 1549/* DDR40_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */ 1550#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000 1551#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_EXT_GT_INT_ALIGN 0 1552#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_EXT_GT_INT_BITS 1 1553#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17 1554#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0 1555 1556/* DDR40_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */ 1557#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000 1558#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_ALIGN 0 1559#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_BITS 2 1560#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15 1561#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0 1562 1563/* DDR40_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: TEST [14:14] */ 1564#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_MASK 0x00004000 1565#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_ALIGN 0 1566#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_BITS 1 1567#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_SHIFT 14 1568#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_DEFAULT 0 1569 1570/* DDR40_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN1 [13:13] */ 1571#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_MASK 0x00002000 1572#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_ALIGN 0 1573#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_BITS 1 1574#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_SHIFT 13 1575#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_DEFAULT 0 1576 1577/* DDR40_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN0 [12:12] */ 1578#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_MASK 0x00001000 1579#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_ALIGN 0 1580#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_BITS 1 1581#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_SHIFT 12 1582#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_DEFAULT 0 1583 1584/* DDR40_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC1 [11:06] */ 1585#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_MASK 0x00000fc0 1586#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_ALIGN 0 1587#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_BITS 6 1588#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_SHIFT 6 1589#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_DEFAULT 32 1590 1591/* DDR40_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC0 [05:00] */ 1592#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_MASK 0x0000003f 1593#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_ALIGN 0 1594#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_BITS 6 1595#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_SHIFT 0 1596#define DDR40_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_DEFAULT 32 1597 1598/*************************************************************************** 1599 *PHYBIST_CNTRL - PhyBist Control Register 1600 ***************************************************************************/ 1601/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved0 [31:14] */ 1602#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_MASK 0xffffc000 1603#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_ALIGN 0 1604#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_BITS 18 1605#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_SHIFT 14 1606 1607/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: force_error_sel [13:08] */ 1608#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00 1609#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_error_sel_ALIGN 0 1610#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_error_sel_BITS 6 1611#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_error_sel_SHIFT 8 1612#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_error_sel_DEFAULT 0 1613 1614/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved1 [07:05] */ 1615#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_MASK 0x000000e0 1616#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_ALIGN 0 1617#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_BITS 3 1618#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_SHIFT 5 1619 1620/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: bench_mode [04:04] */ 1621#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_bench_mode_MASK 0x00000010 1622#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_bench_mode_ALIGN 0 1623#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_bench_mode_BITS 1 1624#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_bench_mode_SHIFT 4 1625#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_bench_mode_DEFAULT 0 1626 1627/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: force_dat_error [03:03] */ 1628#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008 1629#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_dat_error_ALIGN 0 1630#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_dat_error_BITS 1 1631#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_dat_error_SHIFT 3 1632#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_dat_error_DEFAULT 0 1633 1634/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: force_ctl_error [02:02] */ 1635#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004 1636#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_ctl_error_ALIGN 0 1637#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_ctl_error_BITS 1 1638#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_ctl_error_SHIFT 2 1639#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0 1640 1641/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: int_loopback [01:01] */ 1642#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_int_loopback_MASK 0x00000002 1643#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_int_loopback_ALIGN 0 1644#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_int_loopback_BITS 1 1645#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_int_loopback_SHIFT 1 1646#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_int_loopback_DEFAULT 0 1647 1648/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: enable [00:00] */ 1649#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_enable_MASK 0x00000001 1650#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_enable_ALIGN 0 1651#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_enable_BITS 1 1652#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_enable_SHIFT 0 1653#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_enable_DEFAULT 0 1654 1655/*************************************************************************** 1656 *PHYBIST_SEED - PhyBist Seed Register 1657 ***************************************************************************/ 1658/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_SEED :: seed [31:00] */ 1659#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_seed_MASK 0xffffffff 1660#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_seed_ALIGN 0 1661#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_seed_BITS 32 1662#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_seed_SHIFT 0 1663#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_seed_DEFAULT 621693686 1664 1665/*************************************************************************** 1666 *PHYBIST_STATUS - PhyBist General Status Register 1667 ***************************************************************************/ 1668/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: reserved0 [31:04] */ 1669#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_MASK 0xfffffff0 1670#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_ALIGN 0 1671#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_BITS 28 1672#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_SHIFT 4 1673 1674/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: dat_pass [03:03] */ 1675#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_dat_pass_MASK 0x00000008 1676#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_dat_pass_ALIGN 0 1677#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_dat_pass_BITS 1 1678#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_dat_pass_SHIFT 3 1679 1680/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: ctl_pass [02:02] */ 1681#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_ctl_pass_MASK 0x00000004 1682#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_ctl_pass_ALIGN 0 1683#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_ctl_pass_BITS 1 1684#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_ctl_pass_SHIFT 2 1685 1686/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: dat_done [01:01] */ 1687#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_dat_done_MASK 0x00000002 1688#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_dat_done_ALIGN 0 1689#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_dat_done_BITS 1 1690#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_dat_done_SHIFT 1 1691 1692/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: ctl_done [00:00] */ 1693#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_ctl_done_MASK 0x00000001 1694#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_ctl_done_ALIGN 0 1695#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_ctl_done_BITS 1 1696#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_ctl_done_SHIFT 0 1697 1698/*************************************************************************** 1699 *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register 1700 ***************************************************************************/ 1701/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */ 1702#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000 1703#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_ALIGN 0 1704#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_BITS 5 1705#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_SHIFT 27 1706 1707/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */ 1708#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff 1709#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_ctl_errors_ALIGN 0 1710#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_ctl_errors_BITS 27 1711#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0 1712 1713/*************************************************************************** 1714 *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register 1715 ***************************************************************************/ 1716/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */ 1717#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff 1718#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_DQ_STATUS_dat_errors_ALIGN 0 1719#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_DQ_STATUS_dat_errors_BITS 32 1720#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0 1721 1722/*************************************************************************** 1723 *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register 1724 ***************************************************************************/ 1725/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */ 1726#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00 1727#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_reserved0_ALIGN 0 1728#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_reserved0_BITS 24 1729#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_reserved0_SHIFT 8 1730 1731/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */ 1732#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0 1733#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_ck_errors_ALIGN 0 1734#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_ck_errors_BITS 4 1735#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4 1736 1737/* DDR40_CORE_PHY_CONTROL_REGS :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */ 1738#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f 1739#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_dm_errors_ALIGN 0 1740#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_dm_errors_BITS 4 1741#define DDR40_CORE_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0 1742 1743/*************************************************************************** 1744 *COMMAND_REG - DRAM Command Register 1745 ***************************************************************************/ 1746/* DDR40_CORE_PHY_CONTROL_REGS :: COMMAND_REG :: reserved0 [31:29] */ 1747#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_reserved0_MASK 0xe0000000 1748#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_reserved0_ALIGN 0 1749#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_reserved0_BITS 3 1750#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_reserved0_SHIFT 29 1751 1752/* DDR40_CORE_PHY_CONTROL_REGS :: COMMAND_REG :: mpr_mode [28:28] */ 1753#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_mpr_mode_MASK 0x10000000 1754#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_mpr_mode_ALIGN 0 1755#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_mpr_mode_BITS 1 1756#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_mpr_mode_SHIFT 28 1757#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_mpr_mode_DEFAULT 0 1758 1759/* DDR40_CORE_PHY_CONTROL_REGS :: COMMAND_REG :: reserved1 [27:25] */ 1760#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_reserved1_MASK 0x0e000000 1761#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_reserved1_ALIGN 0 1762#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_reserved1_BITS 3 1763#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_reserved1_SHIFT 25 1764 1765/* DDR40_CORE_PHY_CONTROL_REGS :: COMMAND_REG :: aux [24:22] */ 1766#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_aux_MASK 0x01c00000 1767#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_aux_ALIGN 0 1768#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_aux_BITS 3 1769#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_aux_SHIFT 22 1770#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_aux_DEFAULT 0 1771 1772/* DDR40_CORE_PHY_CONTROL_REGS :: COMMAND_REG :: we [21:21] */ 1773#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_we_MASK 0x00200000 1774#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_we_ALIGN 0 1775#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_we_BITS 1 1776#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_we_SHIFT 21 1777#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_we_DEFAULT 0 1778 1779/* DDR40_CORE_PHY_CONTROL_REGS :: COMMAND_REG :: cas [20:20] */ 1780#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_cas_MASK 0x00100000 1781#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_cas_ALIGN 0 1782#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_cas_BITS 1 1783#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_cas_SHIFT 20 1784#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_cas_DEFAULT 0 1785 1786/* DDR40_CORE_PHY_CONTROL_REGS :: COMMAND_REG :: ras [19:19] */ 1787#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ras_MASK 0x00080000 1788#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ras_ALIGN 0 1789#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ras_BITS 1 1790#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ras_SHIFT 19 1791#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ras_DEFAULT 0 1792 1793/* DDR40_CORE_PHY_CONTROL_REGS :: COMMAND_REG :: ba [18:16] */ 1794#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ba_MASK 0x00070000 1795#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ba_ALIGN 0 1796#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ba_BITS 3 1797#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ba_SHIFT 16 1798#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ba_DEFAULT 0 1799 1800/* DDR40_CORE_PHY_CONTROL_REGS :: COMMAND_REG :: ad [15:00] */ 1801#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ad_MASK 0x0000ffff 1802#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ad_ALIGN 0 1803#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ad_BITS 16 1804#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ad_SHIFT 0 1805#define DDR40_CORE_PHY_CONTROL_REGS_COMMAND_REG_ad_DEFAULT 0 1806 1807/*************************************************************************** 1808 *MODE_REG0 - Mode Register 0 1809 ***************************************************************************/ 1810/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG0 :: reserved0 [31:17] */ 1811#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_MASK 0xfffe0000 1812#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_ALIGN 0 1813#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_BITS 15 1814#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_SHIFT 17 1815 1816/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG0 :: valid [16:16] */ 1817#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_valid_MASK 0x00010000 1818#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_valid_ALIGN 0 1819#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_valid_BITS 1 1820#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_valid_SHIFT 16 1821#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_valid_DEFAULT 0 1822 1823/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG0 :: ad [15:00] */ 1824#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_ad_MASK 0x0000ffff 1825#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_ad_ALIGN 0 1826#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_ad_BITS 16 1827#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_ad_SHIFT 0 1828#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG0_ad_DEFAULT 0 1829 1830/*************************************************************************** 1831 *MODE_REG1 - Mode Register 1 1832 ***************************************************************************/ 1833/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG1 :: reserved0 [31:17] */ 1834#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_MASK 0xfffe0000 1835#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_ALIGN 0 1836#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_BITS 15 1837#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_SHIFT 17 1838 1839/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG1 :: valid [16:16] */ 1840#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_valid_MASK 0x00010000 1841#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_valid_ALIGN 0 1842#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_valid_BITS 1 1843#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_valid_SHIFT 16 1844#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_valid_DEFAULT 0 1845 1846/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG1 :: ad [15:00] */ 1847#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_ad_MASK 0x0000ffff 1848#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_ad_ALIGN 0 1849#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_ad_BITS 16 1850#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_ad_SHIFT 0 1851#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG1_ad_DEFAULT 0 1852 1853/*************************************************************************** 1854 *MODE_REG2 - Mode Register 2 1855 ***************************************************************************/ 1856/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG2 :: reserved0 [31:17] */ 1857#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_MASK 0xfffe0000 1858#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_ALIGN 0 1859#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_BITS 15 1860#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_SHIFT 17 1861 1862/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG2 :: valid [16:16] */ 1863#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_valid_MASK 0x00010000 1864#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_valid_ALIGN 0 1865#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_valid_BITS 1 1866#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_valid_SHIFT 16 1867#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_valid_DEFAULT 0 1868 1869/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG2 :: ad [15:00] */ 1870#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_ad_MASK 0x0000ffff 1871#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_ad_ALIGN 0 1872#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_ad_BITS 16 1873#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_ad_SHIFT 0 1874#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG2_ad_DEFAULT 0 1875 1876/*************************************************************************** 1877 *MODE_REG3 - Mode Register 3 1878 ***************************************************************************/ 1879/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG3 :: reserved0 [31:17] */ 1880#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_MASK 0xfffe0000 1881#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_ALIGN 0 1882#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_BITS 15 1883#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_SHIFT 17 1884 1885/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG3 :: valid [16:16] */ 1886#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_valid_MASK 0x00010000 1887#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_valid_ALIGN 0 1888#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_valid_BITS 1 1889#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_valid_SHIFT 16 1890#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_valid_DEFAULT 0 1891 1892/* DDR40_CORE_PHY_CONTROL_REGS :: MODE_REG3 :: ad [15:00] */ 1893#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_ad_MASK 0x0000ffff 1894#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_ad_ALIGN 0 1895#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_ad_BITS 16 1896#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_ad_SHIFT 0 1897#define DDR40_CORE_PHY_CONTROL_REGS_MODE_REG3_ad_DEFAULT 0 1898 1899/*************************************************************************** 1900 *STANDBY_CONTROL - Standby Control register 1901 ***************************************************************************/ 1902/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: reserved0 [31:19] */ 1903#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_MASK 0xfff80000 1904#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_ALIGN 0 1905#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_BITS 13 1906#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_SHIFT 19 1907 1908/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: standby_ready [18:18] */ 1909#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_ready_MASK 0x00040000 1910#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_ready_ALIGN 0 1911#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_ready_BITS 1 1912#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_ready_SHIFT 18 1913#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_ready_DEFAULT 0 1914 1915/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */ 1916#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000 1917#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_exit_pin_en_ALIGN 0 1918#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_exit_pin_en_BITS 1 1919#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17 1920#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0 1921 1922/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: standby_active [16:16] */ 1923#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_active_MASK 0x00010000 1924#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_active_ALIGN 0 1925#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_active_BITS 1 1926#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_active_SHIFT 16 1927#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_active_DEFAULT 0 1928 1929/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: armed [15:15] */ 1930#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_armed_MASK 0x00008000 1931#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_armed_ALIGN 0 1932#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_armed_BITS 1 1933#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_armed_SHIFT 15 1934#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_armed_DEFAULT 0 1935 1936/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: warmstart [14:14] */ 1937#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_warmstart_MASK 0x00004000 1938#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_warmstart_ALIGN 0 1939#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_warmstart_BITS 1 1940#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_warmstart_SHIFT 14 1941#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_warmstart_DEFAULT 0 1942 1943/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */ 1944#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000 1945#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_ldo_volts_ALIGN 0 1946#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_ldo_volts_BITS 2 1947#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12 1948#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0 1949 1950/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */ 1951#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800 1952#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_skip_mrs_ALIGN 0 1953#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_skip_mrs_BITS 1 1954#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11 1955#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0 1956 1957/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */ 1958#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400 1959#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_rst_n_ALIGN 0 1960#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_rst_n_BITS 1 1961#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10 1962#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0 1963 1964/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: pwrdown_cke [09:09] */ 1965#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200 1966#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_cke_ALIGN 0 1967#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_cke_BITS 1 1968#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_cke_SHIFT 9 1969#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0 1970 1971/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: ldo_volts [08:07] */ 1972#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ldo_volts_MASK 0x00000180 1973#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ldo_volts_ALIGN 0 1974#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ldo_volts_BITS 2 1975#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ldo_volts_SHIFT 7 1976#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ldo_volts_DEFAULT 2 1977 1978/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: skip_mrs [06:06] */ 1979#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_skip_mrs_MASK 0x00000040 1980#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_skip_mrs_ALIGN 0 1981#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_skip_mrs_BITS 1 1982#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_skip_mrs_SHIFT 6 1983#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_skip_mrs_DEFAULT 0 1984 1985/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: rst_n [05:05] */ 1986#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_rst_n_MASK 0x00000020 1987#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_rst_n_ALIGN 0 1988#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_rst_n_BITS 1 1989#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_rst_n_SHIFT 5 1990#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_rst_n_DEFAULT 0 1991 1992/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: cke [04:04] */ 1993#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_cke_MASK 0x00000010 1994#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_cke_ALIGN 0 1995#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_cke_BITS 1 1996#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_cke_SHIFT 4 1997#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_cke_DEFAULT 0 1998 1999/* DDR40_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: standby [03:00] */ 2000#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_MASK 0x0000000f 2001#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_ALIGN 0 2002#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_BITS 4 2003#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_SHIFT 0 2004#define DDR40_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_standby_DEFAULT 0 2005 2006/*************************************************************************** 2007 *STRAP_CONTROL - Strap Control register 2008 ***************************************************************************/ 2009/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL :: reserved0 [31:28] */ 2010#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_reserved0_MASK 0xf0000000 2011#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_reserved0_ALIGN 0 2012#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_reserved0_BITS 4 2013#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_reserved0_SHIFT 28 2014 2015/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL :: mhz [27:16] */ 2016#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_mhz_MASK 0x0fff0000 2017#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_mhz_ALIGN 0 2018#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_mhz_BITS 12 2019#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_mhz_SHIFT 16 2020#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_mhz_DEFAULT 0 2021 2022/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL :: ad_width [15:14] */ 2023#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_ad_width_MASK 0x0000c000 2024#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_ad_width_ALIGN 0 2025#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_ad_width_BITS 2 2026#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_ad_width_SHIFT 14 2027#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_ad_width_DEFAULT 0 2028 2029/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL :: dual_rank [13:13] */ 2030#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_dual_rank_MASK 0x00002000 2031#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_dual_rank_ALIGN 0 2032#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_dual_rank_BITS 1 2033#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_dual_rank_SHIFT 13 2034#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_dual_rank_DEFAULT 0 2035 2036/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL :: bus16 [12:12] */ 2037#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_bus16_MASK 0x00001000 2038#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_bus16_ALIGN 0 2039#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_bus16_BITS 1 2040#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_bus16_SHIFT 12 2041#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_bus16_DEFAULT 0 2042 2043/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL :: bus8 [11:11] */ 2044#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_bus8_MASK 0x00000800 2045#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_bus8_ALIGN 0 2046#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_bus8_BITS 1 2047#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_bus8_SHIFT 11 2048#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_bus8_DEFAULT 0 2049 2050/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL :: chip_width [10:10] */ 2051#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_chip_width_MASK 0x00000400 2052#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_chip_width_ALIGN 0 2053#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_chip_width_BITS 1 2054#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_chip_width_SHIFT 10 2055#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_chip_width_DEFAULT 0 2056 2057/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL :: vddq [09:08] */ 2058#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_vddq_MASK 0x00000300 2059#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_vddq_ALIGN 0 2060#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_vddq_BITS 2 2061#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_vddq_SHIFT 8 2062#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_vddq_DEFAULT 0 2063 2064/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL :: chip_size [07:06] */ 2065#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_chip_size_MASK 0x000000c0 2066#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_chip_size_ALIGN 0 2067#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_chip_size_BITS 2 2068#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_chip_size_SHIFT 6 2069#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_chip_size_DEFAULT 0 2070 2071/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL :: jedec_type [05:01] */ 2072#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_jedec_type_MASK 0x0000003e 2073#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_jedec_type_ALIGN 0 2074#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_jedec_type_BITS 5 2075#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_jedec_type_SHIFT 1 2076#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_jedec_type_DEFAULT 0 2077 2078/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL :: straps_valid [00:00] */ 2079#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_straps_valid_MASK 0x00000001 2080#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_straps_valid_ALIGN 0 2081#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_straps_valid_BITS 1 2082#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_straps_valid_SHIFT 0 2083#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL_straps_valid_DEFAULT 0 2084 2085/*************************************************************************** 2086 *STRAP_CONTROL2 - Strap Control register 2087 ***************************************************************************/ 2088/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: reserved0 [31:21] */ 2089#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_reserved0_MASK 0xffe00000 2090#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_reserved0_ALIGN 0 2091#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_reserved0_BITS 11 2092#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_reserved0_SHIFT 21 2093 2094/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: ddr3 [20:20] */ 2095#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_ddr3_MASK 0x00100000 2096#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_ddr3_ALIGN 0 2097#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_ddr3_BITS 1 2098#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_ddr3_SHIFT 20 2099#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_ddr3_DEFAULT 0 2100 2101/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: al [19:17] */ 2102#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_al_MASK 0x000e0000 2103#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_al_ALIGN 0 2104#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_al_BITS 3 2105#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_al_SHIFT 17 2106#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_al_DEFAULT 0 2107 2108/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: wr [16:12] */ 2109#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_wr_MASK 0x0001f000 2110#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_wr_ALIGN 0 2111#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_wr_BITS 5 2112#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_wr_SHIFT 12 2113#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_wr_DEFAULT 0 2114 2115/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: cwl [11:07] */ 2116#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_cwl_MASK 0x00000f80 2117#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_cwl_ALIGN 0 2118#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_cwl_BITS 5 2119#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_cwl_SHIFT 7 2120#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_cwl_DEFAULT 0 2121 2122/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: cl [06:00] */ 2123#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_cl_MASK 0x0000007f 2124#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_cl_ALIGN 0 2125#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_cl_BITS 7 2126#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_cl_SHIFT 0 2127#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_CONTROL2_cl_DEFAULT 0 2128 2129/*************************************************************************** 2130 *STRAP_STATUS - Strap Status register 2131 ***************************************************************************/ 2132/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: reserved0 [31:30] */ 2133#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_reserved0_MASK 0xc0000000 2134#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_reserved0_ALIGN 0 2135#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_reserved0_BITS 2 2136#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_reserved0_SHIFT 30 2137 2138/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: from_reg [29:29] */ 2139#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_from_reg_MASK 0x20000000 2140#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_from_reg_ALIGN 0 2141#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_from_reg_BITS 1 2142#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_from_reg_SHIFT 29 2143 2144/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: from_memc [28:28] */ 2145#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_from_memc_MASK 0x10000000 2146#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_from_memc_ALIGN 0 2147#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_from_memc_BITS 1 2148#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_from_memc_SHIFT 28 2149 2150/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: mhz [27:16] */ 2151#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_mhz_MASK 0x0fff0000 2152#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_mhz_ALIGN 0 2153#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_mhz_BITS 12 2154#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_mhz_SHIFT 16 2155 2156/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: ad_width [15:14] */ 2157#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_ad_width_MASK 0x0000c000 2158#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_ad_width_ALIGN 0 2159#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_ad_width_BITS 2 2160#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_ad_width_SHIFT 14 2161 2162/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: dual_rank [13:13] */ 2163#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_dual_rank_MASK 0x00002000 2164#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_dual_rank_ALIGN 0 2165#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_dual_rank_BITS 1 2166#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_dual_rank_SHIFT 13 2167 2168/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: bus16 [12:12] */ 2169#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_bus16_MASK 0x00001000 2170#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_bus16_ALIGN 0 2171#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_bus16_BITS 1 2172#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_bus16_SHIFT 12 2173 2174/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: bus8 [11:11] */ 2175#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_bus8_MASK 0x00000800 2176#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_bus8_ALIGN 0 2177#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_bus8_BITS 1 2178#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_bus8_SHIFT 11 2179 2180/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: chip_width [10:10] */ 2181#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_chip_width_MASK 0x00000400 2182#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_chip_width_ALIGN 0 2183#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_chip_width_BITS 1 2184#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_chip_width_SHIFT 10 2185 2186/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: vddq [09:08] */ 2187#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_vddq_MASK 0x00000300 2188#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_vddq_ALIGN 0 2189#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_vddq_BITS 2 2190#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_vddq_SHIFT 8 2191 2192/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: chip_size [07:06] */ 2193#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_chip_size_MASK 0x000000c0 2194#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_chip_size_ALIGN 0 2195#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_chip_size_BITS 2 2196#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_chip_size_SHIFT 6 2197 2198/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: jedec_type [05:01] */ 2199#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_jedec_type_MASK 0x0000003e 2200#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_jedec_type_ALIGN 0 2201#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_jedec_type_BITS 5 2202#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_jedec_type_SHIFT 1 2203 2204/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS :: straps_valid [00:00] */ 2205#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_straps_valid_MASK 0x00000001 2206#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_straps_valid_ALIGN 0 2207#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_straps_valid_BITS 1 2208#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS_straps_valid_SHIFT 0 2209 2210/*************************************************************************** 2211 *STRAP_STATUS2 - Strap Status register 2212 ***************************************************************************/ 2213/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS2 :: reserved0 [31:21] */ 2214#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_reserved0_MASK 0xffe00000 2215#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_reserved0_ALIGN 0 2216#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_reserved0_BITS 11 2217#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_reserved0_SHIFT 21 2218 2219/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS2 :: ddr3 [20:20] */ 2220#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_ddr3_MASK 0x00100000 2221#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_ddr3_ALIGN 0 2222#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_ddr3_BITS 1 2223#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_ddr3_SHIFT 20 2224 2225/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS2 :: al [19:17] */ 2226#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_al_MASK 0x000e0000 2227#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_al_ALIGN 0 2228#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_al_BITS 3 2229#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_al_SHIFT 17 2230 2231/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS2 :: wr [16:12] */ 2232#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_wr_MASK 0x0001f000 2233#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_wr_ALIGN 0 2234#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_wr_BITS 5 2235#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_wr_SHIFT 12 2236 2237/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS2 :: cwl [11:07] */ 2238#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_cwl_MASK 0x00000f80 2239#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_cwl_ALIGN 0 2240#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_cwl_BITS 5 2241#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_cwl_SHIFT 7 2242 2243/* DDR40_CORE_PHY_CONTROL_REGS :: STRAP_STATUS2 :: cl [06:00] */ 2244#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_cl_MASK 0x0000007f 2245#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_cl_ALIGN 0 2246#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_cl_BITS 7 2247#define DDR40_CORE_PHY_CONTROL_REGS_STRAP_STATUS2_cl_SHIFT 0 2248 2249/*************************************************************************** 2250 *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register 2251 ***************************************************************************/ 2252/* DDR40_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */ 2253#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0 2254#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_ALIGN 0 2255#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_BITS 28 2256#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4 2257 2258/* DDR40_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */ 2259#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008 2260#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl1_bl1_ALIGN 0 2261#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl1_bl1_BITS 1 2262#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3 2263#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0 2264 2265/* DDR40_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */ 2266#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004 2267#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl1_bl0_ALIGN 0 2268#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl1_bl0_BITS 1 2269#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2 2270#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0 2271 2272/* DDR40_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */ 2273#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002 2274#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl0_bl1_ALIGN 0 2275#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl0_bl1_BITS 1 2276#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1 2277#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0 2278 2279/* DDR40_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */ 2280#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001 2281#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl0_bl0_ALIGN 0 2282#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl0_bl0_BITS 1 2283#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0 2284#define DDR40_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0 2285 2286/*************************************************************************** 2287 *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register 2288 ***************************************************************************/ 2289/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */ 2290#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000 2291#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_busy_ALIGN 0 2292#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_busy_BITS 1 2293#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31 2294#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0 2295 2296/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */ 2297#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000 2298#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_ALIGN 0 2299#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_BITS 13 2300#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18 2301 2302/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */ 2303#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000 2304#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_ALIGN 0 2305#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_BITS 1 2306#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17 2307#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0 2308 2309/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */ 2310#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000 2311#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_ALIGN 0 2312#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_BITS 1 2313#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16 2314#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0 2315 2316/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */ 2317#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00 2318#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_ALIGN 0 2319#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_BITS 7 2320#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9 2321 2322/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */ 2323#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100 2324#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_ALIGN 0 2325#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_BITS 1 2326#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8 2327#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0 2328 2329/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */ 2330#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0 2331#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_ALIGN 0 2332#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_BITS 2 2333#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6 2334 2335/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */ 2336#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f 2337#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_ALIGN 0 2338#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_BITS 6 2339#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0 2340#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0 2341 2342/*************************************************************************** 2343 *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register 2344 ***************************************************************************/ 2345/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */ 2346#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_busy_MASK 0x80000000 2347#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_busy_ALIGN 0 2348#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_busy_BITS 1 2349#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31 2350#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0 2351 2352/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */ 2353#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000 2354#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved0_ALIGN 0 2355#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved0_BITS 13 2356#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18 2357 2358/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */ 2359#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000 2360#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_force_ALIGN 0 2361#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_force_BITS 1 2362#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17 2363#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0 2364 2365/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */ 2366#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000 2367#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_en_ALIGN 0 2368#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_en_BITS 1 2369#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16 2370#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0 2371 2372/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */ 2373#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00 2374#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved1_ALIGN 0 2375#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved1_BITS 7 2376#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9 2377 2378/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */ 2379#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100 2380#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_byte_sel_ALIGN 0 2381#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_byte_sel_BITS 1 2382#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8 2383#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0 2384 2385/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */ 2386#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0 2387#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved2_ALIGN 0 2388#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved2_BITS 2 2389#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6 2390 2391/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */ 2392#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f 2393#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_step_ALIGN 0 2394#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_step_BITS 6 2395#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0 2396#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0 2397 2398/*************************************************************************** 2399 *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register 2400 ***************************************************************************/ 2401/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */ 2402#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000 2403#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_busy_ALIGN 0 2404#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_busy_BITS 1 2405#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31 2406#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0 2407 2408/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */ 2409#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000 2410#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved0_ALIGN 0 2411#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved0_BITS 13 2412#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18 2413 2414/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */ 2415#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000 2416#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_ALIGN 0 2417#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_BITS 1 2418#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17 2419#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0 2420 2421/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */ 2422#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000 2423#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_ALIGN 0 2424#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_BITS 1 2425#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16 2426#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0 2427 2428/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */ 2429#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00 2430#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved1_ALIGN 0 2431#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved1_BITS 7 2432#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9 2433 2434/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */ 2435#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100 2436#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_ALIGN 0 2437#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_BITS 1 2438#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8 2439#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0 2440 2441/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */ 2442#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0 2443#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved2_ALIGN 0 2444#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved2_BITS 2 2445#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6 2446 2447/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */ 2448#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f 2449#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_ALIGN 0 2450#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_BITS 6 2451#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0 2452#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0 2453 2454/*************************************************************************** 2455 *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register 2456 ***************************************************************************/ 2457/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */ 2458#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000 2459#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_busy_ALIGN 0 2460#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_busy_BITS 1 2461#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31 2462#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0 2463 2464/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */ 2465#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000 2466#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved0_ALIGN 0 2467#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved0_BITS 13 2468#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18 2469 2470/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */ 2471#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000 2472#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_ALIGN 0 2473#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_BITS 1 2474#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17 2475#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0 2476 2477/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */ 2478#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000 2479#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_ALIGN 0 2480#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_BITS 1 2481#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16 2482#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0 2483 2484/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */ 2485#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00 2486#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved1_ALIGN 0 2487#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved1_BITS 7 2488#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9 2489 2490/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */ 2491#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100 2492#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_ALIGN 0 2493#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_BITS 1 2494#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8 2495#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0 2496 2497/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */ 2498#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0 2499#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved2_ALIGN 0 2500#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved2_BITS 2 2501#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6 2502 2503/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */ 2504#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f 2505#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_ALIGN 0 2506#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_BITS 6 2507#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0 2508#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0 2509 2510/*************************************************************************** 2511 *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register 2512 ***************************************************************************/ 2513/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */ 2514#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000 2515#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_ALIGN 0 2516#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_BITS 1 2517#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31 2518#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0 2519 2520/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */ 2521#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000 2522#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_ALIGN 0 2523#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_BITS 13 2524#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18 2525 2526/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */ 2527#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000 2528#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_ALIGN 0 2529#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_BITS 1 2530#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17 2531#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0 2532 2533/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */ 2534#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000 2535#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_ALIGN 0 2536#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_BITS 1 2537#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16 2538#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0 2539 2540/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */ 2541#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00 2542#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_ALIGN 0 2543#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_BITS 7 2544#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9 2545 2546/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */ 2547#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100 2548#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_ALIGN 0 2549#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_BITS 1 2550#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8 2551#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0 2552 2553/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */ 2554#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0 2555#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_ALIGN 0 2556#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_BITS 2 2557#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6 2558 2559/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */ 2560#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f 2561#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_ALIGN 0 2562#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_BITS 6 2563#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0 2564#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0 2565 2566/*************************************************************************** 2567 *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register 2568 ***************************************************************************/ 2569/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */ 2570#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000 2571#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_ALIGN 0 2572#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_BITS 1 2573#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31 2574#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0 2575 2576/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */ 2577#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000 2578#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_ALIGN 0 2579#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_BITS 13 2580#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18 2581 2582/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */ 2583#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000 2584#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_ALIGN 0 2585#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_BITS 1 2586#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17 2587#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0 2588 2589/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */ 2590#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000 2591#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_ALIGN 0 2592#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_BITS 1 2593#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16 2594#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0 2595 2596/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */ 2597#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00 2598#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_ALIGN 0 2599#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_BITS 7 2600#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9 2601 2602/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */ 2603#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100 2604#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_ALIGN 0 2605#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_BITS 1 2606#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8 2607#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0 2608 2609/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */ 2610#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0 2611#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_ALIGN 0 2612#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_BITS 2 2613#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6 2614 2615/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */ 2616#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f 2617#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_ALIGN 0 2618#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_BITS 6 2619#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0 2620#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0 2621 2622/*************************************************************************** 2623 *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register 2624 ***************************************************************************/ 2625/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */ 2626#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000 2627#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_ALIGN 0 2628#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_BITS 1 2629#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31 2630#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0 2631 2632/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */ 2633#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000 2634#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_ALIGN 0 2635#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_BITS 13 2636#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18 2637 2638/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */ 2639#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000 2640#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_ALIGN 0 2641#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_BITS 1 2642#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17 2643#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0 2644 2645/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */ 2646#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000 2647#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_ALIGN 0 2648#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_BITS 1 2649#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16 2650#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0 2651 2652/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */ 2653#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00 2654#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_ALIGN 0 2655#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_BITS 7 2656#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9 2657 2658/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */ 2659#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100 2660#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_ALIGN 0 2661#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_BITS 1 2662#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8 2663#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0 2664 2665/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */ 2666#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0 2667#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_ALIGN 0 2668#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_BITS 2 2669#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6 2670 2671/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */ 2672#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f 2673#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_ALIGN 0 2674#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_BITS 6 2675#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0 2676#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0 2677 2678/*************************************************************************** 2679 *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register 2680 ***************************************************************************/ 2681/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */ 2682#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000 2683#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_ALIGN 0 2684#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_BITS 1 2685#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31 2686#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0 2687 2688/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */ 2689#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000 2690#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_ALIGN 0 2691#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_BITS 13 2692#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18 2693 2694/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */ 2695#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000 2696#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_ALIGN 0 2697#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_BITS 1 2698#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17 2699#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0 2700 2701/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */ 2702#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000 2703#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_ALIGN 0 2704#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_BITS 1 2705#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16 2706#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0 2707 2708/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */ 2709#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00 2710#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_ALIGN 0 2711#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_BITS 7 2712#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9 2713 2714/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */ 2715#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100 2716#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_ALIGN 0 2717#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_BITS 1 2718#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8 2719#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0 2720 2721/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */ 2722#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0 2723#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_ALIGN 0 2724#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_BITS 2 2725#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6 2726 2727/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */ 2728#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f 2729#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_ALIGN 0 2730#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_BITS 6 2731#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0 2732#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0 2733 2734/*************************************************************************** 2735 *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register 2736 ***************************************************************************/ 2737/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */ 2738#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000 2739#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_ALIGN 0 2740#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_BITS 1 2741#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31 2742#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0 2743 2744/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */ 2745#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000 2746#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_ALIGN 0 2747#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_BITS 13 2748#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18 2749 2750/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */ 2751#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000 2752#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_ALIGN 0 2753#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_BITS 1 2754#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17 2755#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0 2756 2757/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */ 2758#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000 2759#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_ALIGN 0 2760#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_BITS 1 2761#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16 2762#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0 2763 2764/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */ 2765#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00 2766#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_ALIGN 0 2767#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_BITS 7 2768#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9 2769 2770/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */ 2771#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100 2772#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_ALIGN 0 2773#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_BITS 1 2774#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8 2775#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0 2776 2777/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */ 2778#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0 2779#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_ALIGN 0 2780#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_BITS 2 2781#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6 2782 2783/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */ 2784#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f 2785#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_ALIGN 0 2786#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_BITS 6 2787#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0 2788#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0 2789 2790/*************************************************************************** 2791 *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register 2792 ***************************************************************************/ 2793/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */ 2794#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000 2795#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_ALIGN 0 2796#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_BITS 1 2797#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31 2798#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0 2799 2800/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */ 2801#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000 2802#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_ALIGN 0 2803#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_BITS 13 2804#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18 2805 2806/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */ 2807#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000 2808#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_ALIGN 0 2809#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_BITS 1 2810#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17 2811#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0 2812 2813/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */ 2814#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000 2815#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_ALIGN 0 2816#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_BITS 1 2817#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16 2818#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0 2819 2820/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */ 2821#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00 2822#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_ALIGN 0 2823#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_BITS 7 2824#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9 2825 2826/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */ 2827#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100 2828#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_ALIGN 0 2829#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_BITS 1 2830#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8 2831#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0 2832 2833/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */ 2834#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0 2835#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_ALIGN 0 2836#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_BITS 2 2837#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6 2838 2839/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */ 2840#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f 2841#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_ALIGN 0 2842#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_BITS 6 2843#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0 2844#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0 2845 2846/*************************************************************************** 2847 *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register 2848 ***************************************************************************/ 2849/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */ 2850#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000 2851#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_ALIGN 0 2852#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_BITS 1 2853#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31 2854#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0 2855 2856/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */ 2857#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000 2858#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_ALIGN 0 2859#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_BITS 13 2860#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18 2861 2862/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */ 2863#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000 2864#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_ALIGN 0 2865#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_BITS 1 2866#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17 2867#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0 2868 2869/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */ 2870#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000 2871#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_ALIGN 0 2872#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_BITS 1 2873#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16 2874#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0 2875 2876/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */ 2877#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00 2878#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_ALIGN 0 2879#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_BITS 7 2880#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9 2881 2882/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */ 2883#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100 2884#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_ALIGN 0 2885#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_BITS 1 2886#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8 2887#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0 2888 2889/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */ 2890#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0 2891#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_ALIGN 0 2892#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_BITS 2 2893#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6 2894 2895/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */ 2896#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f 2897#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_ALIGN 0 2898#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_BITS 6 2899#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0 2900#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0 2901 2902/*************************************************************************** 2903 *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register 2904 ***************************************************************************/ 2905/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */ 2906#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000 2907#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_ALIGN 0 2908#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_BITS 1 2909#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31 2910#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0 2911 2912/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */ 2913#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000 2914#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_ALIGN 0 2915#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_BITS 13 2916#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18 2917 2918/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */ 2919#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000 2920#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_ALIGN 0 2921#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_BITS 1 2922#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17 2923#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0 2924 2925/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */ 2926#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000 2927#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_ALIGN 0 2928#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_BITS 1 2929#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16 2930#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0 2931 2932/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */ 2933#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00 2934#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_ALIGN 0 2935#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_BITS 7 2936#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9 2937 2938/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */ 2939#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100 2940#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_ALIGN 0 2941#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_BITS 1 2942#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8 2943#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0 2944 2945/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */ 2946#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0 2947#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_ALIGN 0 2948#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_BITS 2 2949#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6 2950 2951/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */ 2952#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f 2953#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_ALIGN 0 2954#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_BITS 6 2955#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0 2956#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0 2957 2958/*************************************************************************** 2959 *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register 2960 ***************************************************************************/ 2961/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */ 2962#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000 2963#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_busy_ALIGN 0 2964#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_busy_BITS 1 2965#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31 2966#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0 2967 2968/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */ 2969#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000 2970#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_ALIGN 0 2971#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_BITS 13 2972#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18 2973 2974/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */ 2975#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000 2976#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_ALIGN 0 2977#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_BITS 1 2978#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17 2979#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0 2980 2981/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */ 2982#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000 2983#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_ALIGN 0 2984#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_BITS 1 2985#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16 2986#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0 2987 2988/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */ 2989#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00 2990#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_ALIGN 0 2991#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_BITS 7 2992#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9 2993 2994/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */ 2995#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100 2996#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_ALIGN 0 2997#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_BITS 1 2998#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8 2999#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0 3000 3001/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */ 3002#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0 3003#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_ALIGN 0 3004#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_BITS 2 3005#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6 3006 3007/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */ 3008#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f 3009#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_ALIGN 0 3010#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_BITS 6 3011#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0 3012#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0 3013 3014/*************************************************************************** 3015 *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register 3016 ***************************************************************************/ 3017/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */ 3018#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000 3019#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_ALIGN 0 3020#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_BITS 1 3021#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31 3022#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0 3023 3024/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */ 3025#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000 3026#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_ALIGN 0 3027#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_BITS 13 3028#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18 3029 3030/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */ 3031#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000 3032#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_ALIGN 0 3033#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_BITS 1 3034#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17 3035#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0 3036 3037/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */ 3038#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000 3039#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_ALIGN 0 3040#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_BITS 1 3041#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16 3042#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0 3043 3044/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */ 3045#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00 3046#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_ALIGN 0 3047#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_BITS 7 3048#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9 3049 3050/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */ 3051#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100 3052#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_ALIGN 0 3053#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_BITS 1 3054#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8 3055#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0 3056 3057/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */ 3058#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0 3059#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_ALIGN 0 3060#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_BITS 2 3061#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6 3062 3063/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */ 3064#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f 3065#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_ALIGN 0 3066#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_BITS 6 3067#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0 3068#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0 3069 3070/*************************************************************************** 3071 *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register 3072 ***************************************************************************/ 3073/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */ 3074#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000 3075#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_ALIGN 0 3076#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_BITS 1 3077#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31 3078#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0 3079 3080/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */ 3081#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000 3082#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_ALIGN 0 3083#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_BITS 13 3084#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18 3085 3086/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */ 3087#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000 3088#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_ALIGN 0 3089#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_BITS 1 3090#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17 3091#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0 3092 3093/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */ 3094#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000 3095#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_ALIGN 0 3096#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_BITS 1 3097#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16 3098#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0 3099 3100/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */ 3101#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00 3102#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_ALIGN 0 3103#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_BITS 7 3104#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9 3105 3106/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */ 3107#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100 3108#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_ALIGN 0 3109#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_BITS 1 3110#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8 3111#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0 3112 3113/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */ 3114#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0 3115#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_ALIGN 0 3116#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_BITS 2 3117#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6 3118 3119/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */ 3120#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f 3121#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_ALIGN 0 3122#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_BITS 6 3123#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0 3124#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0 3125 3126/*************************************************************************** 3127 *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register 3128 ***************************************************************************/ 3129/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */ 3130#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000 3131#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_ALIGN 0 3132#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_BITS 1 3133#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31 3134#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0 3135 3136/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */ 3137#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000 3138#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_ALIGN 0 3139#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_BITS 13 3140#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18 3141 3142/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */ 3143#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000 3144#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_ALIGN 0 3145#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_BITS 1 3146#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17 3147#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0 3148 3149/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */ 3150#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000 3151#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_ALIGN 0 3152#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_BITS 1 3153#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16 3154#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0 3155 3156/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */ 3157#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00 3158#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_ALIGN 0 3159#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_BITS 7 3160#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9 3161 3162/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */ 3163#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100 3164#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_ALIGN 0 3165#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_BITS 1 3166#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8 3167#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0 3168 3169/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */ 3170#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0 3171#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_ALIGN 0 3172#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_BITS 2 3173#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6 3174 3175/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */ 3176#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f 3177#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_ALIGN 0 3178#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_BITS 6 3179#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0 3180#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0 3181 3182/*************************************************************************** 3183 *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register 3184 ***************************************************************************/ 3185/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */ 3186#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000 3187#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_ALIGN 0 3188#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_BITS 1 3189#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31 3190#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0 3191 3192/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */ 3193#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000 3194#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_ALIGN 0 3195#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_BITS 13 3196#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18 3197 3198/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */ 3199#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000 3200#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_ALIGN 0 3201#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_BITS 1 3202#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17 3203#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0 3204 3205/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */ 3206#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000 3207#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_ALIGN 0 3208#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_BITS 1 3209#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16 3210#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0 3211 3212/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */ 3213#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00 3214#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_ALIGN 0 3215#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_BITS 7 3216#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9 3217 3218/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */ 3219#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100 3220#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_ALIGN 0 3221#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_BITS 1 3222#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8 3223#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0 3224 3225/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */ 3226#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0 3227#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_ALIGN 0 3228#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_BITS 2 3229#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6 3230 3231/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */ 3232#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f 3233#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_ALIGN 0 3234#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_BITS 6 3235#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0 3236#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0 3237 3238/*************************************************************************** 3239 *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register 3240 ***************************************************************************/ 3241/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */ 3242#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000 3243#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_ALIGN 0 3244#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_BITS 1 3245#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31 3246#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0 3247 3248/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */ 3249#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000 3250#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_ALIGN 0 3251#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_BITS 13 3252#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18 3253 3254/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */ 3255#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000 3256#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_ALIGN 0 3257#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_BITS 1 3258#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17 3259#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0 3260 3261/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */ 3262#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000 3263#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_ALIGN 0 3264#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_BITS 1 3265#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16 3266#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0 3267 3268/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */ 3269#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00 3270#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_ALIGN 0 3271#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_BITS 7 3272#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9 3273 3274/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */ 3275#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100 3276#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_ALIGN 0 3277#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_BITS 1 3278#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8 3279#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0 3280 3281/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */ 3282#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0 3283#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_ALIGN 0 3284#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_BITS 2 3285#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6 3286 3287/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */ 3288#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f 3289#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_ALIGN 0 3290#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_BITS 6 3291#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0 3292#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0 3293 3294/*************************************************************************** 3295 *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register 3296 ***************************************************************************/ 3297/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */ 3298#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000 3299#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_ALIGN 0 3300#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_BITS 1 3301#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31 3302#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0 3303 3304/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */ 3305#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000 3306#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_ALIGN 0 3307#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_BITS 13 3308#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18 3309 3310/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */ 3311#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000 3312#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_ALIGN 0 3313#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_BITS 1 3314#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17 3315#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0 3316 3317/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */ 3318#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000 3319#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_ALIGN 0 3320#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_BITS 1 3321#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16 3322#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0 3323 3324/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */ 3325#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00 3326#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_ALIGN 0 3327#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_BITS 7 3328#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9 3329 3330/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */ 3331#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100 3332#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_ALIGN 0 3333#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_BITS 1 3334#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8 3335#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0 3336 3337/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */ 3338#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0 3339#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_ALIGN 0 3340#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_BITS 2 3341#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6 3342 3343/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */ 3344#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f 3345#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_ALIGN 0 3346#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_BITS 6 3347#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0 3348#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0 3349 3350/*************************************************************************** 3351 *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register 3352 ***************************************************************************/ 3353/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */ 3354#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000 3355#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_ALIGN 0 3356#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_BITS 1 3357#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31 3358#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0 3359 3360/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */ 3361#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000 3362#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_ALIGN 0 3363#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_BITS 13 3364#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18 3365 3366/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */ 3367#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000 3368#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_ALIGN 0 3369#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_BITS 1 3370#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17 3371#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0 3372 3373/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */ 3374#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000 3375#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_ALIGN 0 3376#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_BITS 1 3377#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16 3378#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0 3379 3380/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */ 3381#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00 3382#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_ALIGN 0 3383#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_BITS 7 3384#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9 3385 3386/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */ 3387#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100 3388#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_ALIGN 0 3389#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_BITS 1 3390#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8 3391#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0 3392 3393/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */ 3394#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0 3395#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_ALIGN 0 3396#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_BITS 2 3397#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6 3398 3399/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */ 3400#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f 3401#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_ALIGN 0 3402#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_BITS 6 3403#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0 3404#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0 3405 3406/*************************************************************************** 3407 *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register 3408 ***************************************************************************/ 3409/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */ 3410#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000 3411#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_ALIGN 0 3412#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_BITS 1 3413#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31 3414#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0 3415 3416/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */ 3417#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000 3418#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_ALIGN 0 3419#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_BITS 13 3420#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18 3421 3422/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */ 3423#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000 3424#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_ALIGN 0 3425#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_BITS 1 3426#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17 3427#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0 3428 3429/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */ 3430#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000 3431#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_ALIGN 0 3432#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_BITS 1 3433#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16 3434#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0 3435 3436/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */ 3437#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00 3438#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_ALIGN 0 3439#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_BITS 7 3440#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9 3441 3442/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */ 3443#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100 3444#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_ALIGN 0 3445#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_BITS 1 3446#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8 3447#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0 3448 3449/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */ 3450#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0 3451#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_ALIGN 0 3452#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_BITS 2 3453#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6 3454 3455/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */ 3456#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f 3457#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_ALIGN 0 3458#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_BITS 6 3459#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0 3460#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0 3461 3462/*************************************************************************** 3463 *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register 3464 ***************************************************************************/ 3465/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */ 3466#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000 3467#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_ALIGN 0 3468#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_BITS 1 3469#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31 3470#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0 3471 3472/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */ 3473#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000 3474#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_ALIGN 0 3475#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_BITS 13 3476#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18 3477 3478/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */ 3479#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000 3480#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_ALIGN 0 3481#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_BITS 1 3482#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17 3483#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0 3484 3485/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */ 3486#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000 3487#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_ALIGN 0 3488#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_BITS 1 3489#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16 3490#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0 3491 3492/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */ 3493#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00 3494#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_ALIGN 0 3495#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_BITS 7 3496#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9 3497 3498/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */ 3499#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100 3500#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_ALIGN 0 3501#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_BITS 1 3502#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8 3503#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0 3504 3505/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */ 3506#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0 3507#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_ALIGN 0 3508#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_BITS 2 3509#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6 3510 3511/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */ 3512#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f 3513#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_ALIGN 0 3514#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_BITS 6 3515#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0 3516#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0 3517 3518/*************************************************************************** 3519 *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register 3520 ***************************************************************************/ 3521/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */ 3522#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000 3523#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_ALIGN 0 3524#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_BITS 1 3525#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31 3526#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0 3527 3528/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */ 3529#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000 3530#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_ALIGN 0 3531#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_BITS 13 3532#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18 3533 3534/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */ 3535#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000 3536#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_ALIGN 0 3537#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_BITS 1 3538#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17 3539#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0 3540 3541/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */ 3542#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000 3543#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_ALIGN 0 3544#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_BITS 1 3545#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16 3546#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0 3547 3548/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */ 3549#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00 3550#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_ALIGN 0 3551#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_BITS 7 3552#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9 3553 3554/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */ 3555#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100 3556#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_ALIGN 0 3557#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_BITS 1 3558#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8 3559#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0 3560 3561/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */ 3562#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0 3563#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_ALIGN 0 3564#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_BITS 2 3565#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6 3566 3567/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */ 3568#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f 3569#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_ALIGN 0 3570#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_BITS 6 3571#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0 3572#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0 3573 3574/*************************************************************************** 3575 *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register 3576 ***************************************************************************/ 3577/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */ 3578#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000 3579#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_ALIGN 0 3580#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_BITS 1 3581#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31 3582#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0 3583 3584/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */ 3585#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000 3586#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_ALIGN 0 3587#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_BITS 13 3588#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18 3589 3590/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */ 3591#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000 3592#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_ALIGN 0 3593#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_BITS 1 3594#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17 3595#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0 3596 3597/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */ 3598#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000 3599#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_ALIGN 0 3600#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_BITS 1 3601#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16 3602#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0 3603 3604/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */ 3605#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00 3606#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_ALIGN 0 3607#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_BITS 7 3608#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9 3609 3610/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */ 3611#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100 3612#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_ALIGN 0 3613#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_BITS 1 3614#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8 3615#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0 3616 3617/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */ 3618#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0 3619#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_ALIGN 0 3620#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_BITS 2 3621#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6 3622 3623/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */ 3624#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f 3625#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_ALIGN 0 3626#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_BITS 6 3627#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0 3628#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0 3629 3630/*************************************************************************** 3631 *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register 3632 ***************************************************************************/ 3633/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */ 3634#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000 3635#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_ALIGN 0 3636#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_BITS 1 3637#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31 3638#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0 3639 3640/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */ 3641#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000 3642#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_ALIGN 0 3643#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_BITS 13 3644#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18 3645 3646/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */ 3647#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000 3648#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_ALIGN 0 3649#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_BITS 1 3650#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17 3651#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0 3652 3653/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */ 3654#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000 3655#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_ALIGN 0 3656#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_BITS 1 3657#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16 3658#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0 3659 3660/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */ 3661#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00 3662#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_ALIGN 0 3663#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_BITS 7 3664#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9 3665 3666/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */ 3667#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100 3668#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_ALIGN 0 3669#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_BITS 1 3670#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8 3671#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0 3672 3673/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */ 3674#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0 3675#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_ALIGN 0 3676#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_BITS 2 3677#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6 3678 3679/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */ 3680#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f 3681#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_ALIGN 0 3682#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_BITS 6 3683#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0 3684#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0 3685 3686/*************************************************************************** 3687 *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register 3688 ***************************************************************************/ 3689/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */ 3690#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000 3691#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_ALIGN 0 3692#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_BITS 1 3693#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31 3694#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0 3695 3696/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */ 3697#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000 3698#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_ALIGN 0 3699#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_BITS 13 3700#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18 3701 3702/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */ 3703#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000 3704#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_ALIGN 0 3705#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_BITS 1 3706#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17 3707#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0 3708 3709/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */ 3710#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000 3711#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_ALIGN 0 3712#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_BITS 1 3713#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16 3714#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0 3715 3716/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */ 3717#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00 3718#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_ALIGN 0 3719#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_BITS 7 3720#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9 3721 3722/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */ 3723#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100 3724#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_ALIGN 0 3725#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_BITS 1 3726#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8 3727#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0 3728 3729/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */ 3730#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0 3731#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_ALIGN 0 3732#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_BITS 2 3733#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6 3734 3735/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */ 3736#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f 3737#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_ALIGN 0 3738#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_BITS 6 3739#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0 3740#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0 3741 3742/*************************************************************************** 3743 *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register 3744 ***************************************************************************/ 3745/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */ 3746#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000 3747#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_ALIGN 0 3748#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_BITS 1 3749#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31 3750#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0 3751 3752/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */ 3753#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000 3754#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_ALIGN 0 3755#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_BITS 13 3756#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18 3757 3758/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */ 3759#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000 3760#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_ALIGN 0 3761#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_BITS 1 3762#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17 3763#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0 3764 3765/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */ 3766#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000 3767#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_ALIGN 0 3768#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_BITS 1 3769#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16 3770#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0 3771 3772/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */ 3773#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00 3774#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_ALIGN 0 3775#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_BITS 7 3776#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9 3777 3778/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */ 3779#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100 3780#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_ALIGN 0 3781#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_BITS 1 3782#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8 3783#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0 3784 3785/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */ 3786#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0 3787#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_ALIGN 0 3788#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_BITS 2 3789#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6 3790 3791/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */ 3792#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f 3793#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_ALIGN 0 3794#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_BITS 6 3795#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0 3796#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0 3797 3798/*************************************************************************** 3799 *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register 3800 ***************************************************************************/ 3801/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */ 3802#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000 3803#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_ALIGN 0 3804#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_BITS 1 3805#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31 3806#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0 3807 3808/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */ 3809#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000 3810#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_ALIGN 0 3811#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_BITS 13 3812#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18 3813 3814/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */ 3815#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000 3816#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_ALIGN 0 3817#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_BITS 1 3818#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17 3819#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0 3820 3821/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */ 3822#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000 3823#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_ALIGN 0 3824#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_BITS 1 3825#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16 3826#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0 3827 3828/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */ 3829#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00 3830#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_ALIGN 0 3831#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_BITS 7 3832#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9 3833 3834/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */ 3835#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100 3836#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_ALIGN 0 3837#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_BITS 1 3838#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8 3839#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0 3840 3841/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */ 3842#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0 3843#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_ALIGN 0 3844#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_BITS 2 3845#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6 3846 3847/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */ 3848#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f 3849#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_ALIGN 0 3850#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_BITS 6 3851#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0 3852#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0 3853 3854/*************************************************************************** 3855 *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register 3856 ***************************************************************************/ 3857/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */ 3858#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000 3859#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_ALIGN 0 3860#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_BITS 1 3861#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31 3862#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0 3863 3864/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */ 3865#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000 3866#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_ALIGN 0 3867#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_BITS 13 3868#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18 3869 3870/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */ 3871#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000 3872#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_ALIGN 0 3873#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_BITS 1 3874#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17 3875#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0 3876 3877/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */ 3878#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000 3879#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_ALIGN 0 3880#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_BITS 1 3881#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16 3882#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0 3883 3884/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */ 3885#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00 3886#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_ALIGN 0 3887#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_BITS 7 3888#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9 3889 3890/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */ 3891#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100 3892#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_ALIGN 0 3893#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_BITS 1 3894#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8 3895#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0 3896 3897/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */ 3898#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0 3899#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_ALIGN 0 3900#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_BITS 2 3901#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6 3902 3903/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */ 3904#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f 3905#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_ALIGN 0 3906#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_BITS 6 3907#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0 3908#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0 3909 3910/*************************************************************************** 3911 *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register 3912 ***************************************************************************/ 3913/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */ 3914#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000 3915#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_ALIGN 0 3916#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_BITS 1 3917#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31 3918#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0 3919 3920/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */ 3921#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000 3922#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_ALIGN 0 3923#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_BITS 13 3924#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18 3925 3926/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */ 3927#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000 3928#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_ALIGN 0 3929#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_BITS 1 3930#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17 3931#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0 3932 3933/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */ 3934#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000 3935#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_ALIGN 0 3936#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_BITS 1 3937#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16 3938#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0 3939 3940/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */ 3941#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00 3942#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_ALIGN 0 3943#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_BITS 7 3944#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9 3945 3946/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */ 3947#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100 3948#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_ALIGN 0 3949#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_BITS 1 3950#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8 3951#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0 3952 3953/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */ 3954#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0 3955#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_ALIGN 0 3956#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_BITS 2 3957#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6 3958 3959/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */ 3960#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f 3961#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_ALIGN 0 3962#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_BITS 6 3963#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0 3964#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0 3965 3966/*************************************************************************** 3967 *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register 3968 ***************************************************************************/ 3969/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */ 3970#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_busy_MASK 0x80000000 3971#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_busy_ALIGN 0 3972#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_busy_BITS 1 3973#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31 3974#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0 3975 3976/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */ 3977#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000 3978#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved0_ALIGN 0 3979#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved0_BITS 13 3980#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18 3981 3982/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */ 3983#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000 3984#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_force_ALIGN 0 3985#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_force_BITS 1 3986#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17 3987#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0 3988 3989/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */ 3990#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000 3991#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_en_ALIGN 0 3992#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_en_BITS 1 3993#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16 3994#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0 3995 3996/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */ 3997#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00 3998#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved1_ALIGN 0 3999#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved1_BITS 7 4000#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9 4001 4002/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */ 4003#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100 4004#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_byte_sel_ALIGN 0 4005#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_byte_sel_BITS 1 4006#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8 4007#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0 4008 4009/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */ 4010#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0 4011#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved2_ALIGN 0 4012#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved2_BITS 2 4013#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6 4014 4015/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */ 4016#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f 4017#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_step_ALIGN 0 4018#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_step_BITS 6 4019#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0 4020#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0 4021 4022/*************************************************************************** 4023 *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register 4024 ***************************************************************************/ 4025/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */ 4026#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000 4027#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_busy_ALIGN 0 4028#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_busy_BITS 1 4029#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31 4030#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0 4031 4032/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */ 4033#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000 4034#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved0_ALIGN 0 4035#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved0_BITS 13 4036#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18 4037 4038/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */ 4039#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000 4040#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_ALIGN 0 4041#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_BITS 1 4042#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17 4043#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0 4044 4045/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */ 4046#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000 4047#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_ALIGN 0 4048#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_BITS 1 4049#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16 4050#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0 4051 4052/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */ 4053#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00 4054#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved1_ALIGN 0 4055#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved1_BITS 7 4056#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9 4057 4058/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */ 4059#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100 4060#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_ALIGN 0 4061#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_BITS 1 4062#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8 4063#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0 4064 4065/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */ 4066#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0 4067#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved2_ALIGN 0 4068#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved2_BITS 2 4069#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6 4070 4071/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */ 4072#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f 4073#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_ALIGN 0 4074#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_BITS 6 4075#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0 4076#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0 4077 4078/*************************************************************************** 4079 *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register 4080 ***************************************************************************/ 4081/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */ 4082#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000 4083#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_busy_ALIGN 0 4084#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_busy_BITS 1 4085#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31 4086#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0 4087 4088/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */ 4089#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000 4090#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved0_ALIGN 0 4091#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved0_BITS 13 4092#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18 4093 4094/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */ 4095#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000 4096#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_ALIGN 0 4097#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_BITS 1 4098#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17 4099#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0 4100 4101/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */ 4102#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000 4103#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_ALIGN 0 4104#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_BITS 1 4105#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16 4106#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0 4107 4108/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */ 4109#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00 4110#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved1_ALIGN 0 4111#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved1_BITS 7 4112#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9 4113 4114/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */ 4115#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100 4116#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_ALIGN 0 4117#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_BITS 1 4118#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8 4119#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0 4120 4121/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */ 4122#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0 4123#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved2_ALIGN 0 4124#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved2_BITS 2 4125#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6 4126 4127/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */ 4128#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f 4129#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_ALIGN 0 4130#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_BITS 6 4131#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0 4132#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0 4133 4134/*************************************************************************** 4135 *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register 4136 ***************************************************************************/ 4137/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */ 4138#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000 4139#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_ALIGN 0 4140#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_BITS 1 4141#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31 4142#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0 4143 4144/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */ 4145#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000 4146#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_ALIGN 0 4147#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_BITS 13 4148#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18 4149 4150/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */ 4151#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000 4152#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_ALIGN 0 4153#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_BITS 1 4154#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17 4155#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0 4156 4157/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */ 4158#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000 4159#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_ALIGN 0 4160#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_BITS 1 4161#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16 4162#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0 4163 4164/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */ 4165#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00 4166#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_ALIGN 0 4167#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_BITS 7 4168#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9 4169 4170/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */ 4171#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100 4172#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_ALIGN 0 4173#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_BITS 1 4174#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8 4175#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0 4176 4177/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */ 4178#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0 4179#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_ALIGN 0 4180#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_BITS 2 4181#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6 4182 4183/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */ 4184#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f 4185#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_ALIGN 0 4186#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_BITS 6 4187#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0 4188#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0 4189 4190/*************************************************************************** 4191 *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register 4192 ***************************************************************************/ 4193/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */ 4194#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000 4195#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_ALIGN 0 4196#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_BITS 1 4197#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31 4198#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0 4199 4200/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */ 4201#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000 4202#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_ALIGN 0 4203#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_BITS 13 4204#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18 4205 4206/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */ 4207#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000 4208#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_ALIGN 0 4209#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_BITS 1 4210#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17 4211#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0 4212 4213/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */ 4214#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000 4215#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_ALIGN 0 4216#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_BITS 1 4217#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16 4218#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0 4219 4220/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */ 4221#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00 4222#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_ALIGN 0 4223#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_BITS 7 4224#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9 4225 4226/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */ 4227#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100 4228#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_ALIGN 0 4229#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_BITS 1 4230#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8 4231#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0 4232 4233/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */ 4234#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0 4235#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_ALIGN 0 4236#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_BITS 2 4237#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6 4238 4239/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */ 4240#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f 4241#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_ALIGN 0 4242#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_BITS 6 4243#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0 4244#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0 4245 4246/*************************************************************************** 4247 *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register 4248 ***************************************************************************/ 4249/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */ 4250#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000 4251#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_ALIGN 0 4252#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_BITS 1 4253#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31 4254#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0 4255 4256/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */ 4257#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000 4258#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_ALIGN 0 4259#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_BITS 13 4260#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18 4261 4262/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */ 4263#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000 4264#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_ALIGN 0 4265#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_BITS 1 4266#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17 4267#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0 4268 4269/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */ 4270#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000 4271#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_ALIGN 0 4272#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_BITS 1 4273#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16 4274#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0 4275 4276/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */ 4277#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00 4278#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_ALIGN 0 4279#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_BITS 7 4280#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9 4281 4282/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */ 4283#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100 4284#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_ALIGN 0 4285#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_BITS 1 4286#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8 4287#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0 4288 4289/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */ 4290#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0 4291#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_ALIGN 0 4292#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_BITS 2 4293#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6 4294 4295/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */ 4296#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f 4297#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_ALIGN 0 4298#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_BITS 6 4299#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0 4300#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0 4301 4302/*************************************************************************** 4303 *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register 4304 ***************************************************************************/ 4305/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */ 4306#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000 4307#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_ALIGN 0 4308#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_BITS 1 4309#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31 4310#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0 4311 4312/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */ 4313#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000 4314#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_ALIGN 0 4315#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_BITS 13 4316#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18 4317 4318/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */ 4319#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000 4320#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_ALIGN 0 4321#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_BITS 1 4322#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17 4323#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0 4324 4325/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */ 4326#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000 4327#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_ALIGN 0 4328#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_BITS 1 4329#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16 4330#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0 4331 4332/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */ 4333#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00 4334#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_ALIGN 0 4335#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_BITS 7 4336#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9 4337 4338/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */ 4339#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100 4340#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_ALIGN 0 4341#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_BITS 1 4342#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8 4343#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0 4344 4345/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */ 4346#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0 4347#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_ALIGN 0 4348#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_BITS 2 4349#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6 4350 4351/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */ 4352#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f 4353#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_ALIGN 0 4354#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_BITS 6 4355#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0 4356#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0 4357 4358/*************************************************************************** 4359 *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register 4360 ***************************************************************************/ 4361/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */ 4362#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000 4363#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_ALIGN 0 4364#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_BITS 1 4365#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31 4366#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0 4367 4368/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */ 4369#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000 4370#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_ALIGN 0 4371#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_BITS 13 4372#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18 4373 4374/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */ 4375#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000 4376#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_ALIGN 0 4377#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_BITS 1 4378#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17 4379#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0 4380 4381/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */ 4382#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000 4383#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_ALIGN 0 4384#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_BITS 1 4385#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16 4386#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0 4387 4388/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */ 4389#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00 4390#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_ALIGN 0 4391#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_BITS 7 4392#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9 4393 4394/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */ 4395#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100 4396#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_ALIGN 0 4397#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_BITS 1 4398#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8 4399#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0 4400 4401/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */ 4402#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0 4403#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_ALIGN 0 4404#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_BITS 2 4405#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6 4406 4407/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */ 4408#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f 4409#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_ALIGN 0 4410#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_BITS 6 4411#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0 4412#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0 4413 4414/*************************************************************************** 4415 *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register 4416 ***************************************************************************/ 4417/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */ 4418#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000 4419#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_ALIGN 0 4420#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_BITS 1 4421#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31 4422#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0 4423 4424/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */ 4425#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000 4426#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_ALIGN 0 4427#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_BITS 13 4428#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18 4429 4430/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */ 4431#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000 4432#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_ALIGN 0 4433#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_BITS 1 4434#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17 4435#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0 4436 4437/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */ 4438#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000 4439#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_ALIGN 0 4440#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_BITS 1 4441#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16 4442#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0 4443 4444/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */ 4445#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00 4446#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_ALIGN 0 4447#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_BITS 7 4448#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9 4449 4450/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */ 4451#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100 4452#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_ALIGN 0 4453#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_BITS 1 4454#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8 4455#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0 4456 4457/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */ 4458#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0 4459#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_ALIGN 0 4460#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_BITS 2 4461#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6 4462 4463/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */ 4464#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f 4465#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_ALIGN 0 4466#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_BITS 6 4467#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0 4468#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0 4469 4470/*************************************************************************** 4471 *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register 4472 ***************************************************************************/ 4473/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */ 4474#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000 4475#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_ALIGN 0 4476#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_BITS 1 4477#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31 4478#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0 4479 4480/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */ 4481#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000 4482#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_ALIGN 0 4483#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_BITS 13 4484#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18 4485 4486/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */ 4487#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000 4488#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_ALIGN 0 4489#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_BITS 1 4490#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17 4491#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0 4492 4493/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */ 4494#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000 4495#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_ALIGN 0 4496#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_BITS 1 4497#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16 4498#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0 4499 4500/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */ 4501#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00 4502#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_ALIGN 0 4503#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_BITS 7 4504#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9 4505 4506/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */ 4507#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100 4508#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_ALIGN 0 4509#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_BITS 1 4510#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8 4511#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0 4512 4513/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */ 4514#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0 4515#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_ALIGN 0 4516#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_BITS 2 4517#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6 4518 4519/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */ 4520#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f 4521#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_ALIGN 0 4522#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_BITS 6 4523#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0 4524#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0 4525 4526/*************************************************************************** 4527 *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register 4528 ***************************************************************************/ 4529/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */ 4530#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000 4531#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_ALIGN 0 4532#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_BITS 1 4533#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31 4534#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0 4535 4536/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */ 4537#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000 4538#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_ALIGN 0 4539#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_BITS 13 4540#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18 4541 4542/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */ 4543#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000 4544#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_ALIGN 0 4545#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_BITS 1 4546#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17 4547#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0 4548 4549/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */ 4550#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000 4551#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_ALIGN 0 4552#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_BITS 1 4553#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16 4554#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0 4555 4556/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */ 4557#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00 4558#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_ALIGN 0 4559#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_BITS 7 4560#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9 4561 4562/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */ 4563#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100 4564#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_ALIGN 0 4565#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_BITS 1 4566#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8 4567#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0 4568 4569/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */ 4570#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0 4571#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_ALIGN 0 4572#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_BITS 2 4573#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6 4574 4575/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */ 4576#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f 4577#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_ALIGN 0 4578#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_BITS 6 4579#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0 4580#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0 4581 4582/*************************************************************************** 4583 *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register 4584 ***************************************************************************/ 4585/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */ 4586#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000 4587#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_busy_ALIGN 0 4588#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_busy_BITS 1 4589#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31 4590#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0 4591 4592/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */ 4593#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000 4594#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_ALIGN 0 4595#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_BITS 13 4596#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18 4597 4598/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */ 4599#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000 4600#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_ALIGN 0 4601#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_BITS 1 4602#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17 4603#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0 4604 4605/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */ 4606#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000 4607#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_ALIGN 0 4608#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_BITS 1 4609#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16 4610#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0 4611 4612/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */ 4613#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00 4614#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_ALIGN 0 4615#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_BITS 7 4616#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9 4617 4618/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */ 4619#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100 4620#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_ALIGN 0 4621#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_BITS 1 4622#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8 4623#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0 4624 4625/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */ 4626#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0 4627#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_ALIGN 0 4628#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_BITS 2 4629#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6 4630 4631/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */ 4632#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f 4633#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_ALIGN 0 4634#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_BITS 6 4635#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0 4636#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0 4637 4638/*************************************************************************** 4639 *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register 4640 ***************************************************************************/ 4641/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */ 4642#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000 4643#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_ALIGN 0 4644#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_BITS 1 4645#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31 4646#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0 4647 4648/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */ 4649#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000 4650#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_ALIGN 0 4651#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_BITS 13 4652#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18 4653 4654/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */ 4655#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000 4656#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_ALIGN 0 4657#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_BITS 1 4658#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17 4659#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0 4660 4661/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */ 4662#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000 4663#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_ALIGN 0 4664#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_BITS 1 4665#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16 4666#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0 4667 4668/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */ 4669#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00 4670#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_ALIGN 0 4671#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_BITS 7 4672#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9 4673 4674/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */ 4675#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100 4676#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_ALIGN 0 4677#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_BITS 1 4678#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8 4679#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0 4680 4681/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */ 4682#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0 4683#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_ALIGN 0 4684#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_BITS 2 4685#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6 4686 4687/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */ 4688#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f 4689#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_ALIGN 0 4690#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_BITS 6 4691#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0 4692#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0 4693 4694/*************************************************************************** 4695 *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register 4696 ***************************************************************************/ 4697/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */ 4698#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000 4699#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_ALIGN 0 4700#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_BITS 1 4701#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31 4702#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0 4703 4704/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */ 4705#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000 4706#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_ALIGN 0 4707#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_BITS 13 4708#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18 4709 4710/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */ 4711#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000 4712#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_ALIGN 0 4713#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_BITS 1 4714#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17 4715#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0 4716 4717/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */ 4718#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000 4719#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_ALIGN 0 4720#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_BITS 1 4721#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16 4722#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0 4723 4724/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */ 4725#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00 4726#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_ALIGN 0 4727#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_BITS 7 4728#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9 4729 4730/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */ 4731#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100 4732#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_ALIGN 0 4733#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_BITS 1 4734#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8 4735#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0 4736 4737/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */ 4738#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0 4739#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_ALIGN 0 4740#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_BITS 2 4741#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6 4742 4743/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */ 4744#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f 4745#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_ALIGN 0 4746#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_BITS 6 4747#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0 4748#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0 4749 4750/*************************************************************************** 4751 *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register 4752 ***************************************************************************/ 4753/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */ 4754#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000 4755#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_ALIGN 0 4756#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_BITS 1 4757#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31 4758#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0 4759 4760/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */ 4761#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000 4762#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_ALIGN 0 4763#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_BITS 13 4764#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18 4765 4766/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */ 4767#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000 4768#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_ALIGN 0 4769#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_BITS 1 4770#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17 4771#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0 4772 4773/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */ 4774#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000 4775#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_ALIGN 0 4776#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_BITS 1 4777#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16 4778#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0 4779 4780/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */ 4781#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00 4782#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_ALIGN 0 4783#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_BITS 7 4784#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9 4785 4786/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */ 4787#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100 4788#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_ALIGN 0 4789#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_BITS 1 4790#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8 4791#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0 4792 4793/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */ 4794#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0 4795#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_ALIGN 0 4796#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_BITS 2 4797#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6 4798 4799/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */ 4800#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f 4801#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_ALIGN 0 4802#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_BITS 6 4803#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0 4804#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0 4805 4806/*************************************************************************** 4807 *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register 4808 ***************************************************************************/ 4809/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */ 4810#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000 4811#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_ALIGN 0 4812#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_BITS 1 4813#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31 4814#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0 4815 4816/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */ 4817#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000 4818#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_ALIGN 0 4819#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_BITS 13 4820#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18 4821 4822/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */ 4823#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000 4824#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_ALIGN 0 4825#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_BITS 1 4826#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17 4827#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0 4828 4829/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */ 4830#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000 4831#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_ALIGN 0 4832#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_BITS 1 4833#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16 4834#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0 4835 4836/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */ 4837#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00 4838#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_ALIGN 0 4839#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_BITS 7 4840#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9 4841 4842/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */ 4843#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100 4844#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_ALIGN 0 4845#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_BITS 1 4846#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8 4847#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0 4848 4849/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */ 4850#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0 4851#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_ALIGN 0 4852#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_BITS 2 4853#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6 4854 4855/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */ 4856#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f 4857#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_ALIGN 0 4858#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_BITS 6 4859#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0 4860#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0 4861 4862/*************************************************************************** 4863 *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register 4864 ***************************************************************************/ 4865/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */ 4866#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000 4867#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_ALIGN 0 4868#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_BITS 1 4869#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31 4870#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0 4871 4872/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */ 4873#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000 4874#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_ALIGN 0 4875#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_BITS 13 4876#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18 4877 4878/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */ 4879#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000 4880#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_ALIGN 0 4881#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_BITS 1 4882#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17 4883#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0 4884 4885/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */ 4886#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000 4887#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_ALIGN 0 4888#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_BITS 1 4889#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16 4890#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0 4891 4892/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */ 4893#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00 4894#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_ALIGN 0 4895#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_BITS 7 4896#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9 4897 4898/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */ 4899#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100 4900#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_ALIGN 0 4901#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_BITS 1 4902#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8 4903#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0 4904 4905/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */ 4906#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0 4907#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_ALIGN 0 4908#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_BITS 2 4909#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6 4910 4911/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */ 4912#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f 4913#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_ALIGN 0 4914#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_BITS 6 4915#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0 4916#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0 4917 4918/*************************************************************************** 4919 *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register 4920 ***************************************************************************/ 4921/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */ 4922#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000 4923#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_ALIGN 0 4924#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_BITS 1 4925#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31 4926#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0 4927 4928/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */ 4929#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000 4930#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_ALIGN 0 4931#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_BITS 13 4932#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18 4933 4934/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */ 4935#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000 4936#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_ALIGN 0 4937#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_BITS 1 4938#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17 4939#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0 4940 4941/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */ 4942#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000 4943#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_ALIGN 0 4944#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_BITS 1 4945#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16 4946#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0 4947 4948/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */ 4949#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00 4950#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_ALIGN 0 4951#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_BITS 7 4952#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9 4953 4954/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */ 4955#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100 4956#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_ALIGN 0 4957#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_BITS 1 4958#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8 4959#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0 4960 4961/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */ 4962#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0 4963#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_ALIGN 0 4964#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_BITS 2 4965#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6 4966 4967/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */ 4968#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f 4969#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_ALIGN 0 4970#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_BITS 6 4971#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0 4972#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0 4973 4974/*************************************************************************** 4975 *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register 4976 ***************************************************************************/ 4977/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */ 4978#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000 4979#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_ALIGN 0 4980#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_BITS 1 4981#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31 4982#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0 4983 4984/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */ 4985#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000 4986#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_ALIGN 0 4987#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_BITS 13 4988#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18 4989 4990/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */ 4991#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000 4992#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_ALIGN 0 4993#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_BITS 1 4994#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17 4995#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0 4996 4997/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */ 4998#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000 4999#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_ALIGN 0 5000#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_BITS 1 5001#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16 5002#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0 5003 5004/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */ 5005#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00 5006#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_ALIGN 0 5007#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_BITS 7 5008#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9 5009 5010/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */ 5011#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100 5012#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_ALIGN 0 5013#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_BITS 1 5014#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8 5015#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0 5016 5017/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */ 5018#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0 5019#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_ALIGN 0 5020#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_BITS 2 5021#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6 5022 5023/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */ 5024#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f 5025#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_ALIGN 0 5026#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_BITS 6 5027#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0 5028#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0 5029 5030/*************************************************************************** 5031 *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register 5032 ***************************************************************************/ 5033/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */ 5034#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000 5035#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_ALIGN 0 5036#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_BITS 1 5037#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31 5038#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0 5039 5040/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */ 5041#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000 5042#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_ALIGN 0 5043#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_BITS 13 5044#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18 5045 5046/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */ 5047#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000 5048#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_ALIGN 0 5049#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_BITS 1 5050#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17 5051#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0 5052 5053/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */ 5054#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000 5055#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_ALIGN 0 5056#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_BITS 1 5057#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16 5058#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0 5059 5060/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */ 5061#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00 5062#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_ALIGN 0 5063#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_BITS 7 5064#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9 5065 5066/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */ 5067#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100 5068#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_ALIGN 0 5069#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_BITS 1 5070#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8 5071#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0 5072 5073/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */ 5074#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0 5075#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_ALIGN 0 5076#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_BITS 2 5077#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6 5078 5079/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */ 5080#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f 5081#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_ALIGN 0 5082#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_BITS 6 5083#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0 5084#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0 5085 5086/*************************************************************************** 5087 *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register 5088 ***************************************************************************/ 5089/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */ 5090#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000 5091#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_ALIGN 0 5092#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_BITS 1 5093#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31 5094#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0 5095 5096/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */ 5097#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000 5098#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_ALIGN 0 5099#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_BITS 13 5100#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18 5101 5102/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */ 5103#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000 5104#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_ALIGN 0 5105#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_BITS 1 5106#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17 5107#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0 5108 5109/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */ 5110#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000 5111#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_ALIGN 0 5112#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_BITS 1 5113#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16 5114#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0 5115 5116/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */ 5117#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00 5118#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_ALIGN 0 5119#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_BITS 7 5120#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9 5121 5122/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */ 5123#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100 5124#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_ALIGN 0 5125#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_BITS 1 5126#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8 5127#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0 5128 5129/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */ 5130#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0 5131#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_ALIGN 0 5132#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_BITS 2 5133#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6 5134 5135/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */ 5136#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f 5137#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_ALIGN 0 5138#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_BITS 6 5139#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0 5140#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0 5141 5142/*************************************************************************** 5143 *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register 5144 ***************************************************************************/ 5145/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */ 5146#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000 5147#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_ALIGN 0 5148#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_BITS 1 5149#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31 5150#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0 5151 5152/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */ 5153#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000 5154#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_ALIGN 0 5155#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_BITS 13 5156#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18 5157 5158/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */ 5159#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000 5160#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_ALIGN 0 5161#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_BITS 1 5162#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17 5163#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0 5164 5165/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */ 5166#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000 5167#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_ALIGN 0 5168#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_BITS 1 5169#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16 5170#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0 5171 5172/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */ 5173#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00 5174#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_ALIGN 0 5175#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_BITS 7 5176#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9 5177 5178/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */ 5179#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100 5180#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_ALIGN 0 5181#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_BITS 1 5182#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8 5183#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0 5184 5185/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */ 5186#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0 5187#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_ALIGN 0 5188#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_BITS 2 5189#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6 5190 5191/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */ 5192#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f 5193#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_ALIGN 0 5194#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_BITS 6 5195#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0 5196#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0 5197 5198/*************************************************************************** 5199 *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register 5200 ***************************************************************************/ 5201/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */ 5202#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000 5203#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_ALIGN 0 5204#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_BITS 1 5205#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31 5206#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0 5207 5208/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */ 5209#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000 5210#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_ALIGN 0 5211#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_BITS 13 5212#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18 5213 5214/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */ 5215#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000 5216#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_ALIGN 0 5217#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_BITS 1 5218#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17 5219#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0 5220 5221/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */ 5222#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000 5223#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_ALIGN 0 5224#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_BITS 1 5225#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16 5226#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0 5227 5228/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */ 5229#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00 5230#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_ALIGN 0 5231#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_BITS 7 5232#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9 5233 5234/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */ 5235#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100 5236#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_ALIGN 0 5237#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_BITS 1 5238#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8 5239#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0 5240 5241/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */ 5242#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0 5243#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_ALIGN 0 5244#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_BITS 2 5245#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6 5246 5247/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */ 5248#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f 5249#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_ALIGN 0 5250#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_BITS 6 5251#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0 5252#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0 5253 5254/*************************************************************************** 5255 *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register 5256 ***************************************************************************/ 5257/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */ 5258#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000 5259#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_ALIGN 0 5260#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_BITS 1 5261#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31 5262#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0 5263 5264/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */ 5265#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000 5266#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_ALIGN 0 5267#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_BITS 13 5268#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18 5269 5270/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */ 5271#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000 5272#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_ALIGN 0 5273#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_BITS 1 5274#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17 5275#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0 5276 5277/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */ 5278#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000 5279#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_ALIGN 0 5280#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_BITS 1 5281#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16 5282#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0 5283 5284/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */ 5285#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00 5286#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_ALIGN 0 5287#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_BITS 7 5288#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9 5289 5290/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */ 5291#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100 5292#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_ALIGN 0 5293#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_BITS 1 5294#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8 5295#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0 5296 5297/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */ 5298#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0 5299#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_ALIGN 0 5300#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_BITS 2 5301#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6 5302 5303/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */ 5304#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f 5305#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_ALIGN 0 5306#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_BITS 6 5307#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0 5308#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0 5309 5310/*************************************************************************** 5311 *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register 5312 ***************************************************************************/ 5313/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */ 5314#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000 5315#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_ALIGN 0 5316#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_BITS 1 5317#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31 5318#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0 5319 5320/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */ 5321#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000 5322#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_ALIGN 0 5323#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_BITS 13 5324#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18 5325 5326/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */ 5327#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000 5328#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_ALIGN 0 5329#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_BITS 1 5330#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17 5331#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0 5332 5333/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */ 5334#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000 5335#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_ALIGN 0 5336#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_BITS 1 5337#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16 5338#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0 5339 5340/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */ 5341#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00 5342#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_ALIGN 0 5343#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_BITS 7 5344#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9 5345 5346/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */ 5347#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100 5348#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_ALIGN 0 5349#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_BITS 1 5350#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8 5351#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0 5352 5353/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */ 5354#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0 5355#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_ALIGN 0 5356#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_BITS 2 5357#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6 5358 5359/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */ 5360#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f 5361#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_ALIGN 0 5362#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_BITS 6 5363#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0 5364#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0 5365 5366/*************************************************************************** 5367 *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register 5368 ***************************************************************************/ 5369/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */ 5370#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000 5371#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_ALIGN 0 5372#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_BITS 1 5373#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31 5374#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0 5375 5376/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */ 5377#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000 5378#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_ALIGN 0 5379#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_BITS 13 5380#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18 5381 5382/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */ 5383#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000 5384#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_ALIGN 0 5385#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_BITS 1 5386#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17 5387#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0 5388 5389/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */ 5390#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000 5391#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_ALIGN 0 5392#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_BITS 1 5393#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16 5394#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0 5395 5396/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */ 5397#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00 5398#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_ALIGN 0 5399#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_BITS 7 5400#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9 5401 5402/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */ 5403#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100 5404#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_ALIGN 0 5405#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_BITS 1 5406#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8 5407#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0 5408 5409/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */ 5410#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0 5411#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_ALIGN 0 5412#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_BITS 2 5413#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6 5414 5415/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */ 5416#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f 5417#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_ALIGN 0 5418#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_BITS 6 5419#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0 5420#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0 5421 5422/*************************************************************************** 5423 *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register 5424 ***************************************************************************/ 5425/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */ 5426#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000 5427#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_ALIGN 0 5428#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_BITS 1 5429#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31 5430#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0 5431 5432/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */ 5433#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000 5434#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_ALIGN 0 5435#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_BITS 13 5436#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18 5437 5438/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */ 5439#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000 5440#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_ALIGN 0 5441#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_BITS 1 5442#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17 5443#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0 5444 5445/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */ 5446#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000 5447#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_ALIGN 0 5448#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_BITS 1 5449#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16 5450#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0 5451 5452/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */ 5453#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00 5454#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_ALIGN 0 5455#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_BITS 7 5456#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9 5457 5458/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */ 5459#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100 5460#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_ALIGN 0 5461#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_BITS 1 5462#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8 5463#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0 5464 5465/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */ 5466#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0 5467#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_ALIGN 0 5468#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_BITS 2 5469#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6 5470 5471/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */ 5472#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f 5473#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_ALIGN 0 5474#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_BITS 6 5475#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0 5476#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0 5477 5478/*************************************************************************** 5479 *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register 5480 ***************************************************************************/ 5481/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */ 5482#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000 5483#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_ALIGN 0 5484#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_BITS 1 5485#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31 5486#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0 5487 5488/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */ 5489#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000 5490#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_ALIGN 0 5491#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_BITS 13 5492#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18 5493 5494/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */ 5495#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000 5496#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_ALIGN 0 5497#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_BITS 1 5498#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17 5499#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0 5500 5501/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */ 5502#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000 5503#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_ALIGN 0 5504#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_BITS 1 5505#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16 5506#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0 5507 5508/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */ 5509#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00 5510#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_ALIGN 0 5511#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_BITS 7 5512#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9 5513 5514/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */ 5515#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100 5516#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_ALIGN 0 5517#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_BITS 1 5518#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8 5519#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0 5520 5521/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */ 5522#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0 5523#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_ALIGN 0 5524#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_BITS 2 5525#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6 5526 5527/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */ 5528#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f 5529#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_ALIGN 0 5530#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_BITS 6 5531#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0 5532#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0 5533 5534/*************************************************************************** 5535 *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register 5536 ***************************************************************************/ 5537/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */ 5538#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000 5539#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_ALIGN 0 5540#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_BITS 1 5541#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31 5542#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0 5543 5544/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */ 5545#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000 5546#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_ALIGN 0 5547#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_BITS 13 5548#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18 5549 5550/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */ 5551#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000 5552#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_ALIGN 0 5553#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_BITS 1 5554#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17 5555#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0 5556 5557/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */ 5558#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000 5559#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_ALIGN 0 5560#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_BITS 1 5561#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16 5562#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0 5563 5564/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */ 5565#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00 5566#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_ALIGN 0 5567#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_BITS 7 5568#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9 5569 5570/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */ 5571#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100 5572#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_ALIGN 0 5573#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_BITS 1 5574#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8 5575#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0 5576 5577/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */ 5578#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0 5579#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_ALIGN 0 5580#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_BITS 2 5581#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6 5582 5583/* DDR40_CORE_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */ 5584#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f 5585#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_ALIGN 0 5586#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_BITS 6 5587#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0 5588#define DDR40_CORE_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0 5589 5590/*************************************************************************** 5591 *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register 5592 ***************************************************************************/ 5593/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */ 5594#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000 5595#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_ALIGN 0 5596#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_BITS 15 5597#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17 5598 5599/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */ 5600#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000 5601#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_ALIGN 0 5602#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_BITS 1 5603#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16 5604#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0 5605 5606/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */ 5607#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00 5608#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_ALIGN 0 5609#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_BITS 7 5610#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9 5611 5612/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */ 5613#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100 5614#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_ALIGN 0 5615#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_BITS 1 5616#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8 5617#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0 5618 5619/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */ 5620#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0 5621#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_ALIGN 0 5622#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_BITS 2 5623#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6 5624 5625/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */ 5626#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f 5627#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_ALIGN 0 5628#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_BITS 6 5629#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0 5630#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0 5631 5632/*************************************************************************** 5633 *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register 5634 ***************************************************************************/ 5635/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */ 5636#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000 5637#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_ALIGN 0 5638#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_BITS 15 5639#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17 5640 5641/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */ 5642#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000 5643#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_ALIGN 0 5644#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_BITS 1 5645#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16 5646#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0 5647 5648/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */ 5649#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00 5650#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_ALIGN 0 5651#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_BITS 7 5652#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9 5653 5654/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */ 5655#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100 5656#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_ALIGN 0 5657#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_BITS 1 5658#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8 5659#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0 5660 5661/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */ 5662#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0 5663#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_ALIGN 0 5664#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_BITS 2 5665#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6 5666 5667/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */ 5668#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f 5669#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_ALIGN 0 5670#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_BITS 6 5671#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0 5672#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0 5673 5674/*************************************************************************** 5675 *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register 5676 ***************************************************************************/ 5677/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */ 5678#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000 5679#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_ALIGN 0 5680#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_BITS 7 5681#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25 5682 5683/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */ 5684#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000 5685#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_ALIGN 0 5686#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_BITS 1 5687#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24 5688#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0 5689 5690/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */ 5691#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000 5692#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_ALIGN 0 5693#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_BITS 8 5694#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16 5695#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0 5696 5697/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */ 5698#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00 5699#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_ALIGN 0 5700#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_BITS 7 5701#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9 5702 5703/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */ 5704#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100 5705#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_ALIGN 0 5706#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_BITS 1 5707#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8 5708#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0 5709 5710/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */ 5711#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0 5712#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_ALIGN 0 5713#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_BITS 2 5714#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6 5715 5716/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */ 5717#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f 5718#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_ALIGN 0 5719#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_BITS 6 5720#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0 5721#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0 5722 5723/*************************************************************************** 5724 *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register 5725 ***************************************************************************/ 5726/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */ 5727#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000 5728#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_ALIGN 0 5729#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_BITS 7 5730#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25 5731 5732/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */ 5733#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000 5734#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_ALIGN 0 5735#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_BITS 1 5736#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24 5737#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0 5738 5739/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */ 5740#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000 5741#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_ALIGN 0 5742#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_BITS 8 5743#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16 5744#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0 5745 5746/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */ 5747#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00 5748#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_ALIGN 0 5749#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_BITS 7 5750#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9 5751 5752/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */ 5753#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100 5754#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_ALIGN 0 5755#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_BITS 1 5756#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8 5757#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0 5758 5759/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */ 5760#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0 5761#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_ALIGN 0 5762#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_BITS 2 5763#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6 5764 5765/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */ 5766#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f 5767#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_ALIGN 0 5768#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_BITS 6 5769#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0 5770#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0 5771 5772/*************************************************************************** 5773 *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register 5774 ***************************************************************************/ 5775/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */ 5776#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000 5777#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_ALIGN 0 5778#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_BITS 15 5779#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17 5780 5781/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */ 5782#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000 5783#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_ALIGN 0 5784#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_BITS 1 5785#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16 5786#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0 5787 5788/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */ 5789#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00 5790#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_ALIGN 0 5791#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_BITS 7 5792#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9 5793 5794/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */ 5795#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100 5796#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_ALIGN 0 5797#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_BITS 1 5798#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8 5799#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0 5800 5801/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */ 5802#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0 5803#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_ALIGN 0 5804#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_BITS 2 5805#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6 5806 5807/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */ 5808#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f 5809#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_ALIGN 0 5810#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_BITS 6 5811#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0 5812#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0 5813 5814/*************************************************************************** 5815 *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register 5816 ***************************************************************************/ 5817/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */ 5818#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000 5819#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_ALIGN 0 5820#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_BITS 7 5821#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25 5822 5823/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */ 5824#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000 5825#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_ALIGN 0 5826#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_BITS 1 5827#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24 5828#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0 5829 5830/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */ 5831#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000 5832#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_ALIGN 0 5833#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_BITS 8 5834#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16 5835#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0 5836 5837/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */ 5838#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00 5839#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_ALIGN 0 5840#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_BITS 7 5841#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9 5842 5843/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */ 5844#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100 5845#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_ALIGN 0 5846#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_BITS 1 5847#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8 5848#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0 5849 5850/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */ 5851#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0 5852#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_ALIGN 0 5853#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_BITS 2 5854#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6 5855 5856/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */ 5857#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f 5858#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_ALIGN 0 5859#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_BITS 6 5860#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0 5861#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0 5862 5863/*************************************************************************** 5864 *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register 5865 ***************************************************************************/ 5866/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */ 5867#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000 5868#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_ALIGN 0 5869#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_BITS 15 5870#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17 5871 5872/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */ 5873#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000 5874#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_ALIGN 0 5875#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_BITS 1 5876#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16 5877#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0 5878 5879/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */ 5880#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00 5881#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_ALIGN 0 5882#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_BITS 7 5883#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9 5884 5885/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */ 5886#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100 5887#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_ALIGN 0 5888#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_BITS 1 5889#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8 5890#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0 5891 5892/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */ 5893#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0 5894#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_ALIGN 0 5895#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_BITS 2 5896#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6 5897 5898/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */ 5899#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f 5900#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_ALIGN 0 5901#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_BITS 6 5902#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0 5903#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0 5904 5905/*************************************************************************** 5906 *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register 5907 ***************************************************************************/ 5908/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */ 5909#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000 5910#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_ALIGN 0 5911#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_BITS 15 5912#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17 5913 5914/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */ 5915#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000 5916#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_ALIGN 0 5917#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_BITS 1 5918#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16 5919#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0 5920 5921/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */ 5922#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00 5923#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_ALIGN 0 5924#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_BITS 7 5925#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9 5926 5927/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */ 5928#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100 5929#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_ALIGN 0 5930#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_BITS 1 5931#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8 5932#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0 5933 5934/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */ 5935#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0 5936#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_ALIGN 0 5937#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_BITS 2 5938#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6 5939 5940/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */ 5941#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f 5942#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_ALIGN 0 5943#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_BITS 6 5944#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0 5945#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0 5946 5947/*************************************************************************** 5948 *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register 5949 ***************************************************************************/ 5950/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */ 5951#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000 5952#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_ALIGN 0 5953#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_BITS 7 5954#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25 5955 5956/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */ 5957#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000 5958#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_ALIGN 0 5959#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_BITS 1 5960#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24 5961#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0 5962 5963/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */ 5964#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000 5965#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_ALIGN 0 5966#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_BITS 8 5967#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16 5968#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0 5969 5970/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */ 5971#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00 5972#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_ALIGN 0 5973#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_BITS 7 5974#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9 5975 5976/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */ 5977#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100 5978#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_ALIGN 0 5979#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_BITS 1 5980#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8 5981#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0 5982 5983/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */ 5984#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0 5985#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_ALIGN 0 5986#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_BITS 2 5987#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6 5988 5989/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */ 5990#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f 5991#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_ALIGN 0 5992#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_BITS 6 5993#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0 5994#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0 5995 5996/*************************************************************************** 5997 *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register 5998 ***************************************************************************/ 5999/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */ 6000#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000 6001#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_ALIGN 0 6002#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_BITS 7 6003#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25 6004 6005/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */ 6006#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000 6007#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_ALIGN 0 6008#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_BITS 1 6009#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24 6010#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0 6011 6012/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */ 6013#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000 6014#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_ALIGN 0 6015#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_BITS 8 6016#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16 6017#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0 6018 6019/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */ 6020#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00 6021#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_ALIGN 0 6022#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_BITS 7 6023#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9 6024 6025/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */ 6026#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100 6027#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_ALIGN 0 6028#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_BITS 1 6029#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8 6030#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0 6031 6032/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */ 6033#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0 6034#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_ALIGN 0 6035#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_BITS 2 6036#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6 6037 6038/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */ 6039#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f 6040#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_ALIGN 0 6041#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_BITS 6 6042#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0 6043#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0 6044 6045/*************************************************************************** 6046 *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register 6047 ***************************************************************************/ 6048/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */ 6049#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000 6050#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_ALIGN 0 6051#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_BITS 15 6052#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17 6053 6054/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */ 6055#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000 6056#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_ALIGN 0 6057#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_BITS 1 6058#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16 6059#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0 6060 6061/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */ 6062#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00 6063#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_ALIGN 0 6064#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_BITS 7 6065#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9 6066 6067/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */ 6068#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100 6069#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_ALIGN 0 6070#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_BITS 1 6071#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8 6072#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0 6073 6074/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */ 6075#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0 6076#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_ALIGN 0 6077#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_BITS 2 6078#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6 6079 6080/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */ 6081#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f 6082#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_ALIGN 0 6083#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_BITS 6 6084#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0 6085#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0 6086 6087/*************************************************************************** 6088 *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register 6089 ***************************************************************************/ 6090/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */ 6091#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000 6092#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_ALIGN 0 6093#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_BITS 7 6094#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25 6095 6096/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */ 6097#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000 6098#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_ALIGN 0 6099#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_BITS 1 6100#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24 6101#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0 6102 6103/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */ 6104#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000 6105#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_ALIGN 0 6106#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_BITS 8 6107#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16 6108#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0 6109 6110/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */ 6111#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00 6112#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_ALIGN 0 6113#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_BITS 7 6114#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9 6115 6116/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */ 6117#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100 6118#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_ALIGN 0 6119#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_BITS 1 6120#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8 6121#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0 6122 6123/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */ 6124#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0 6125#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_ALIGN 0 6126#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_BITS 2 6127#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6 6128 6129/* DDR40_CORE_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */ 6130#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f 6131#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_ALIGN 0 6132#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_BITS 6 6133#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0 6134#define DDR40_CORE_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0 6135 6136/*************************************************************************** 6137 *READ_DATA_DLY - Word Lane read channel control register 6138 ***************************************************************************/ 6139/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_DATA_DLY :: reserved0 [31:03] */ 6140#define DDR40_CORE_PHY_WORD_LANE_0_READ_DATA_DLY_reserved0_MASK 0xfffffff8 6141#define DDR40_CORE_PHY_WORD_LANE_0_READ_DATA_DLY_reserved0_ALIGN 0 6142#define DDR40_CORE_PHY_WORD_LANE_0_READ_DATA_DLY_reserved0_BITS 29 6143#define DDR40_CORE_PHY_WORD_LANE_0_READ_DATA_DLY_reserved0_SHIFT 3 6144 6145/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */ 6146#define DDR40_CORE_PHY_WORD_LANE_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007 6147#define DDR40_CORE_PHY_WORD_LANE_0_READ_DATA_DLY_rd_data_dly_ALIGN 0 6148#define DDR40_CORE_PHY_WORD_LANE_0_READ_DATA_DLY_rd_data_dly_BITS 3 6149#define DDR40_CORE_PHY_WORD_LANE_0_READ_DATA_DLY_rd_data_dly_SHIFT 0 6150#define DDR40_CORE_PHY_WORD_LANE_0_READ_DATA_DLY_rd_data_dly_DEFAULT 1 6151 6152/*************************************************************************** 6153 *READ_CONTROL - Word Lane read channel control register 6154 ***************************************************************************/ 6155/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_CONTROL :: reserved0 [31:03] */ 6156#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_reserved0_MASK 0xfffffff8 6157#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_reserved0_ALIGN 0 6158#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_reserved0_BITS 29 6159#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_reserved0_SHIFT 3 6160 6161/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_CONTROL :: dq_odt_enable [02:02] */ 6162#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004 6163#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_enable_ALIGN 0 6164#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_enable_BITS 1 6165#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_enable_SHIFT 2 6166#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_enable_DEFAULT 1 6167 6168/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */ 6169#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002 6170#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_te_adj_ALIGN 0 6171#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_te_adj_BITS 1 6172#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1 6173#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 1 6174 6175/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */ 6176#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001 6177#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_le_adj_ALIGN 0 6178#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_le_adj_BITS 1 6179#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0 6180#define DDR40_CORE_PHY_WORD_LANE_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0 6181 6182/*************************************************************************** 6183 *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data 6184 ***************************************************************************/ 6185/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */ 6186#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000 6187#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_reserved0_ALIGN 0 6188#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_reserved0_BITS 16 6189#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16 6190 6191/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */ 6192#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00 6193#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_data_p_ALIGN 0 6194#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_data_p_BITS 8 6195#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8 6196 6197/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */ 6198#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff 6199#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_data_n_ALIGN 0 6200#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_data_n_BITS 8 6201#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0 6202 6203/*************************************************************************** 6204 *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data 6205 ***************************************************************************/ 6206/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */ 6207#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000 6208#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_reserved0_ALIGN 0 6209#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_reserved0_BITS 16 6210#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16 6211 6212/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */ 6213#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00 6214#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_data_p_ALIGN 0 6215#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_data_p_BITS 8 6216#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8 6217 6218/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */ 6219#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff 6220#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_data_n_ALIGN 0 6221#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_data_n_BITS 8 6222#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0 6223 6224/*************************************************************************** 6225 *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data 6226 ***************************************************************************/ 6227/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */ 6228#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000 6229#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_reserved0_ALIGN 0 6230#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_reserved0_BITS 16 6231#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16 6232 6233/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */ 6234#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00 6235#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_data_p_ALIGN 0 6236#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_data_p_BITS 8 6237#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8 6238 6239/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */ 6240#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff 6241#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_data_n_ALIGN 0 6242#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_data_n_BITS 8 6243#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0 6244 6245/*************************************************************************** 6246 *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data 6247 ***************************************************************************/ 6248/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */ 6249#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000 6250#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_reserved0_ALIGN 0 6251#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_reserved0_BITS 16 6252#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16 6253 6254/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */ 6255#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00 6256#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_data_p_ALIGN 0 6257#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_data_p_BITS 8 6258#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8 6259 6260/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */ 6261#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff 6262#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_data_n_ALIGN 0 6263#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_data_n_BITS 8 6264#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0 6265 6266/*************************************************************************** 6267 *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data 6268 ***************************************************************************/ 6269/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */ 6270#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000 6271#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_reserved0_ALIGN 0 6272#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_reserved0_BITS 16 6273#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16 6274 6275/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */ 6276#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00 6277#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_data_p_ALIGN 0 6278#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_data_p_BITS 8 6279#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8 6280 6281/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */ 6282#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff 6283#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_data_n_ALIGN 0 6284#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_data_n_BITS 8 6285#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0 6286 6287/*************************************************************************** 6288 *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data 6289 ***************************************************************************/ 6290/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */ 6291#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000 6292#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_reserved0_ALIGN 0 6293#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_reserved0_BITS 16 6294#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16 6295 6296/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */ 6297#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00 6298#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_data_p_ALIGN 0 6299#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_data_p_BITS 8 6300#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8 6301 6302/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */ 6303#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff 6304#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_data_n_ALIGN 0 6305#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_data_n_BITS 8 6306#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0 6307 6308/*************************************************************************** 6309 *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data 6310 ***************************************************************************/ 6311/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */ 6312#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000 6313#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_reserved0_ALIGN 0 6314#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_reserved0_BITS 16 6315#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16 6316 6317/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */ 6318#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00 6319#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_data_p_ALIGN 0 6320#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_data_p_BITS 8 6321#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8 6322 6323/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */ 6324#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff 6325#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_data_n_ALIGN 0 6326#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_data_n_BITS 8 6327#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0 6328 6329/*************************************************************************** 6330 *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data 6331 ***************************************************************************/ 6332/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */ 6333#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000 6334#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_reserved0_ALIGN 0 6335#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_reserved0_BITS 16 6336#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16 6337 6338/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */ 6339#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00 6340#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_data_p_ALIGN 0 6341#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_data_p_BITS 8 6342#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8 6343 6344/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */ 6345#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff 6346#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_data_n_ALIGN 0 6347#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_data_n_BITS 8 6348#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0 6349 6350/*************************************************************************** 6351 *READ_FIFO_STATUS - Read fifo status register 6352 ***************************************************************************/ 6353/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */ 6354#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00 6355#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_reserved0_ALIGN 0 6356#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_reserved0_BITS 24 6357#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_reserved0_SHIFT 8 6358 6359/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_STATUS :: status1 [07:04] */ 6360#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_status1_MASK 0x000000f0 6361#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_status1_ALIGN 0 6362#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_status1_BITS 4 6363#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_status1_SHIFT 4 6364#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_status1_DEFAULT 0 6365 6366/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_STATUS :: status0 [03:00] */ 6367#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_status0_MASK 0x0000000f 6368#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_status0_ALIGN 0 6369#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_status0_BITS 4 6370#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_status0_SHIFT 0 6371#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_STATUS_status0_DEFAULT 0 6372 6373/*************************************************************************** 6374 *READ_FIFO_CLEAR - Read fifo status clear register 6375 ***************************************************************************/ 6376/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 6377#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe 6378#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_CLEAR_reserved0_ALIGN 0 6379#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_CLEAR_reserved0_BITS 31 6380#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_CLEAR_reserved0_SHIFT 1 6381 6382/* DDR40_CORE_PHY_WORD_LANE_0 :: READ_FIFO_CLEAR :: clear [00:00] */ 6383#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_CLEAR_clear_MASK 0x00000001 6384#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_CLEAR_clear_ALIGN 0 6385#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_CLEAR_clear_BITS 1 6386#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_CLEAR_clear_SHIFT 0 6387#define DDR40_CORE_PHY_WORD_LANE_0_READ_FIFO_CLEAR_clear_DEFAULT 0 6388 6389/*************************************************************************** 6390 *IDLE_PAD_CONTROL - Idle mode SSTL pad control register 6391 ***************************************************************************/ 6392/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: idle [31:31] */ 6393#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_idle_MASK 0x80000000 6394#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_idle_ALIGN 0 6395#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_idle_BITS 1 6396#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_idle_SHIFT 31 6397#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_idle_DEFAULT 0 6398 6399/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */ 6400#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000 6401#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_reserved0_ALIGN 0 6402#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_reserved0_BITS 7 6403#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24 6404 6405/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */ 6406#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000 6407#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_ALIGN 0 6408#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_BITS 2 6409#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22 6410#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 1 6411 6412/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */ 6413#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000 6414#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_ALIGN 0 6415#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_BITS 2 6416#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20 6417#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 1 6418 6419/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */ 6420#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000 6421#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_rxenb_ALIGN 0 6422#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_rxenb_BITS 1 6423#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19 6424#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 1 6425 6426/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */ 6427#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000 6428#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_iddq_ALIGN 0 6429#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_iddq_BITS 1 6430#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18 6431#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 1 6432 6433/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */ 6434#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_reb_MASK 0x00020000 6435#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_reb_ALIGN 0 6436#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_reb_BITS 1 6437#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17 6438#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 1 6439 6440/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */ 6441#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_oeb_MASK 0x00010000 6442#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_oeb_ALIGN 0 6443#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_oeb_BITS 1 6444#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16 6445#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 1 6446 6447/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */ 6448#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000 6449#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_rxenb_ALIGN 0 6450#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_rxenb_BITS 1 6451#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15 6452#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0 6453 6454/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */ 6455#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000 6456#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_ALIGN 0 6457#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_BITS 1 6458#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14 6459#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0 6460 6461/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */ 6462#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000 6463#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_reb_ALIGN 0 6464#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_reb_BITS 1 6465#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13 6466#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 1 6467 6468/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */ 6469#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000 6470#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_oeb_ALIGN 0 6471#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_oeb_BITS 1 6472#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12 6473#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0 6474 6475/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */ 6476#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800 6477#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_rxenb_ALIGN 0 6478#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_rxenb_BITS 1 6479#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11 6480#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 1 6481 6482/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */ 6483#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400 6484#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_ALIGN 0 6485#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_BITS 1 6486#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10 6487#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 1 6488 6489/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */ 6490#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200 6491#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_reb_ALIGN 0 6492#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_reb_BITS 1 6493#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9 6494#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 1 6495 6496/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */ 6497#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100 6498#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_oeb_ALIGN 0 6499#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_oeb_BITS 1 6500#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8 6501#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 1 6502 6503/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */ 6504#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080 6505#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_rxenb_ALIGN 0 6506#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_rxenb_BITS 1 6507#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7 6508#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 1 6509 6510/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */ 6511#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040 6512#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_iddq_ALIGN 0 6513#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_iddq_BITS 1 6514#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6 6515#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0 6516 6517/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */ 6518#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020 6519#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_reb_ALIGN 0 6520#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_reb_BITS 1 6521#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5 6522#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 1 6523 6524/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */ 6525#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010 6526#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_oeb_ALIGN 0 6527#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_oeb_BITS 1 6528#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4 6529#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0 6530 6531/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */ 6532#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008 6533#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_rxenb_ALIGN 0 6534#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_rxenb_BITS 1 6535#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3 6536#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 1 6537 6538/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */ 6539#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004 6540#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_iddq_ALIGN 0 6541#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_iddq_BITS 1 6542#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2 6543#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0 6544 6545/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */ 6546#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002 6547#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_reb_ALIGN 0 6548#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_reb_BITS 1 6549#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1 6550#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 1 6551 6552/* DDR40_CORE_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */ 6553#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001 6554#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_oeb_ALIGN 0 6555#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_oeb_BITS 1 6556#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0 6557#define DDR40_CORE_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0 6558 6559/*************************************************************************** 6560 *DRIVE_PAD_CTL - SSTL pad drive characteristics control register 6561 ***************************************************************************/ 6562/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */ 6563#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_reserved0_MASK 0xfffff000 6564#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_reserved0_ALIGN 0 6565#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_reserved0_BITS 20 6566#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_reserved0_SHIFT 12 6567 6568/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */ 6569#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_no_dqs_rd_MASK 0x00000800 6570#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_no_dqs_rd_ALIGN 0 6571#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_no_dqs_rd_BITS 1 6572#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11 6573#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0 6574 6575/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */ 6576#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400 6577#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_dqs_always_on_ALIGN 0 6578#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_dqs_always_on_BITS 1 6579#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10 6580#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 1 6581 6582/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */ 6583#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200 6584#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_dqs_tx_dis_ALIGN 0 6585#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_dqs_tx_dis_BITS 1 6586#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9 6587#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0 6588 6589/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */ 6590#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100 6591#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_half_strength_ck_ALIGN 0 6592#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_half_strength_ck_BITS 1 6593#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8 6594#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0 6595 6596/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */ 6597#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080 6598#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_half_strength_ALIGN 0 6599#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_half_strength_BITS 1 6600#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_half_strength_SHIFT 7 6601#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0 6602 6603/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */ 6604#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rdqs_en_MASK 0x00000040 6605#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rdqs_en_ALIGN 0 6606#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rdqs_en_BITS 1 6607#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rdqs_en_SHIFT 6 6608#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0 6609 6610/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */ 6611#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020 6612#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_gddr_symmetry_ALIGN 0 6613#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_gddr_symmetry_BITS 1 6614#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5 6615#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0 6616 6617/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */ 6618#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018 6619#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_vddo_volts_ALIGN 0 6620#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_vddo_volts_BITS 2 6621#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3 6622#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0 6623 6624/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */ 6625#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rt60b_MASK 0x00000004 6626#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rt60b_ALIGN 0 6627#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rt60b_BITS 1 6628#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rt60b_SHIFT 2 6629#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rt60b_DEFAULT 0 6630 6631/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */ 6632#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rt120b_g_MASK 0x00000002 6633#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rt120b_g_ALIGN 0 6634#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rt120b_g_BITS 1 6635#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1 6636#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1 6637 6638/* DDR40_CORE_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */ 6639#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_g_ddr_MASK 0x00000001 6640#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_g_ddr_ALIGN 0 6641#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_g_ddr_BITS 1 6642#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_g_ddr_SHIFT 0 6643#define DDR40_CORE_PHY_WORD_LANE_0_DRIVE_PAD_CTL_g_ddr_DEFAULT 0 6644 6645/*************************************************************************** 6646 *CLOCK_PAD_DISABLE - Clock pad disable register 6647 ***************************************************************************/ 6648/* DDR40_CORE_PHY_WORD_LANE_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */ 6649#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8 6650#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_reserved0_ALIGN 0 6651#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_reserved0_BITS 29 6652#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3 6653 6654/* DDR40_CORE_PHY_WORD_LANE_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */ 6655#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004 6656#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_dm_pad_dis_ALIGN 0 6657#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_dm_pad_dis_BITS 1 6658#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2 6659#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0 6660 6661/* DDR40_CORE_PHY_WORD_LANE_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */ 6662#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002 6663#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_clk1_pad_dis_ALIGN 0 6664#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_clk1_pad_dis_BITS 1 6665#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1 6666#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0 6667 6668/* DDR40_CORE_PHY_WORD_LANE_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */ 6669#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001 6670#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_clk0_pad_dis_ALIGN 0 6671#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_clk0_pad_dis_BITS 1 6672#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0 6673#define DDR40_CORE_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0 6674 6675/*************************************************************************** 6676 *WR_PREAMBLE_MODE - Write cycle preamble control register 6677 ***************************************************************************/ 6678/* DDR40_CORE_PHY_WORD_LANE_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */ 6679#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc 6680#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_reserved0_ALIGN 0 6681#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_reserved0_BITS 30 6682#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2 6683 6684/* DDR40_CORE_PHY_WORD_LANE_0 :: WR_PREAMBLE_MODE :: long [01:01] */ 6685#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_long_MASK 0x00000002 6686#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_long_ALIGN 0 6687#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_long_BITS 1 6688#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_long_SHIFT 1 6689#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_long_DEFAULT 0 6690 6691/* DDR40_CORE_PHY_WORD_LANE_0 :: WR_PREAMBLE_MODE :: mode [00:00] */ 6692#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_mode_MASK 0x00000001 6693#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_mode_ALIGN 0 6694#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_mode_BITS 1 6695#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_mode_SHIFT 0 6696#define DDR40_CORE_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_mode_DEFAULT 0 6697 6698/*************************************************************************** 6699 *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register 6700 ***************************************************************************/ 6701/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */ 6702#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000 6703#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_busy_ALIGN 0 6704#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_busy_BITS 1 6705#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31 6706#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0 6707 6708/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */ 6709#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000 6710#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved0_ALIGN 0 6711#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved0_BITS 13 6712#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18 6713 6714/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */ 6715#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000 6716#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_force_ALIGN 0 6717#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_force_BITS 1 6718#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17 6719#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0 6720 6721/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */ 6722#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000 6723#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_en_ALIGN 0 6724#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_en_BITS 1 6725#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16 6726#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0 6727 6728/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */ 6729#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00 6730#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved1_ALIGN 0 6731#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved1_BITS 7 6732#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9 6733 6734/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */ 6735#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100 6736#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_byte_sel_ALIGN 0 6737#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_byte_sel_BITS 1 6738#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8 6739#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0 6740 6741/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */ 6742#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0 6743#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved2_ALIGN 0 6744#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved2_BITS 2 6745#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6 6746 6747/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */ 6748#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f 6749#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_step_ALIGN 0 6750#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_step_BITS 6 6751#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0 6752#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0 6753 6754/*************************************************************************** 6755 *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register 6756 ***************************************************************************/ 6757/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */ 6758#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_busy_MASK 0x80000000 6759#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_busy_ALIGN 0 6760#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_busy_BITS 1 6761#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31 6762#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0 6763 6764/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */ 6765#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000 6766#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved0_ALIGN 0 6767#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved0_BITS 13 6768#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18 6769 6770/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */ 6771#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000 6772#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_force_ALIGN 0 6773#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_force_BITS 1 6774#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17 6775#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0 6776 6777/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */ 6778#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000 6779#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_en_ALIGN 0 6780#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_en_BITS 1 6781#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16 6782#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0 6783 6784/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */ 6785#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00 6786#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved1_ALIGN 0 6787#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved1_BITS 7 6788#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9 6789 6790/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */ 6791#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100 6792#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_byte_sel_ALIGN 0 6793#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_byte_sel_BITS 1 6794#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8 6795#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0 6796 6797/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */ 6798#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0 6799#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved2_ALIGN 0 6800#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved2_BITS 2 6801#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6 6802 6803/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */ 6804#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f 6805#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_step_ALIGN 0 6806#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_step_BITS 6 6807#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0 6808#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0 6809 6810/*************************************************************************** 6811 *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register 6812 ***************************************************************************/ 6813/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */ 6814#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000 6815#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_busy_ALIGN 0 6816#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_busy_BITS 1 6817#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31 6818#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0 6819 6820/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */ 6821#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000 6822#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved0_ALIGN 0 6823#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved0_BITS 13 6824#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18 6825 6826/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */ 6827#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000 6828#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_force_ALIGN 0 6829#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_force_BITS 1 6830#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17 6831#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0 6832 6833/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */ 6834#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000 6835#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_en_ALIGN 0 6836#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_en_BITS 1 6837#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16 6838#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0 6839 6840/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */ 6841#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00 6842#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved1_ALIGN 0 6843#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved1_BITS 7 6844#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9 6845 6846/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */ 6847#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100 6848#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_byte_sel_ALIGN 0 6849#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_byte_sel_BITS 1 6850#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8 6851#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0 6852 6853/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */ 6854#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0 6855#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved2_ALIGN 0 6856#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved2_BITS 2 6857#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6 6858 6859/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */ 6860#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f 6861#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_step_ALIGN 0 6862#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_step_BITS 6 6863#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0 6864#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0 6865 6866/*************************************************************************** 6867 *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register 6868 ***************************************************************************/ 6869/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */ 6870#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000 6871#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_busy_ALIGN 0 6872#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_busy_BITS 1 6873#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31 6874#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0 6875 6876/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */ 6877#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000 6878#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved0_ALIGN 0 6879#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved0_BITS 13 6880#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18 6881 6882/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */ 6883#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000 6884#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_force_ALIGN 0 6885#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_force_BITS 1 6886#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17 6887#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0 6888 6889/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */ 6890#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000 6891#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_en_ALIGN 0 6892#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_en_BITS 1 6893#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16 6894#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0 6895 6896/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */ 6897#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00 6898#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved1_ALIGN 0 6899#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved1_BITS 7 6900#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9 6901 6902/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */ 6903#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100 6904#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_byte_sel_ALIGN 0 6905#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_byte_sel_BITS 1 6906#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8 6907#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0 6908 6909/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */ 6910#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0 6911#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved2_ALIGN 0 6912#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved2_BITS 2 6913#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6 6914 6915/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */ 6916#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f 6917#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_step_ALIGN 0 6918#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_step_BITS 6 6919#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0 6920#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0 6921 6922/*************************************************************************** 6923 *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register 6924 ***************************************************************************/ 6925/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */ 6926#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000 6927#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_busy_ALIGN 0 6928#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_busy_BITS 1 6929#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31 6930#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0 6931 6932/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */ 6933#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000 6934#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_ALIGN 0 6935#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_BITS 13 6936#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18 6937 6938/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */ 6939#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000 6940#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_ALIGN 0 6941#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_BITS 1 6942#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17 6943#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0 6944 6945/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */ 6946#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000 6947#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_ALIGN 0 6948#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_BITS 1 6949#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16 6950#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0 6951 6952/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */ 6953#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00 6954#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_ALIGN 0 6955#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_BITS 7 6956#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9 6957 6958/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */ 6959#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100 6960#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_ALIGN 0 6961#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_BITS 1 6962#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8 6963#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0 6964 6965/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */ 6966#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0 6967#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_ALIGN 0 6968#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_BITS 2 6969#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6 6970 6971/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */ 6972#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f 6973#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_ALIGN 0 6974#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_BITS 6 6975#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0 6976#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0 6977 6978/*************************************************************************** 6979 *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register 6980 ***************************************************************************/ 6981/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */ 6982#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000 6983#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_busy_ALIGN 0 6984#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_busy_BITS 1 6985#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31 6986#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0 6987 6988/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */ 6989#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000 6990#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_ALIGN 0 6991#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_BITS 13 6992#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18 6993 6994/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */ 6995#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000 6996#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_ALIGN 0 6997#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_BITS 1 6998#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17 6999#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0 7000 7001/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */ 7002#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000 7003#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_ALIGN 0 7004#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_BITS 1 7005#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16 7006#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0 7007 7008/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */ 7009#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00 7010#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_ALIGN 0 7011#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_BITS 7 7012#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9 7013 7014/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */ 7015#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100 7016#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_ALIGN 0 7017#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_BITS 1 7018#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8 7019#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0 7020 7021/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */ 7022#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0 7023#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_ALIGN 0 7024#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_BITS 2 7025#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6 7026 7027/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */ 7028#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f 7029#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_ALIGN 0 7030#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_BITS 6 7031#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0 7032#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0 7033 7034/*************************************************************************** 7035 *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register 7036 ***************************************************************************/ 7037/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */ 7038#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000 7039#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_busy_ALIGN 0 7040#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_busy_BITS 1 7041#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31 7042#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0 7043 7044/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */ 7045#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000 7046#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_ALIGN 0 7047#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_BITS 13 7048#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18 7049 7050/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */ 7051#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000 7052#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_ALIGN 0 7053#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_BITS 1 7054#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17 7055#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0 7056 7057/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */ 7058#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000 7059#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_ALIGN 0 7060#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_BITS 1 7061#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16 7062#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0 7063 7064/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */ 7065#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00 7066#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_ALIGN 0 7067#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_BITS 7 7068#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9 7069 7070/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */ 7071#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100 7072#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_ALIGN 0 7073#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_BITS 1 7074#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8 7075#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0 7076 7077/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */ 7078#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0 7079#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_ALIGN 0 7080#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_BITS 2 7081#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6 7082 7083/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */ 7084#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f 7085#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_ALIGN 0 7086#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_BITS 6 7087#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0 7088#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0 7089 7090/*************************************************************************** 7091 *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register 7092 ***************************************************************************/ 7093/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */ 7094#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000 7095#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_busy_ALIGN 0 7096#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_busy_BITS 1 7097#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31 7098#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0 7099 7100/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */ 7101#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000 7102#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_ALIGN 0 7103#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_BITS 13 7104#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18 7105 7106/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */ 7107#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000 7108#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_ALIGN 0 7109#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_BITS 1 7110#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17 7111#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0 7112 7113/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */ 7114#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000 7115#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_ALIGN 0 7116#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_BITS 1 7117#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16 7118#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0 7119 7120/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */ 7121#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00 7122#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_ALIGN 0 7123#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_BITS 7 7124#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9 7125 7126/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */ 7127#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100 7128#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_ALIGN 0 7129#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_BITS 1 7130#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8 7131#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0 7132 7133/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */ 7134#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0 7135#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_ALIGN 0 7136#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_BITS 2 7137#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6 7138 7139/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */ 7140#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f 7141#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_ALIGN 0 7142#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_BITS 6 7143#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0 7144#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0 7145 7146/*************************************************************************** 7147 *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register 7148 ***************************************************************************/ 7149/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */ 7150#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000 7151#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_busy_ALIGN 0 7152#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_busy_BITS 1 7153#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31 7154#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0 7155 7156/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */ 7157#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000 7158#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_ALIGN 0 7159#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_BITS 13 7160#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18 7161 7162/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */ 7163#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000 7164#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_ALIGN 0 7165#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_BITS 1 7166#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17 7167#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0 7168 7169/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */ 7170#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000 7171#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_ALIGN 0 7172#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_BITS 1 7173#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16 7174#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0 7175 7176/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */ 7177#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00 7178#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_ALIGN 0 7179#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_BITS 7 7180#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9 7181 7182/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */ 7183#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100 7184#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_ALIGN 0 7185#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_BITS 1 7186#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8 7187#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0 7188 7189/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */ 7190#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0 7191#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_ALIGN 0 7192#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_BITS 2 7193#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6 7194 7195/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */ 7196#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f 7197#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_ALIGN 0 7198#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_BITS 6 7199#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0 7200#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0 7201 7202/*************************************************************************** 7203 *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register 7204 ***************************************************************************/ 7205/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */ 7206#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000 7207#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_busy_ALIGN 0 7208#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_busy_BITS 1 7209#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31 7210#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0 7211 7212/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */ 7213#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000 7214#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_ALIGN 0 7215#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_BITS 13 7216#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18 7217 7218/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */ 7219#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000 7220#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_ALIGN 0 7221#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_BITS 1 7222#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17 7223#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0 7224 7225/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */ 7226#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000 7227#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_ALIGN 0 7228#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_BITS 1 7229#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16 7230#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0 7231 7232/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */ 7233#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00 7234#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_ALIGN 0 7235#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_BITS 7 7236#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9 7237 7238/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */ 7239#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100 7240#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_ALIGN 0 7241#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_BITS 1 7242#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8 7243#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0 7244 7245/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */ 7246#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0 7247#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_ALIGN 0 7248#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_BITS 2 7249#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6 7250 7251/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */ 7252#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f 7253#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_ALIGN 0 7254#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_BITS 6 7255#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0 7256#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0 7257 7258/*************************************************************************** 7259 *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register 7260 ***************************************************************************/ 7261/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */ 7262#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000 7263#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_busy_ALIGN 0 7264#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_busy_BITS 1 7265#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31 7266#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0 7267 7268/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */ 7269#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000 7270#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_ALIGN 0 7271#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_BITS 13 7272#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18 7273 7274/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */ 7275#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000 7276#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_ALIGN 0 7277#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_BITS 1 7278#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17 7279#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0 7280 7281/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */ 7282#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000 7283#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_ALIGN 0 7284#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_BITS 1 7285#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16 7286#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0 7287 7288/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */ 7289#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00 7290#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_ALIGN 0 7291#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_BITS 7 7292#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9 7293 7294/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */ 7295#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100 7296#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_ALIGN 0 7297#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_BITS 1 7298#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8 7299#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0 7300 7301/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */ 7302#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0 7303#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_ALIGN 0 7304#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_BITS 2 7305#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6 7306 7307/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */ 7308#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f 7309#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_ALIGN 0 7310#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_BITS 6 7311#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0 7312#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0 7313 7314/*************************************************************************** 7315 *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register 7316 ***************************************************************************/ 7317/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */ 7318#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000 7319#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_busy_ALIGN 0 7320#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_busy_BITS 1 7321#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31 7322#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0 7323 7324/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */ 7325#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000 7326#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_ALIGN 0 7327#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_BITS 13 7328#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18 7329 7330/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */ 7331#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000 7332#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_ALIGN 0 7333#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_BITS 1 7334#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17 7335#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0 7336 7337/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */ 7338#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000 7339#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_ALIGN 0 7340#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_BITS 1 7341#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16 7342#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0 7343 7344/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */ 7345#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00 7346#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_ALIGN 0 7347#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_BITS 7 7348#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9 7349 7350/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */ 7351#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100 7352#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_ALIGN 0 7353#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_BITS 1 7354#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8 7355#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0 7356 7357/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */ 7358#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0 7359#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_ALIGN 0 7360#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_BITS 2 7361#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6 7362 7363/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */ 7364#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f 7365#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_ALIGN 0 7366#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_BITS 6 7367#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0 7368#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0 7369 7370/*************************************************************************** 7371 *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register 7372 ***************************************************************************/ 7373/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */ 7374#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000 7375#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_busy_ALIGN 0 7376#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_busy_BITS 1 7377#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31 7378#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0 7379 7380/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */ 7381#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000 7382#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved0_ALIGN 0 7383#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved0_BITS 13 7384#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18 7385 7386/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */ 7387#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000 7388#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_force_ALIGN 0 7389#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_force_BITS 1 7390#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17 7391#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0 7392 7393/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */ 7394#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000 7395#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_en_ALIGN 0 7396#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_en_BITS 1 7397#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16 7398#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0 7399 7400/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */ 7401#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00 7402#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved1_ALIGN 0 7403#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved1_BITS 7 7404#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9 7405 7406/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */ 7407#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100 7408#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_byte_sel_ALIGN 0 7409#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_byte_sel_BITS 1 7410#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8 7411#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0 7412 7413/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */ 7414#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0 7415#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved2_ALIGN 0 7416#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved2_BITS 2 7417#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6 7418 7419/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */ 7420#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f 7421#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_step_ALIGN 0 7422#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_step_BITS 6 7423#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0 7424#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0 7425 7426/*************************************************************************** 7427 *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register 7428 ***************************************************************************/ 7429/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */ 7430#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000 7431#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_ALIGN 0 7432#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_BITS 1 7433#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31 7434#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0 7435 7436/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */ 7437#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000 7438#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_ALIGN 0 7439#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_BITS 13 7440#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18 7441 7442/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */ 7443#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000 7444#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_ALIGN 0 7445#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_BITS 1 7446#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17 7447#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0 7448 7449/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */ 7450#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000 7451#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_ALIGN 0 7452#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_BITS 1 7453#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16 7454#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0 7455 7456/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */ 7457#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00 7458#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_ALIGN 0 7459#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_BITS 7 7460#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9 7461 7462/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */ 7463#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100 7464#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_ALIGN 0 7465#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_BITS 1 7466#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8 7467#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0 7468 7469/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */ 7470#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0 7471#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_ALIGN 0 7472#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_BITS 2 7473#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6 7474 7475/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */ 7476#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f 7477#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_ALIGN 0 7478#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_BITS 6 7479#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0 7480#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0 7481 7482/*************************************************************************** 7483 *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register 7484 ***************************************************************************/ 7485/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */ 7486#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000 7487#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_ALIGN 0 7488#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_BITS 1 7489#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31 7490#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0 7491 7492/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */ 7493#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000 7494#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_ALIGN 0 7495#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_BITS 13 7496#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18 7497 7498/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */ 7499#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000 7500#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_ALIGN 0 7501#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_BITS 1 7502#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17 7503#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0 7504 7505/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */ 7506#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000 7507#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_ALIGN 0 7508#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_BITS 1 7509#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16 7510#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0 7511 7512/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */ 7513#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00 7514#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_ALIGN 0 7515#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_BITS 7 7516#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9 7517 7518/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */ 7519#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100 7520#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_ALIGN 0 7521#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_BITS 1 7522#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8 7523#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0 7524 7525/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */ 7526#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0 7527#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_ALIGN 0 7528#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_BITS 2 7529#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6 7530 7531/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */ 7532#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f 7533#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_ALIGN 0 7534#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_BITS 6 7535#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0 7536#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0 7537 7538/*************************************************************************** 7539 *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register 7540 ***************************************************************************/ 7541/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */ 7542#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000 7543#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_ALIGN 0 7544#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_BITS 1 7545#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31 7546#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0 7547 7548/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */ 7549#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000 7550#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_ALIGN 0 7551#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_BITS 13 7552#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18 7553 7554/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */ 7555#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000 7556#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_ALIGN 0 7557#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_BITS 1 7558#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17 7559#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0 7560 7561/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */ 7562#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000 7563#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_ALIGN 0 7564#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_BITS 1 7565#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16 7566#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0 7567 7568/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */ 7569#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00 7570#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_ALIGN 0 7571#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_BITS 7 7572#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9 7573 7574/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */ 7575#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100 7576#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_ALIGN 0 7577#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_BITS 1 7578#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8 7579#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0 7580 7581/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */ 7582#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0 7583#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_ALIGN 0 7584#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_BITS 2 7585#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6 7586 7587/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */ 7588#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f 7589#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_ALIGN 0 7590#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_BITS 6 7591#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0 7592#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0 7593 7594/*************************************************************************** 7595 *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register 7596 ***************************************************************************/ 7597/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */ 7598#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000 7599#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_ALIGN 0 7600#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_BITS 1 7601#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31 7602#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0 7603 7604/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */ 7605#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000 7606#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_ALIGN 0 7607#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_BITS 13 7608#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18 7609 7610/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */ 7611#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000 7612#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_ALIGN 0 7613#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_BITS 1 7614#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17 7615#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0 7616 7617/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */ 7618#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000 7619#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_ALIGN 0 7620#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_BITS 1 7621#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16 7622#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0 7623 7624/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */ 7625#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00 7626#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_ALIGN 0 7627#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_BITS 7 7628#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9 7629 7630/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */ 7631#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100 7632#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_ALIGN 0 7633#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_BITS 1 7634#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8 7635#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0 7636 7637/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */ 7638#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0 7639#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_ALIGN 0 7640#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_BITS 2 7641#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6 7642 7643/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */ 7644#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f 7645#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_ALIGN 0 7646#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_BITS 6 7647#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0 7648#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0 7649 7650/*************************************************************************** 7651 *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register 7652 ***************************************************************************/ 7653/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */ 7654#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000 7655#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_ALIGN 0 7656#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_BITS 1 7657#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31 7658#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0 7659 7660/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */ 7661#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000 7662#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_ALIGN 0 7663#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_BITS 13 7664#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18 7665 7666/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */ 7667#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000 7668#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_ALIGN 0 7669#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_BITS 1 7670#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17 7671#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0 7672 7673/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */ 7674#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000 7675#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_ALIGN 0 7676#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_BITS 1 7677#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16 7678#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0 7679 7680/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */ 7681#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00 7682#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_ALIGN 0 7683#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_BITS 7 7684#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9 7685 7686/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */ 7687#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100 7688#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_ALIGN 0 7689#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_BITS 1 7690#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8 7691#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0 7692 7693/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */ 7694#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0 7695#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_ALIGN 0 7696#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_BITS 2 7697#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6 7698 7699/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */ 7700#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f 7701#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_ALIGN 0 7702#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_BITS 6 7703#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0 7704#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0 7705 7706/*************************************************************************** 7707 *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register 7708 ***************************************************************************/ 7709/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */ 7710#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000 7711#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_ALIGN 0 7712#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_BITS 1 7713#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31 7714#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0 7715 7716/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */ 7717#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000 7718#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_ALIGN 0 7719#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_BITS 13 7720#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18 7721 7722/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */ 7723#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000 7724#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_ALIGN 0 7725#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_BITS 1 7726#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17 7727#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0 7728 7729/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */ 7730#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000 7731#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_ALIGN 0 7732#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_BITS 1 7733#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16 7734#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0 7735 7736/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */ 7737#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00 7738#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_ALIGN 0 7739#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_BITS 7 7740#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9 7741 7742/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */ 7743#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100 7744#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_ALIGN 0 7745#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_BITS 1 7746#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8 7747#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0 7748 7749/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */ 7750#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0 7751#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_ALIGN 0 7752#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_BITS 2 7753#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6 7754 7755/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */ 7756#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f 7757#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_ALIGN 0 7758#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_BITS 6 7759#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0 7760#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0 7761 7762/*************************************************************************** 7763 *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register 7764 ***************************************************************************/ 7765/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */ 7766#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000 7767#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_ALIGN 0 7768#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_BITS 1 7769#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31 7770#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0 7771 7772/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */ 7773#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000 7774#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_ALIGN 0 7775#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_BITS 13 7776#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18 7777 7778/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */ 7779#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000 7780#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_ALIGN 0 7781#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_BITS 1 7782#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17 7783#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0 7784 7785/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */ 7786#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000 7787#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_ALIGN 0 7788#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_BITS 1 7789#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16 7790#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0 7791 7792/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */ 7793#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00 7794#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_ALIGN 0 7795#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_BITS 7 7796#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9 7797 7798/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */ 7799#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100 7800#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_ALIGN 0 7801#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_BITS 1 7802#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8 7803#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0 7804 7805/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */ 7806#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0 7807#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_ALIGN 0 7808#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_BITS 2 7809#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6 7810 7811/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */ 7812#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f 7813#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_ALIGN 0 7814#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_BITS 6 7815#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0 7816#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0 7817 7818/*************************************************************************** 7819 *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register 7820 ***************************************************************************/ 7821/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */ 7822#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000 7823#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_ALIGN 0 7824#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_BITS 1 7825#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31 7826#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0 7827 7828/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */ 7829#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000 7830#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_ALIGN 0 7831#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_BITS 13 7832#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18 7833 7834/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */ 7835#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000 7836#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_ALIGN 0 7837#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_BITS 1 7838#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17 7839#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0 7840 7841/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */ 7842#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000 7843#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_ALIGN 0 7844#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_BITS 1 7845#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16 7846#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0 7847 7848/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */ 7849#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00 7850#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_ALIGN 0 7851#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_BITS 7 7852#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9 7853 7854/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */ 7855#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100 7856#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_ALIGN 0 7857#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_BITS 1 7858#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8 7859#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0 7860 7861/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */ 7862#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0 7863#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_ALIGN 0 7864#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_BITS 2 7865#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6 7866 7867/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */ 7868#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f 7869#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_ALIGN 0 7870#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_BITS 6 7871#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0 7872#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0 7873 7874/*************************************************************************** 7875 *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register 7876 ***************************************************************************/ 7877/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */ 7878#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000 7879#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_ALIGN 0 7880#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_BITS 1 7881#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31 7882#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0 7883 7884/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */ 7885#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000 7886#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_ALIGN 0 7887#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_BITS 13 7888#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18 7889 7890/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */ 7891#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000 7892#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_ALIGN 0 7893#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_BITS 1 7894#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17 7895#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0 7896 7897/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */ 7898#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000 7899#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_ALIGN 0 7900#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_BITS 1 7901#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16 7902#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0 7903 7904/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */ 7905#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00 7906#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_ALIGN 0 7907#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_BITS 7 7908#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9 7909 7910/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */ 7911#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100 7912#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_ALIGN 0 7913#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_BITS 1 7914#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8 7915#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0 7916 7917/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */ 7918#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0 7919#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_ALIGN 0 7920#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_BITS 2 7921#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6 7922 7923/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */ 7924#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f 7925#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_ALIGN 0 7926#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_BITS 6 7927#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0 7928#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0 7929 7930/*************************************************************************** 7931 *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register 7932 ***************************************************************************/ 7933/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */ 7934#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000 7935#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_ALIGN 0 7936#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_BITS 1 7937#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31 7938#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0 7939 7940/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */ 7941#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000 7942#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_ALIGN 0 7943#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_BITS 13 7944#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18 7945 7946/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */ 7947#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000 7948#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_ALIGN 0 7949#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_BITS 1 7950#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17 7951#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0 7952 7953/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */ 7954#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000 7955#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_ALIGN 0 7956#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_BITS 1 7957#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16 7958#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0 7959 7960/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */ 7961#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00 7962#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_ALIGN 0 7963#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_BITS 7 7964#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9 7965 7966/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */ 7967#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100 7968#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_ALIGN 0 7969#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_BITS 1 7970#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8 7971#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0 7972 7973/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */ 7974#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0 7975#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_ALIGN 0 7976#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_BITS 2 7977#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6 7978 7979/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */ 7980#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f 7981#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_ALIGN 0 7982#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_BITS 6 7983#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0 7984#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0 7985 7986/*************************************************************************** 7987 *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register 7988 ***************************************************************************/ 7989/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */ 7990#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000 7991#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_ALIGN 0 7992#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_BITS 1 7993#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31 7994#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0 7995 7996/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */ 7997#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000 7998#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_ALIGN 0 7999#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_BITS 13 8000#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18 8001 8002/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */ 8003#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000 8004#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_ALIGN 0 8005#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_BITS 1 8006#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17 8007#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0 8008 8009/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */ 8010#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000 8011#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_ALIGN 0 8012#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_BITS 1 8013#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16 8014#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0 8015 8016/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */ 8017#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00 8018#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_ALIGN 0 8019#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_BITS 7 8020#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9 8021 8022/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */ 8023#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100 8024#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_ALIGN 0 8025#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_BITS 1 8026#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8 8027#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0 8028 8029/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */ 8030#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0 8031#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_ALIGN 0 8032#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_BITS 2 8033#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6 8034 8035/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */ 8036#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f 8037#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_ALIGN 0 8038#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_BITS 6 8039#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0 8040#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0 8041 8042/*************************************************************************** 8043 *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register 8044 ***************************************************************************/ 8045/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */ 8046#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000 8047#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_ALIGN 0 8048#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_BITS 1 8049#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31 8050#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0 8051 8052/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */ 8053#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000 8054#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_ALIGN 0 8055#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_BITS 13 8056#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18 8057 8058/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */ 8059#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000 8060#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_ALIGN 0 8061#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_BITS 1 8062#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17 8063#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0 8064 8065/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */ 8066#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000 8067#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_ALIGN 0 8068#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_BITS 1 8069#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16 8070#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0 8071 8072/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */ 8073#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00 8074#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_ALIGN 0 8075#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_BITS 7 8076#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9 8077 8078/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */ 8079#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100 8080#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_ALIGN 0 8081#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_BITS 1 8082#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8 8083#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0 8084 8085/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */ 8086#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0 8087#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_ALIGN 0 8088#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_BITS 2 8089#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6 8090 8091/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */ 8092#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f 8093#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_ALIGN 0 8094#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_BITS 6 8095#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0 8096#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0 8097 8098/*************************************************************************** 8099 *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register 8100 ***************************************************************************/ 8101/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */ 8102#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000 8103#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_ALIGN 0 8104#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_BITS 1 8105#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31 8106#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0 8107 8108/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */ 8109#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000 8110#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_ALIGN 0 8111#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_BITS 13 8112#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18 8113 8114/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */ 8115#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000 8116#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_ALIGN 0 8117#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_BITS 1 8118#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17 8119#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0 8120 8121/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */ 8122#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000 8123#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_ALIGN 0 8124#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_BITS 1 8125#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16 8126#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0 8127 8128/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */ 8129#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00 8130#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_ALIGN 0 8131#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_BITS 7 8132#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9 8133 8134/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */ 8135#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100 8136#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_ALIGN 0 8137#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_BITS 1 8138#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8 8139#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0 8140 8141/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */ 8142#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0 8143#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_ALIGN 0 8144#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_BITS 2 8145#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6 8146 8147/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */ 8148#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f 8149#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_ALIGN 0 8150#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_BITS 6 8151#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0 8152#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0 8153 8154/*************************************************************************** 8155 *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register 8156 ***************************************************************************/ 8157/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */ 8158#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000 8159#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_ALIGN 0 8160#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_BITS 1 8161#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31 8162#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0 8163 8164/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */ 8165#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000 8166#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_ALIGN 0 8167#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_BITS 13 8168#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18 8169 8170/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */ 8171#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000 8172#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_ALIGN 0 8173#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_BITS 1 8174#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17 8175#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0 8176 8177/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */ 8178#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000 8179#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_ALIGN 0 8180#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_BITS 1 8181#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16 8182#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0 8183 8184/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */ 8185#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00 8186#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_ALIGN 0 8187#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_BITS 7 8188#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9 8189 8190/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */ 8191#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100 8192#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_ALIGN 0 8193#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_BITS 1 8194#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8 8195#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0 8196 8197/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */ 8198#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0 8199#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_ALIGN 0 8200#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_BITS 2 8201#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6 8202 8203/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */ 8204#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f 8205#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_ALIGN 0 8206#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_BITS 6 8207#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0 8208#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0 8209 8210/*************************************************************************** 8211 *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register 8212 ***************************************************************************/ 8213/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */ 8214#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000 8215#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_ALIGN 0 8216#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_BITS 1 8217#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31 8218#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0 8219 8220/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */ 8221#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000 8222#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_ALIGN 0 8223#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_BITS 13 8224#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18 8225 8226/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */ 8227#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000 8228#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_ALIGN 0 8229#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_BITS 1 8230#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17 8231#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0 8232 8233/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */ 8234#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000 8235#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_ALIGN 0 8236#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_BITS 1 8237#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16 8238#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0 8239 8240/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */ 8241#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00 8242#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_ALIGN 0 8243#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_BITS 7 8244#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9 8245 8246/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */ 8247#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100 8248#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_ALIGN 0 8249#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_BITS 1 8250#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8 8251#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0 8252 8253/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */ 8254#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0 8255#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_ALIGN 0 8256#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_BITS 2 8257#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6 8258 8259/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */ 8260#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f 8261#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_ALIGN 0 8262#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_BITS 6 8263#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0 8264#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0 8265 8266/*************************************************************************** 8267 *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register 8268 ***************************************************************************/ 8269/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */ 8270#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000 8271#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_ALIGN 0 8272#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_BITS 1 8273#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31 8274#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0 8275 8276/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */ 8277#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000 8278#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_ALIGN 0 8279#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_BITS 13 8280#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18 8281 8282/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */ 8283#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000 8284#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_ALIGN 0 8285#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_BITS 1 8286#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17 8287#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0 8288 8289/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */ 8290#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000 8291#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_ALIGN 0 8292#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_BITS 1 8293#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16 8294#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0 8295 8296/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */ 8297#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00 8298#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_ALIGN 0 8299#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_BITS 7 8300#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9 8301 8302/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */ 8303#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100 8304#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_ALIGN 0 8305#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_BITS 1 8306#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8 8307#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0 8308 8309/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */ 8310#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0 8311#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_ALIGN 0 8312#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_BITS 2 8313#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6 8314 8315/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */ 8316#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f 8317#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_ALIGN 0 8318#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_BITS 6 8319#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0 8320#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0 8321 8322/*************************************************************************** 8323 *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register 8324 ***************************************************************************/ 8325/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */ 8326#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000 8327#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_ALIGN 0 8328#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_BITS 1 8329#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31 8330#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0 8331 8332/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */ 8333#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000 8334#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_ALIGN 0 8335#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_BITS 13 8336#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18 8337 8338/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */ 8339#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000 8340#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_ALIGN 0 8341#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_BITS 1 8342#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17 8343#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0 8344 8345/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */ 8346#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000 8347#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_ALIGN 0 8348#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_BITS 1 8349#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16 8350#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0 8351 8352/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */ 8353#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00 8354#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_ALIGN 0 8355#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_BITS 7 8356#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9 8357 8358/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */ 8359#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100 8360#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_ALIGN 0 8361#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_BITS 1 8362#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8 8363#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0 8364 8365/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */ 8366#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0 8367#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_ALIGN 0 8368#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_BITS 2 8369#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6 8370 8371/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */ 8372#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f 8373#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_ALIGN 0 8374#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_BITS 6 8375#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0 8376#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0 8377 8378/*************************************************************************** 8379 *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register 8380 ***************************************************************************/ 8381/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */ 8382#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_busy_MASK 0x80000000 8383#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_busy_ALIGN 0 8384#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_busy_BITS 1 8385#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31 8386#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0 8387 8388/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */ 8389#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000 8390#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved0_ALIGN 0 8391#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved0_BITS 13 8392#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18 8393 8394/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */ 8395#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000 8396#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_force_ALIGN 0 8397#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_force_BITS 1 8398#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17 8399#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0 8400 8401/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */ 8402#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000 8403#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_en_ALIGN 0 8404#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_en_BITS 1 8405#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16 8406#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0 8407 8408/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */ 8409#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00 8410#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved1_ALIGN 0 8411#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved1_BITS 7 8412#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9 8413 8414/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */ 8415#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100 8416#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_byte_sel_ALIGN 0 8417#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_byte_sel_BITS 1 8418#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8 8419#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0 8420 8421/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */ 8422#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0 8423#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved2_ALIGN 0 8424#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved2_BITS 2 8425#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6 8426 8427/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */ 8428#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f 8429#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_step_ALIGN 0 8430#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_step_BITS 6 8431#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0 8432#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0 8433 8434/*************************************************************************** 8435 *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register 8436 ***************************************************************************/ 8437/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */ 8438#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000 8439#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_busy_ALIGN 0 8440#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_busy_BITS 1 8441#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31 8442#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0 8443 8444/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */ 8445#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000 8446#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved0_ALIGN 0 8447#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved0_BITS 13 8448#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18 8449 8450/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */ 8451#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000 8452#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_force_ALIGN 0 8453#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_force_BITS 1 8454#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17 8455#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0 8456 8457/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */ 8458#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000 8459#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_en_ALIGN 0 8460#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_en_BITS 1 8461#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16 8462#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0 8463 8464/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */ 8465#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00 8466#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved1_ALIGN 0 8467#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved1_BITS 7 8468#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9 8469 8470/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */ 8471#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100 8472#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_byte_sel_ALIGN 0 8473#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_byte_sel_BITS 1 8474#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8 8475#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0 8476 8477/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */ 8478#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0 8479#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved2_ALIGN 0 8480#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved2_BITS 2 8481#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6 8482 8483/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */ 8484#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f 8485#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_step_ALIGN 0 8486#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_step_BITS 6 8487#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0 8488#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0 8489 8490/*************************************************************************** 8491 *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register 8492 ***************************************************************************/ 8493/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */ 8494#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000 8495#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_busy_ALIGN 0 8496#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_busy_BITS 1 8497#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31 8498#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0 8499 8500/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */ 8501#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000 8502#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved0_ALIGN 0 8503#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved0_BITS 13 8504#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18 8505 8506/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */ 8507#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000 8508#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_force_ALIGN 0 8509#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_force_BITS 1 8510#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17 8511#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0 8512 8513/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */ 8514#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000 8515#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_en_ALIGN 0 8516#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_en_BITS 1 8517#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16 8518#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0 8519 8520/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */ 8521#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00 8522#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved1_ALIGN 0 8523#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved1_BITS 7 8524#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9 8525 8526/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */ 8527#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100 8528#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_byte_sel_ALIGN 0 8529#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_byte_sel_BITS 1 8530#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8 8531#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0 8532 8533/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */ 8534#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0 8535#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved2_ALIGN 0 8536#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved2_BITS 2 8537#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6 8538 8539/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */ 8540#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f 8541#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_step_ALIGN 0 8542#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_step_BITS 6 8543#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0 8544#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0 8545 8546/*************************************************************************** 8547 *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register 8548 ***************************************************************************/ 8549/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */ 8550#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000 8551#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_busy_ALIGN 0 8552#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_busy_BITS 1 8553#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31 8554#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0 8555 8556/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */ 8557#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000 8558#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_ALIGN 0 8559#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_BITS 13 8560#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18 8561 8562/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */ 8563#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000 8564#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_ALIGN 0 8565#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_BITS 1 8566#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17 8567#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0 8568 8569/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */ 8570#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000 8571#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_ALIGN 0 8572#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_BITS 1 8573#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16 8574#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0 8575 8576/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */ 8577#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00 8578#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_ALIGN 0 8579#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_BITS 7 8580#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9 8581 8582/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */ 8583#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100 8584#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_ALIGN 0 8585#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_BITS 1 8586#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8 8587#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0 8588 8589/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */ 8590#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0 8591#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_ALIGN 0 8592#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_BITS 2 8593#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6 8594 8595/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */ 8596#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f 8597#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_ALIGN 0 8598#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_BITS 6 8599#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0 8600#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0 8601 8602/*************************************************************************** 8603 *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register 8604 ***************************************************************************/ 8605/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */ 8606#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000 8607#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_busy_ALIGN 0 8608#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_busy_BITS 1 8609#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31 8610#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0 8611 8612/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */ 8613#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000 8614#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_ALIGN 0 8615#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_BITS 13 8616#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18 8617 8618/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */ 8619#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000 8620#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_ALIGN 0 8621#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_BITS 1 8622#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17 8623#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0 8624 8625/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */ 8626#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000 8627#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_ALIGN 0 8628#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_BITS 1 8629#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16 8630#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0 8631 8632/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */ 8633#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00 8634#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_ALIGN 0 8635#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_BITS 7 8636#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9 8637 8638/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */ 8639#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100 8640#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_ALIGN 0 8641#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_BITS 1 8642#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8 8643#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0 8644 8645/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */ 8646#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0 8647#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_ALIGN 0 8648#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_BITS 2 8649#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6 8650 8651/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */ 8652#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f 8653#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_ALIGN 0 8654#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_BITS 6 8655#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0 8656#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0 8657 8658/*************************************************************************** 8659 *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register 8660 ***************************************************************************/ 8661/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */ 8662#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000 8663#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_busy_ALIGN 0 8664#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_busy_BITS 1 8665#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31 8666#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0 8667 8668/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */ 8669#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000 8670#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_ALIGN 0 8671#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_BITS 13 8672#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18 8673 8674/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */ 8675#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000 8676#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_ALIGN 0 8677#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_BITS 1 8678#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17 8679#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0 8680 8681/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */ 8682#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000 8683#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_ALIGN 0 8684#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_BITS 1 8685#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16 8686#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0 8687 8688/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */ 8689#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00 8690#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_ALIGN 0 8691#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_BITS 7 8692#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9 8693 8694/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */ 8695#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100 8696#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_ALIGN 0 8697#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_BITS 1 8698#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8 8699#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0 8700 8701/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */ 8702#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0 8703#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_ALIGN 0 8704#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_BITS 2 8705#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6 8706 8707/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */ 8708#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f 8709#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_ALIGN 0 8710#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_BITS 6 8711#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0 8712#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0 8713 8714/*************************************************************************** 8715 *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register 8716 ***************************************************************************/ 8717/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */ 8718#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000 8719#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_busy_ALIGN 0 8720#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_busy_BITS 1 8721#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31 8722#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0 8723 8724/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */ 8725#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000 8726#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_ALIGN 0 8727#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_BITS 13 8728#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18 8729 8730/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */ 8731#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000 8732#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_ALIGN 0 8733#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_BITS 1 8734#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17 8735#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0 8736 8737/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */ 8738#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000 8739#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_ALIGN 0 8740#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_BITS 1 8741#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16 8742#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0 8743 8744/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */ 8745#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00 8746#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_ALIGN 0 8747#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_BITS 7 8748#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9 8749 8750/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */ 8751#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100 8752#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_ALIGN 0 8753#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_BITS 1 8754#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8 8755#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0 8756 8757/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */ 8758#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0 8759#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_ALIGN 0 8760#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_BITS 2 8761#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6 8762 8763/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */ 8764#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f 8765#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_ALIGN 0 8766#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_BITS 6 8767#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0 8768#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0 8769 8770/*************************************************************************** 8771 *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register 8772 ***************************************************************************/ 8773/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */ 8774#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000 8775#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_busy_ALIGN 0 8776#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_busy_BITS 1 8777#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31 8778#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0 8779 8780/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */ 8781#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000 8782#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_ALIGN 0 8783#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_BITS 13 8784#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18 8785 8786/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */ 8787#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000 8788#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_ALIGN 0 8789#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_BITS 1 8790#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17 8791#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0 8792 8793/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */ 8794#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000 8795#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_ALIGN 0 8796#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_BITS 1 8797#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16 8798#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0 8799 8800/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */ 8801#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00 8802#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_ALIGN 0 8803#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_BITS 7 8804#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9 8805 8806/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */ 8807#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100 8808#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_ALIGN 0 8809#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_BITS 1 8810#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8 8811#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0 8812 8813/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */ 8814#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0 8815#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_ALIGN 0 8816#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_BITS 2 8817#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6 8818 8819/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */ 8820#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f 8821#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_ALIGN 0 8822#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_BITS 6 8823#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0 8824#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0 8825 8826/*************************************************************************** 8827 *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register 8828 ***************************************************************************/ 8829/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */ 8830#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000 8831#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_busy_ALIGN 0 8832#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_busy_BITS 1 8833#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31 8834#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0 8835 8836/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */ 8837#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000 8838#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_ALIGN 0 8839#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_BITS 13 8840#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18 8841 8842/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */ 8843#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000 8844#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_ALIGN 0 8845#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_BITS 1 8846#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17 8847#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0 8848 8849/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */ 8850#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000 8851#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_ALIGN 0 8852#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_BITS 1 8853#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16 8854#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0 8855 8856/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */ 8857#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00 8858#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_ALIGN 0 8859#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_BITS 7 8860#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9 8861 8862/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */ 8863#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100 8864#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_ALIGN 0 8865#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_BITS 1 8866#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8 8867#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0 8868 8869/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */ 8870#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0 8871#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_ALIGN 0 8872#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_BITS 2 8873#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6 8874 8875/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */ 8876#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f 8877#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_ALIGN 0 8878#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_BITS 6 8879#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0 8880#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0 8881 8882/*************************************************************************** 8883 *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register 8884 ***************************************************************************/ 8885/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */ 8886#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000 8887#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_busy_ALIGN 0 8888#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_busy_BITS 1 8889#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31 8890#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0 8891 8892/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */ 8893#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000 8894#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_ALIGN 0 8895#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_BITS 13 8896#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18 8897 8898/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */ 8899#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000 8900#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_ALIGN 0 8901#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_BITS 1 8902#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17 8903#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0 8904 8905/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */ 8906#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000 8907#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_ALIGN 0 8908#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_BITS 1 8909#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16 8910#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0 8911 8912/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */ 8913#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00 8914#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_ALIGN 0 8915#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_BITS 7 8916#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9 8917 8918/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */ 8919#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100 8920#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_ALIGN 0 8921#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_BITS 1 8922#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8 8923#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0 8924 8925/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */ 8926#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0 8927#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_ALIGN 0 8928#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_BITS 2 8929#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6 8930 8931/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */ 8932#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f 8933#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_ALIGN 0 8934#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_BITS 6 8935#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0 8936#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0 8937 8938/*************************************************************************** 8939 *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register 8940 ***************************************************************************/ 8941/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */ 8942#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000 8943#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_busy_ALIGN 0 8944#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_busy_BITS 1 8945#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31 8946#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0 8947 8948/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */ 8949#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000 8950#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_ALIGN 0 8951#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_BITS 13 8952#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18 8953 8954/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */ 8955#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000 8956#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_ALIGN 0 8957#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_BITS 1 8958#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17 8959#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0 8960 8961/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */ 8962#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000 8963#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_ALIGN 0 8964#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_BITS 1 8965#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16 8966#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0 8967 8968/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */ 8969#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00 8970#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_ALIGN 0 8971#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_BITS 7 8972#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9 8973 8974/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */ 8975#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100 8976#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_ALIGN 0 8977#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_BITS 1 8978#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8 8979#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0 8980 8981/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */ 8982#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0 8983#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_ALIGN 0 8984#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_BITS 2 8985#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6 8986 8987/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */ 8988#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f 8989#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_ALIGN 0 8990#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_BITS 6 8991#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0 8992#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0 8993 8994/*************************************************************************** 8995 *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register 8996 ***************************************************************************/ 8997/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */ 8998#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000 8999#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_busy_ALIGN 0 9000#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_busy_BITS 1 9001#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31 9002#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0 9003 9004/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */ 9005#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000 9006#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved0_ALIGN 0 9007#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved0_BITS 13 9008#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18 9009 9010/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */ 9011#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000 9012#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_force_ALIGN 0 9013#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_force_BITS 1 9014#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17 9015#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0 9016 9017/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */ 9018#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000 9019#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_en_ALIGN 0 9020#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_en_BITS 1 9021#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16 9022#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0 9023 9024/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */ 9025#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00 9026#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved1_ALIGN 0 9027#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved1_BITS 7 9028#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9 9029 9030/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */ 9031#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100 9032#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_byte_sel_ALIGN 0 9033#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_byte_sel_BITS 1 9034#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8 9035#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0 9036 9037/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */ 9038#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0 9039#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved2_ALIGN 0 9040#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved2_BITS 2 9041#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6 9042 9043/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */ 9044#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f 9045#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_step_ALIGN 0 9046#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_step_BITS 6 9047#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0 9048#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0 9049 9050/*************************************************************************** 9051 *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register 9052 ***************************************************************************/ 9053/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */ 9054#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000 9055#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_ALIGN 0 9056#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_BITS 1 9057#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31 9058#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0 9059 9060/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */ 9061#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000 9062#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_ALIGN 0 9063#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_BITS 13 9064#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18 9065 9066/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */ 9067#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000 9068#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_ALIGN 0 9069#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_BITS 1 9070#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17 9071#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0 9072 9073/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */ 9074#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000 9075#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_ALIGN 0 9076#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_BITS 1 9077#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16 9078#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0 9079 9080/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */ 9081#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00 9082#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_ALIGN 0 9083#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_BITS 7 9084#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9 9085 9086/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */ 9087#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100 9088#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_ALIGN 0 9089#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_BITS 1 9090#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8 9091#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0 9092 9093/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */ 9094#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0 9095#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_ALIGN 0 9096#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_BITS 2 9097#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6 9098 9099/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */ 9100#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f 9101#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_ALIGN 0 9102#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_BITS 6 9103#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0 9104#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0 9105 9106/*************************************************************************** 9107 *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register 9108 ***************************************************************************/ 9109/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */ 9110#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000 9111#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_ALIGN 0 9112#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_BITS 1 9113#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31 9114#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0 9115 9116/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */ 9117#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000 9118#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_ALIGN 0 9119#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_BITS 13 9120#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18 9121 9122/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */ 9123#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000 9124#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_ALIGN 0 9125#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_BITS 1 9126#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17 9127#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0 9128 9129/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */ 9130#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000 9131#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_ALIGN 0 9132#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_BITS 1 9133#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16 9134#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0 9135 9136/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */ 9137#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00 9138#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_ALIGN 0 9139#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_BITS 7 9140#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9 9141 9142/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */ 9143#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100 9144#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_ALIGN 0 9145#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_BITS 1 9146#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8 9147#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0 9148 9149/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */ 9150#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0 9151#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_ALIGN 0 9152#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_BITS 2 9153#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6 9154 9155/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */ 9156#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f 9157#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_ALIGN 0 9158#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_BITS 6 9159#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0 9160#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0 9161 9162/*************************************************************************** 9163 *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register 9164 ***************************************************************************/ 9165/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */ 9166#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000 9167#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_ALIGN 0 9168#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_BITS 1 9169#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31 9170#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0 9171 9172/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */ 9173#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000 9174#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_ALIGN 0 9175#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_BITS 13 9176#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18 9177 9178/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */ 9179#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000 9180#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_ALIGN 0 9181#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_BITS 1 9182#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17 9183#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0 9184 9185/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */ 9186#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000 9187#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_ALIGN 0 9188#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_BITS 1 9189#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16 9190#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0 9191 9192/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */ 9193#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00 9194#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_ALIGN 0 9195#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_BITS 7 9196#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9 9197 9198/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */ 9199#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100 9200#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_ALIGN 0 9201#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_BITS 1 9202#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8 9203#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0 9204 9205/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */ 9206#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0 9207#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_ALIGN 0 9208#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_BITS 2 9209#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6 9210 9211/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */ 9212#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f 9213#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_ALIGN 0 9214#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_BITS 6 9215#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0 9216#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0 9217 9218/*************************************************************************** 9219 *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register 9220 ***************************************************************************/ 9221/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */ 9222#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000 9223#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_ALIGN 0 9224#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_BITS 1 9225#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31 9226#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0 9227 9228/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */ 9229#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000 9230#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_ALIGN 0 9231#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_BITS 13 9232#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18 9233 9234/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */ 9235#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000 9236#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_ALIGN 0 9237#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_BITS 1 9238#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17 9239#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0 9240 9241/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */ 9242#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000 9243#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_ALIGN 0 9244#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_BITS 1 9245#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16 9246#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0 9247 9248/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */ 9249#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00 9250#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_ALIGN 0 9251#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_BITS 7 9252#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9 9253 9254/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */ 9255#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100 9256#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_ALIGN 0 9257#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_BITS 1 9258#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8 9259#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0 9260 9261/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */ 9262#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0 9263#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_ALIGN 0 9264#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_BITS 2 9265#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6 9266 9267/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */ 9268#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f 9269#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_ALIGN 0 9270#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_BITS 6 9271#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0 9272#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0 9273 9274/*************************************************************************** 9275 *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register 9276 ***************************************************************************/ 9277/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */ 9278#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000 9279#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_ALIGN 0 9280#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_BITS 1 9281#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31 9282#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0 9283 9284/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */ 9285#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000 9286#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_ALIGN 0 9287#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_BITS 13 9288#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18 9289 9290/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */ 9291#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000 9292#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_ALIGN 0 9293#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_BITS 1 9294#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17 9295#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0 9296 9297/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */ 9298#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000 9299#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_ALIGN 0 9300#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_BITS 1 9301#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16 9302#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0 9303 9304/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */ 9305#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00 9306#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_ALIGN 0 9307#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_BITS 7 9308#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9 9309 9310/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */ 9311#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100 9312#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_ALIGN 0 9313#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_BITS 1 9314#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8 9315#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0 9316 9317/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */ 9318#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0 9319#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_ALIGN 0 9320#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_BITS 2 9321#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6 9322 9323/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */ 9324#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f 9325#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_ALIGN 0 9326#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_BITS 6 9327#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0 9328#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0 9329 9330/*************************************************************************** 9331 *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register 9332 ***************************************************************************/ 9333/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */ 9334#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000 9335#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_ALIGN 0 9336#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_BITS 1 9337#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31 9338#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0 9339 9340/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */ 9341#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000 9342#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_ALIGN 0 9343#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_BITS 13 9344#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18 9345 9346/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */ 9347#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000 9348#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_ALIGN 0 9349#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_BITS 1 9350#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17 9351#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0 9352 9353/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */ 9354#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000 9355#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_ALIGN 0 9356#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_BITS 1 9357#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16 9358#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0 9359 9360/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */ 9361#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00 9362#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_ALIGN 0 9363#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_BITS 7 9364#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9 9365 9366/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */ 9367#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100 9368#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_ALIGN 0 9369#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_BITS 1 9370#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8 9371#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0 9372 9373/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */ 9374#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0 9375#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_ALIGN 0 9376#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_BITS 2 9377#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6 9378 9379/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */ 9380#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f 9381#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_ALIGN 0 9382#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_BITS 6 9383#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0 9384#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0 9385 9386/*************************************************************************** 9387 *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register 9388 ***************************************************************************/ 9389/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */ 9390#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000 9391#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_ALIGN 0 9392#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_BITS 1 9393#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31 9394#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0 9395 9396/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */ 9397#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000 9398#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_ALIGN 0 9399#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_BITS 13 9400#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18 9401 9402/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */ 9403#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000 9404#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_ALIGN 0 9405#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_BITS 1 9406#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17 9407#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0 9408 9409/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */ 9410#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000 9411#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_ALIGN 0 9412#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_BITS 1 9413#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16 9414#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0 9415 9416/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */ 9417#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00 9418#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_ALIGN 0 9419#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_BITS 7 9420#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9 9421 9422/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */ 9423#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100 9424#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_ALIGN 0 9425#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_BITS 1 9426#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8 9427#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0 9428 9429/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */ 9430#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0 9431#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_ALIGN 0 9432#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_BITS 2 9433#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6 9434 9435/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */ 9436#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f 9437#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_ALIGN 0 9438#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_BITS 6 9439#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0 9440#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0 9441 9442/*************************************************************************** 9443 *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register 9444 ***************************************************************************/ 9445/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */ 9446#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000 9447#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_ALIGN 0 9448#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_BITS 1 9449#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31 9450#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0 9451 9452/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */ 9453#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000 9454#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_ALIGN 0 9455#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_BITS 13 9456#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18 9457 9458/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */ 9459#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000 9460#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_ALIGN 0 9461#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_BITS 1 9462#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17 9463#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0 9464 9465/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */ 9466#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000 9467#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_ALIGN 0 9468#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_BITS 1 9469#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16 9470#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0 9471 9472/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */ 9473#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00 9474#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_ALIGN 0 9475#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_BITS 7 9476#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9 9477 9478/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */ 9479#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100 9480#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_ALIGN 0 9481#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_BITS 1 9482#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8 9483#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0 9484 9485/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */ 9486#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0 9487#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_ALIGN 0 9488#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_BITS 2 9489#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6 9490 9491/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */ 9492#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f 9493#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_ALIGN 0 9494#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_BITS 6 9495#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0 9496#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0 9497 9498/*************************************************************************** 9499 *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register 9500 ***************************************************************************/ 9501/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */ 9502#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000 9503#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_ALIGN 0 9504#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_BITS 1 9505#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31 9506#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0 9507 9508/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */ 9509#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000 9510#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_ALIGN 0 9511#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_BITS 13 9512#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18 9513 9514/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */ 9515#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000 9516#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_ALIGN 0 9517#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_BITS 1 9518#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17 9519#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0 9520 9521/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */ 9522#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000 9523#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_ALIGN 0 9524#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_BITS 1 9525#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16 9526#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0 9527 9528/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */ 9529#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00 9530#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_ALIGN 0 9531#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_BITS 7 9532#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9 9533 9534/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */ 9535#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100 9536#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_ALIGN 0 9537#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_BITS 1 9538#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8 9539#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0 9540 9541/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */ 9542#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0 9543#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_ALIGN 0 9544#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_BITS 2 9545#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6 9546 9547/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */ 9548#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f 9549#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_ALIGN 0 9550#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_BITS 6 9551#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0 9552#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0 9553 9554/*************************************************************************** 9555 *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register 9556 ***************************************************************************/ 9557/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */ 9558#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000 9559#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_ALIGN 0 9560#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_BITS 1 9561#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31 9562#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0 9563 9564/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */ 9565#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000 9566#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_ALIGN 0 9567#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_BITS 13 9568#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18 9569 9570/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */ 9571#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000 9572#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_ALIGN 0 9573#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_BITS 1 9574#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17 9575#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0 9576 9577/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */ 9578#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000 9579#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_ALIGN 0 9580#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_BITS 1 9581#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16 9582#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0 9583 9584/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */ 9585#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00 9586#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_ALIGN 0 9587#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_BITS 7 9588#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9 9589 9590/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */ 9591#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100 9592#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_ALIGN 0 9593#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_BITS 1 9594#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8 9595#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0 9596 9597/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */ 9598#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0 9599#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_ALIGN 0 9600#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_BITS 2 9601#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6 9602 9603/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */ 9604#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f 9605#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_ALIGN 0 9606#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_BITS 6 9607#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0 9608#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0 9609 9610/*************************************************************************** 9611 *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register 9612 ***************************************************************************/ 9613/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */ 9614#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000 9615#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_ALIGN 0 9616#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_BITS 1 9617#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31 9618#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0 9619 9620/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */ 9621#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000 9622#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_ALIGN 0 9623#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_BITS 13 9624#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18 9625 9626/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */ 9627#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000 9628#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_ALIGN 0 9629#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_BITS 1 9630#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17 9631#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0 9632 9633/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */ 9634#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000 9635#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_ALIGN 0 9636#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_BITS 1 9637#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16 9638#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0 9639 9640/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */ 9641#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00 9642#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_ALIGN 0 9643#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_BITS 7 9644#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9 9645 9646/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */ 9647#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100 9648#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_ALIGN 0 9649#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_BITS 1 9650#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8 9651#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0 9652 9653/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */ 9654#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0 9655#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_ALIGN 0 9656#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_BITS 2 9657#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6 9658 9659/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */ 9660#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f 9661#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_ALIGN 0 9662#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_BITS 6 9663#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0 9664#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0 9665 9666/*************************************************************************** 9667 *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register 9668 ***************************************************************************/ 9669/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */ 9670#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000 9671#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_ALIGN 0 9672#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_BITS 1 9673#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31 9674#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0 9675 9676/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */ 9677#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000 9678#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_ALIGN 0 9679#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_BITS 13 9680#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18 9681 9682/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */ 9683#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000 9684#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_ALIGN 0 9685#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_BITS 1 9686#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17 9687#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0 9688 9689/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */ 9690#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000 9691#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_ALIGN 0 9692#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_BITS 1 9693#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16 9694#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0 9695 9696/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */ 9697#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00 9698#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_ALIGN 0 9699#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_BITS 7 9700#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9 9701 9702/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */ 9703#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100 9704#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_ALIGN 0 9705#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_BITS 1 9706#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8 9707#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0 9708 9709/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */ 9710#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0 9711#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_ALIGN 0 9712#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_BITS 2 9713#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6 9714 9715/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */ 9716#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f 9717#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_ALIGN 0 9718#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_BITS 6 9719#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0 9720#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0 9721 9722/*************************************************************************** 9723 *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register 9724 ***************************************************************************/ 9725/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */ 9726#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000 9727#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_ALIGN 0 9728#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_BITS 1 9729#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31 9730#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0 9731 9732/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */ 9733#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000 9734#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_ALIGN 0 9735#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_BITS 13 9736#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18 9737 9738/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */ 9739#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000 9740#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_ALIGN 0 9741#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_BITS 1 9742#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17 9743#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0 9744 9745/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */ 9746#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000 9747#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_ALIGN 0 9748#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_BITS 1 9749#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16 9750#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0 9751 9752/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */ 9753#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00 9754#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_ALIGN 0 9755#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_BITS 7 9756#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9 9757 9758/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */ 9759#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100 9760#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_ALIGN 0 9761#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_BITS 1 9762#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8 9763#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0 9764 9765/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */ 9766#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0 9767#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_ALIGN 0 9768#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_BITS 2 9769#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6 9770 9771/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */ 9772#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f 9773#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_ALIGN 0 9774#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_BITS 6 9775#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0 9776#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0 9777 9778/*************************************************************************** 9779 *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register 9780 ***************************************************************************/ 9781/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */ 9782#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000 9783#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_ALIGN 0 9784#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_BITS 1 9785#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31 9786#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0 9787 9788/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */ 9789#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000 9790#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_ALIGN 0 9791#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_BITS 13 9792#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18 9793 9794/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */ 9795#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000 9796#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_ALIGN 0 9797#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_BITS 1 9798#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17 9799#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0 9800 9801/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */ 9802#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000 9803#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_ALIGN 0 9804#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_BITS 1 9805#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16 9806#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0 9807 9808/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */ 9809#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00 9810#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_ALIGN 0 9811#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_BITS 7 9812#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9 9813 9814/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */ 9815#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100 9816#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_ALIGN 0 9817#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_BITS 1 9818#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8 9819#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0 9820 9821/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */ 9822#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0 9823#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_ALIGN 0 9824#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_BITS 2 9825#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6 9826 9827/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */ 9828#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f 9829#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_ALIGN 0 9830#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_BITS 6 9831#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0 9832#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0 9833 9834/*************************************************************************** 9835 *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register 9836 ***************************************************************************/ 9837/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */ 9838#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000 9839#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_ALIGN 0 9840#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_BITS 1 9841#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31 9842#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0 9843 9844/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */ 9845#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000 9846#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_ALIGN 0 9847#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_BITS 13 9848#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18 9849 9850/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */ 9851#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000 9852#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_ALIGN 0 9853#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_BITS 1 9854#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17 9855#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0 9856 9857/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */ 9858#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000 9859#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_ALIGN 0 9860#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_BITS 1 9861#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16 9862#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0 9863 9864/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */ 9865#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00 9866#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_ALIGN 0 9867#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_BITS 7 9868#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9 9869 9870/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */ 9871#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100 9872#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_ALIGN 0 9873#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_BITS 1 9874#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8 9875#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0 9876 9877/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */ 9878#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0 9879#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_ALIGN 0 9880#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_BITS 2 9881#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6 9882 9883/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */ 9884#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f 9885#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_ALIGN 0 9886#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_BITS 6 9887#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0 9888#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0 9889 9890/*************************************************************************** 9891 *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register 9892 ***************************************************************************/ 9893/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */ 9894#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000 9895#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_ALIGN 0 9896#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_BITS 1 9897#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31 9898#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0 9899 9900/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */ 9901#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000 9902#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_ALIGN 0 9903#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_BITS 13 9904#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18 9905 9906/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */ 9907#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000 9908#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_ALIGN 0 9909#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_BITS 1 9910#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17 9911#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0 9912 9913/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */ 9914#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000 9915#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_ALIGN 0 9916#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_BITS 1 9917#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16 9918#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0 9919 9920/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */ 9921#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00 9922#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_ALIGN 0 9923#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_BITS 7 9924#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9 9925 9926/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */ 9927#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100 9928#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_ALIGN 0 9929#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_BITS 1 9930#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8 9931#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0 9932 9933/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */ 9934#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0 9935#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_ALIGN 0 9936#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_BITS 2 9937#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6 9938 9939/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */ 9940#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f 9941#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_ALIGN 0 9942#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_BITS 6 9943#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0 9944#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0 9945 9946/*************************************************************************** 9947 *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register 9948 ***************************************************************************/ 9949/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */ 9950#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000 9951#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_ALIGN 0 9952#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_BITS 1 9953#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31 9954#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0 9955 9956/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */ 9957#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000 9958#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_ALIGN 0 9959#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_BITS 13 9960#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18 9961 9962/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */ 9963#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000 9964#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_ALIGN 0 9965#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_BITS 1 9966#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17 9967#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0 9968 9969/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */ 9970#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000 9971#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_ALIGN 0 9972#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_BITS 1 9973#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16 9974#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0 9975 9976/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */ 9977#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00 9978#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_ALIGN 0 9979#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_BITS 7 9980#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9 9981 9982/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */ 9983#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100 9984#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_ALIGN 0 9985#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_BITS 1 9986#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8 9987#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0 9988 9989/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */ 9990#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0 9991#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_ALIGN 0 9992#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_BITS 2 9993#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6 9994 9995/* DDR40_CORE_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */ 9996#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f 9997#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_ALIGN 0 9998#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_BITS 6 9999#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0 10000#define DDR40_CORE_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0 10001 10002/*************************************************************************** 10003 *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register 10004 ***************************************************************************/ 10005/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */ 10006#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000 10007#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_ALIGN 0 10008#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_BITS 15 10009#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17 10010 10011/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */ 10012#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000 10013#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_ALIGN 0 10014#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_BITS 1 10015#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16 10016#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0 10017 10018/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */ 10019#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00 10020#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_ALIGN 0 10021#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_BITS 7 10022#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9 10023 10024/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */ 10025#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100 10026#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_ALIGN 0 10027#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_BITS 1 10028#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8 10029#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0 10030 10031/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */ 10032#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0 10033#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_ALIGN 0 10034#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_BITS 2 10035#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6 10036 10037/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */ 10038#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f 10039#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_ALIGN 0 10040#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_BITS 6 10041#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0 10042#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0 10043 10044/*************************************************************************** 10045 *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register 10046 ***************************************************************************/ 10047/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */ 10048#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000 10049#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_ALIGN 0 10050#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_BITS 15 10051#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17 10052 10053/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */ 10054#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000 10055#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_ALIGN 0 10056#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_BITS 1 10057#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16 10058#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0 10059 10060/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */ 10061#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00 10062#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_ALIGN 0 10063#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_BITS 7 10064#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9 10065 10066/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */ 10067#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100 10068#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_ALIGN 0 10069#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_BITS 1 10070#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8 10071#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0 10072 10073/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */ 10074#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0 10075#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_ALIGN 0 10076#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_BITS 2 10077#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6 10078 10079/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */ 10080#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f 10081#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_ALIGN 0 10082#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_BITS 6 10083#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0 10084#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0 10085 10086/*************************************************************************** 10087 *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register 10088 ***************************************************************************/ 10089/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */ 10090#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000 10091#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_ALIGN 0 10092#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_BITS 7 10093#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25 10094 10095/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */ 10096#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000 10097#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_ALIGN 0 10098#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_BITS 1 10099#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24 10100#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0 10101 10102/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */ 10103#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000 10104#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_ALIGN 0 10105#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_BITS 8 10106#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16 10107#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0 10108 10109/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */ 10110#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00 10111#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_ALIGN 0 10112#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_BITS 7 10113#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9 10114 10115/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */ 10116#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100 10117#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_ALIGN 0 10118#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_BITS 1 10119#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8 10120#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0 10121 10122/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */ 10123#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0 10124#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_ALIGN 0 10125#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_BITS 2 10126#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6 10127 10128/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */ 10129#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f 10130#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_ALIGN 0 10131#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_BITS 6 10132#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0 10133#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0 10134 10135/*************************************************************************** 10136 *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register 10137 ***************************************************************************/ 10138/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */ 10139#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000 10140#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_ALIGN 0 10141#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_BITS 7 10142#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25 10143 10144/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */ 10145#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000 10146#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_ALIGN 0 10147#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_BITS 1 10148#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24 10149#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0 10150 10151/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */ 10152#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000 10153#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_ALIGN 0 10154#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_BITS 8 10155#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16 10156#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0 10157 10158/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */ 10159#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00 10160#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_ALIGN 0 10161#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_BITS 7 10162#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9 10163 10164/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */ 10165#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100 10166#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_ALIGN 0 10167#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_BITS 1 10168#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8 10169#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0 10170 10171/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */ 10172#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0 10173#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_ALIGN 0 10174#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_BITS 2 10175#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6 10176 10177/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */ 10178#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f 10179#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_ALIGN 0 10180#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_BITS 6 10181#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0 10182#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0 10183 10184/*************************************************************************** 10185 *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register 10186 ***************************************************************************/ 10187/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */ 10188#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000 10189#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved0_ALIGN 0 10190#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved0_BITS 15 10191#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17 10192 10193/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */ 10194#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000 10195#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_ALIGN 0 10196#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_BITS 1 10197#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16 10198#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0 10199 10200/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */ 10201#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00 10202#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved1_ALIGN 0 10203#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved1_BITS 7 10204#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9 10205 10206/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */ 10207#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100 10208#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_ALIGN 0 10209#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_BITS 1 10210#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8 10211#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0 10212 10213/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */ 10214#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0 10215#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved2_ALIGN 0 10216#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved2_BITS 2 10217#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6 10218 10219/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */ 10220#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f 10221#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_ALIGN 0 10222#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_BITS 6 10223#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0 10224#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0 10225 10226/*************************************************************************** 10227 *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register 10228 ***************************************************************************/ 10229/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */ 10230#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000 10231#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_ALIGN 0 10232#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_BITS 7 10233#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25 10234 10235/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */ 10236#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000 10237#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_ALIGN 0 10238#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_BITS 1 10239#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24 10240#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0 10241 10242/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */ 10243#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000 10244#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_ALIGN 0 10245#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_BITS 8 10246#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16 10247#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0 10248 10249/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */ 10250#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00 10251#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_ALIGN 0 10252#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_BITS 7 10253#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9 10254 10255/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */ 10256#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100 10257#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_ALIGN 0 10258#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_BITS 1 10259#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8 10260#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0 10261 10262/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */ 10263#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0 10264#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_ALIGN 0 10265#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_BITS 2 10266#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6 10267 10268/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */ 10269#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f 10270#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_ALIGN 0 10271#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_BITS 6 10272#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0 10273#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0 10274 10275/*************************************************************************** 10276 *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register 10277 ***************************************************************************/ 10278/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */ 10279#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000 10280#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_ALIGN 0 10281#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_BITS 15 10282#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17 10283 10284/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */ 10285#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000 10286#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_ALIGN 0 10287#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_BITS 1 10288#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16 10289#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0 10290 10291/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */ 10292#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00 10293#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_ALIGN 0 10294#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_BITS 7 10295#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9 10296 10297/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */ 10298#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100 10299#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_ALIGN 0 10300#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_BITS 1 10301#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8 10302#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0 10303 10304/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */ 10305#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0 10306#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_ALIGN 0 10307#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_BITS 2 10308#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6 10309 10310/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */ 10311#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f 10312#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_ALIGN 0 10313#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_BITS 6 10314#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0 10315#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0 10316 10317/*************************************************************************** 10318 *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register 10319 ***************************************************************************/ 10320/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */ 10321#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000 10322#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_ALIGN 0 10323#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_BITS 15 10324#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17 10325 10326/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */ 10327#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000 10328#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_ALIGN 0 10329#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_BITS 1 10330#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16 10331#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0 10332 10333/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */ 10334#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00 10335#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_ALIGN 0 10336#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_BITS 7 10337#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9 10338 10339/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */ 10340#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100 10341#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_ALIGN 0 10342#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_BITS 1 10343#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8 10344#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0 10345 10346/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */ 10347#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0 10348#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_ALIGN 0 10349#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_BITS 2 10350#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6 10351 10352/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */ 10353#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f 10354#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_ALIGN 0 10355#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_BITS 6 10356#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0 10357#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0 10358 10359/*************************************************************************** 10360 *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register 10361 ***************************************************************************/ 10362/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */ 10363#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000 10364#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_ALIGN 0 10365#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_BITS 7 10366#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25 10367 10368/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */ 10369#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000 10370#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_ALIGN 0 10371#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_BITS 1 10372#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24 10373#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0 10374 10375/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */ 10376#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000 10377#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_ALIGN 0 10378#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_BITS 8 10379#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16 10380#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0 10381 10382/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */ 10383#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00 10384#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_ALIGN 0 10385#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_BITS 7 10386#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9 10387 10388/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */ 10389#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100 10390#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_ALIGN 0 10391#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_BITS 1 10392#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8 10393#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0 10394 10395/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */ 10396#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0 10397#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_ALIGN 0 10398#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_BITS 2 10399#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6 10400 10401/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */ 10402#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f 10403#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_ALIGN 0 10404#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_BITS 6 10405#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0 10406#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0 10407 10408/*************************************************************************** 10409 *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register 10410 ***************************************************************************/ 10411/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */ 10412#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000 10413#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_ALIGN 0 10414#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_BITS 7 10415#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25 10416 10417/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */ 10418#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000 10419#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_ALIGN 0 10420#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_BITS 1 10421#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24 10422#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0 10423 10424/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */ 10425#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000 10426#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_ALIGN 0 10427#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_BITS 8 10428#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16 10429#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0 10430 10431/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */ 10432#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00 10433#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_ALIGN 0 10434#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_BITS 7 10435#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9 10436 10437/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */ 10438#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100 10439#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_ALIGN 0 10440#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_BITS 1 10441#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8 10442#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0 10443 10444/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */ 10445#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0 10446#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_ALIGN 0 10447#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_BITS 2 10448#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6 10449 10450/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */ 10451#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f 10452#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_ALIGN 0 10453#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_BITS 6 10454#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0 10455#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0 10456 10457/*************************************************************************** 10458 *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register 10459 ***************************************************************************/ 10460/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */ 10461#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000 10462#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved0_ALIGN 0 10463#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved0_BITS 15 10464#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17 10465 10466/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */ 10467#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000 10468#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_ALIGN 0 10469#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_BITS 1 10470#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16 10471#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0 10472 10473/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */ 10474#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00 10475#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved1_ALIGN 0 10476#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved1_BITS 7 10477#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9 10478 10479/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */ 10480#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100 10481#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_ALIGN 0 10482#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_BITS 1 10483#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8 10484#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0 10485 10486/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */ 10487#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0 10488#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved2_ALIGN 0 10489#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved2_BITS 2 10490#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6 10491 10492/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */ 10493#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f 10494#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_ALIGN 0 10495#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_BITS 6 10496#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0 10497#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0 10498 10499/*************************************************************************** 10500 *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register 10501 ***************************************************************************/ 10502/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */ 10503#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000 10504#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_ALIGN 0 10505#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_BITS 7 10506#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25 10507 10508/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */ 10509#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000 10510#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_ALIGN 0 10511#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_BITS 1 10512#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24 10513#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0 10514 10515/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */ 10516#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000 10517#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_ALIGN 0 10518#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_BITS 8 10519#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16 10520#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0 10521 10522/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */ 10523#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00 10524#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_ALIGN 0 10525#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_BITS 7 10526#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9 10527 10528/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */ 10529#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100 10530#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_ALIGN 0 10531#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_BITS 1 10532#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8 10533#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0 10534 10535/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */ 10536#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0 10537#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_ALIGN 0 10538#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_BITS 2 10539#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6 10540 10541/* DDR40_CORE_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */ 10542#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f 10543#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_ALIGN 0 10544#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_BITS 6 10545#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0 10546#define DDR40_CORE_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0 10547 10548/*************************************************************************** 10549 *READ_DATA_DLY - Word Lane read channel control register 10550 ***************************************************************************/ 10551/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_DATA_DLY :: reserved0 [31:03] */ 10552#define DDR40_CORE_PHY_WORD_LANE_1_READ_DATA_DLY_reserved0_MASK 0xfffffff8 10553#define DDR40_CORE_PHY_WORD_LANE_1_READ_DATA_DLY_reserved0_ALIGN 0 10554#define DDR40_CORE_PHY_WORD_LANE_1_READ_DATA_DLY_reserved0_BITS 29 10555#define DDR40_CORE_PHY_WORD_LANE_1_READ_DATA_DLY_reserved0_SHIFT 3 10556 10557/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_DATA_DLY :: rd_data_dly [02:00] */ 10558#define DDR40_CORE_PHY_WORD_LANE_1_READ_DATA_DLY_rd_data_dly_MASK 0x00000007 10559#define DDR40_CORE_PHY_WORD_LANE_1_READ_DATA_DLY_rd_data_dly_ALIGN 0 10560#define DDR40_CORE_PHY_WORD_LANE_1_READ_DATA_DLY_rd_data_dly_BITS 3 10561#define DDR40_CORE_PHY_WORD_LANE_1_READ_DATA_DLY_rd_data_dly_SHIFT 0 10562#define DDR40_CORE_PHY_WORD_LANE_1_READ_DATA_DLY_rd_data_dly_DEFAULT 1 10563 10564/*************************************************************************** 10565 *READ_CONTROL - Word Lane read channel control register 10566 ***************************************************************************/ 10567/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_CONTROL :: reserved0 [31:03] */ 10568#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_reserved0_MASK 0xfffffff8 10569#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_reserved0_ALIGN 0 10570#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_reserved0_BITS 29 10571#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_reserved0_SHIFT 3 10572 10573/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_CONTROL :: dq_odt_enable [02:02] */ 10574#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_enable_MASK 0x00000004 10575#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_enable_ALIGN 0 10576#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_enable_BITS 1 10577#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_enable_SHIFT 2 10578#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_enable_DEFAULT 1 10579 10580/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_CONTROL :: dq_odt_te_adj [01:01] */ 10581#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002 10582#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_te_adj_ALIGN 0 10583#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_te_adj_BITS 1 10584#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_te_adj_SHIFT 1 10585#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_te_adj_DEFAULT 1 10586 10587/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_CONTROL :: dq_odt_le_adj [00:00] */ 10588#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001 10589#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_le_adj_ALIGN 0 10590#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_le_adj_BITS 1 10591#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_le_adj_SHIFT 0 10592#define DDR40_CORE_PHY_WORD_LANE_1_READ_CONTROL_dq_odt_le_adj_DEFAULT 0 10593 10594/*************************************************************************** 10595 *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data 10596 ***************************************************************************/ 10597/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */ 10598#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000 10599#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_reserved0_ALIGN 0 10600#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_reserved0_BITS 16 10601#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16 10602 10603/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */ 10604#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00 10605#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_data_p_ALIGN 0 10606#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_data_p_BITS 8 10607#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8 10608 10609/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */ 10610#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff 10611#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_data_n_ALIGN 0 10612#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_data_n_BITS 8 10613#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0 10614 10615/*************************************************************************** 10616 *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data 10617 ***************************************************************************/ 10618/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */ 10619#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000 10620#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_reserved0_ALIGN 0 10621#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_reserved0_BITS 16 10622#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16 10623 10624/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */ 10625#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00 10626#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_data_p_ALIGN 0 10627#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_data_p_BITS 8 10628#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8 10629 10630/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */ 10631#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff 10632#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_data_n_ALIGN 0 10633#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_data_n_BITS 8 10634#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0 10635 10636/*************************************************************************** 10637 *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data 10638 ***************************************************************************/ 10639/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */ 10640#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000 10641#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_reserved0_ALIGN 0 10642#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_reserved0_BITS 16 10643#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16 10644 10645/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */ 10646#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00 10647#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_data_p_ALIGN 0 10648#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_data_p_BITS 8 10649#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8 10650 10651/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */ 10652#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff 10653#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_data_n_ALIGN 0 10654#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_data_n_BITS 8 10655#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0 10656 10657/*************************************************************************** 10658 *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data 10659 ***************************************************************************/ 10660/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */ 10661#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000 10662#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_reserved0_ALIGN 0 10663#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_reserved0_BITS 16 10664#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16 10665 10666/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */ 10667#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00 10668#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_data_p_ALIGN 0 10669#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_data_p_BITS 8 10670#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8 10671 10672/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */ 10673#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff 10674#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_data_n_ALIGN 0 10675#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_data_n_BITS 8 10676#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0 10677 10678/*************************************************************************** 10679 *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data 10680 ***************************************************************************/ 10681/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */ 10682#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000 10683#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_reserved0_ALIGN 0 10684#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_reserved0_BITS 16 10685#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16 10686 10687/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */ 10688#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00 10689#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_data_p_ALIGN 0 10690#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_data_p_BITS 8 10691#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8 10692 10693/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */ 10694#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff 10695#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_data_n_ALIGN 0 10696#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_data_n_BITS 8 10697#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0 10698 10699/*************************************************************************** 10700 *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data 10701 ***************************************************************************/ 10702/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */ 10703#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000 10704#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_reserved0_ALIGN 0 10705#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_reserved0_BITS 16 10706#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16 10707 10708/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */ 10709#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00 10710#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_data_p_ALIGN 0 10711#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_data_p_BITS 8 10712#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8 10713 10714/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */ 10715#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff 10716#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_data_n_ALIGN 0 10717#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_data_n_BITS 8 10718#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0 10719 10720/*************************************************************************** 10721 *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data 10722 ***************************************************************************/ 10723/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */ 10724#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000 10725#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_reserved0_ALIGN 0 10726#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_reserved0_BITS 16 10727#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16 10728 10729/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */ 10730#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00 10731#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_data_p_ALIGN 0 10732#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_data_p_BITS 8 10733#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8 10734 10735/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */ 10736#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff 10737#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_data_n_ALIGN 0 10738#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_data_n_BITS 8 10739#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0 10740 10741/*************************************************************************** 10742 *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data 10743 ***************************************************************************/ 10744/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */ 10745#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000 10746#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_reserved0_ALIGN 0 10747#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_reserved0_BITS 16 10748#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16 10749 10750/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */ 10751#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00 10752#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_data_p_ALIGN 0 10753#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_data_p_BITS 8 10754#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8 10755 10756/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */ 10757#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff 10758#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_data_n_ALIGN 0 10759#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_data_n_BITS 8 10760#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0 10761 10762/*************************************************************************** 10763 *READ_FIFO_STATUS - Read fifo status register 10764 ***************************************************************************/ 10765/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_STATUS :: reserved0 [31:08] */ 10766#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_reserved0_MASK 0xffffff00 10767#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_reserved0_ALIGN 0 10768#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_reserved0_BITS 24 10769#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_reserved0_SHIFT 8 10770 10771/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_STATUS :: status1 [07:04] */ 10772#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_status1_MASK 0x000000f0 10773#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_status1_ALIGN 0 10774#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_status1_BITS 4 10775#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_status1_SHIFT 4 10776#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_status1_DEFAULT 0 10777 10778/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_STATUS :: status0 [03:00] */ 10779#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_status0_MASK 0x0000000f 10780#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_status0_ALIGN 0 10781#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_status0_BITS 4 10782#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_status0_SHIFT 0 10783#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_STATUS_status0_DEFAULT 0 10784 10785/*************************************************************************** 10786 *READ_FIFO_CLEAR - Read fifo status clear register 10787 ***************************************************************************/ 10788/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 10789#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe 10790#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_CLEAR_reserved0_ALIGN 0 10791#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_CLEAR_reserved0_BITS 31 10792#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_CLEAR_reserved0_SHIFT 1 10793 10794/* DDR40_CORE_PHY_WORD_LANE_1 :: READ_FIFO_CLEAR :: clear [00:00] */ 10795#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_CLEAR_clear_MASK 0x00000001 10796#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_CLEAR_clear_ALIGN 0 10797#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_CLEAR_clear_BITS 1 10798#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_CLEAR_clear_SHIFT 0 10799#define DDR40_CORE_PHY_WORD_LANE_1_READ_FIFO_CLEAR_clear_DEFAULT 0 10800 10801/*************************************************************************** 10802 *IDLE_PAD_CONTROL - Idle mode SSTL pad control register 10803 ***************************************************************************/ 10804/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: idle [31:31] */ 10805#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_idle_MASK 0x80000000 10806#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_idle_ALIGN 0 10807#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_idle_BITS 1 10808#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_idle_SHIFT 31 10809#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_idle_DEFAULT 0 10810 10811/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */ 10812#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000 10813#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_reserved0_ALIGN 0 10814#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_reserved0_BITS 7 10815#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_reserved0_SHIFT 24 10816 10817/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */ 10818#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000 10819#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_ALIGN 0 10820#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_BITS 2 10821#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22 10822#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 1 10823 10824/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */ 10825#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000 10826#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_auto_dq_iddq_mode_ALIGN 0 10827#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_auto_dq_iddq_mode_BITS 2 10828#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20 10829#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 1 10830 10831/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */ 10832#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000 10833#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_rxenb_ALIGN 0 10834#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_rxenb_BITS 1 10835#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19 10836#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 1 10837 10838/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */ 10839#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000 10840#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_iddq_ALIGN 0 10841#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_iddq_BITS 1 10842#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18 10843#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 1 10844 10845/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */ 10846#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_reb_MASK 0x00020000 10847#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_reb_ALIGN 0 10848#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_reb_BITS 1 10849#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_reb_SHIFT 17 10850#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_reb_DEFAULT 1 10851 10852/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */ 10853#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_oeb_MASK 0x00010000 10854#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_oeb_ALIGN 0 10855#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_oeb_BITS 1 10856#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16 10857#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 1 10858 10859/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */ 10860#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000 10861#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_rxenb_ALIGN 0 10862#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_rxenb_BITS 1 10863#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15 10864#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0 10865 10866/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */ 10867#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000 10868#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_ALIGN 0 10869#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_BITS 1 10870#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14 10871#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0 10872 10873/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */ 10874#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000 10875#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_reb_ALIGN 0 10876#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_reb_BITS 1 10877#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13 10878#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 1 10879 10880/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */ 10881#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000 10882#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_oeb_ALIGN 0 10883#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_oeb_BITS 1 10884#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12 10885#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0 10886 10887/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */ 10888#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800 10889#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_rxenb_ALIGN 0 10890#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_rxenb_BITS 1 10891#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11 10892#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 1 10893 10894/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */ 10895#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400 10896#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_ALIGN 0 10897#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_BITS 1 10898#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10 10899#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 1 10900 10901/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */ 10902#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200 10903#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_reb_ALIGN 0 10904#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_reb_BITS 1 10905#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9 10906#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 1 10907 10908/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */ 10909#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100 10910#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_oeb_ALIGN 0 10911#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_oeb_BITS 1 10912#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8 10913#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 1 10914 10915/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */ 10916#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080 10917#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_rxenb_ALIGN 0 10918#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_rxenb_BITS 1 10919#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7 10920#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 1 10921 10922/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */ 10923#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040 10924#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_iddq_ALIGN 0 10925#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_iddq_BITS 1 10926#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6 10927#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0 10928 10929/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */ 10930#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020 10931#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_reb_ALIGN 0 10932#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_reb_BITS 1 10933#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5 10934#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 1 10935 10936/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */ 10937#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010 10938#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_oeb_ALIGN 0 10939#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_oeb_BITS 1 10940#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4 10941#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0 10942 10943/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */ 10944#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008 10945#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_rxenb_ALIGN 0 10946#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_rxenb_BITS 1 10947#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3 10948#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 1 10949 10950/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */ 10951#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004 10952#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_iddq_ALIGN 0 10953#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_iddq_BITS 1 10954#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2 10955#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0 10956 10957/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */ 10958#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002 10959#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_reb_ALIGN 0 10960#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_reb_BITS 1 10961#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1 10962#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 1 10963 10964/* DDR40_CORE_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */ 10965#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001 10966#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_oeb_ALIGN 0 10967#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_oeb_BITS 1 10968#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0 10969#define DDR40_CORE_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0 10970 10971/*************************************************************************** 10972 *DRIVE_PAD_CTL - SSTL pad drive characteristics control register 10973 ***************************************************************************/ 10974/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: reserved0 [31:12] */ 10975#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_reserved0_MASK 0xfffff000 10976#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_reserved0_ALIGN 0 10977#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_reserved0_BITS 20 10978#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_reserved0_SHIFT 12 10979 10980/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */ 10981#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_no_dqs_rd_MASK 0x00000800 10982#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_no_dqs_rd_ALIGN 0 10983#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_no_dqs_rd_BITS 1 10984#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11 10985#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0 10986 10987/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */ 10988#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400 10989#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_dqs_always_on_ALIGN 0 10990#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_dqs_always_on_BITS 1 10991#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10 10992#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 1 10993 10994/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */ 10995#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200 10996#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_dqs_tx_dis_ALIGN 0 10997#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_dqs_tx_dis_BITS 1 10998#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9 10999#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0 11000 11001/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */ 11002#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100 11003#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_half_strength_ck_ALIGN 0 11004#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_half_strength_ck_BITS 1 11005#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8 11006#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0 11007 11008/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: half_strength [07:07] */ 11009#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_half_strength_MASK 0x00000080 11010#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_half_strength_ALIGN 0 11011#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_half_strength_BITS 1 11012#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_half_strength_SHIFT 7 11013#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_half_strength_DEFAULT 0 11014 11015/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */ 11016#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rdqs_en_MASK 0x00000040 11017#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rdqs_en_ALIGN 0 11018#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rdqs_en_BITS 1 11019#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rdqs_en_SHIFT 6 11020#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0 11021 11022/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */ 11023#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020 11024#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_gddr_symmetry_ALIGN 0 11025#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_gddr_symmetry_BITS 1 11026#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5 11027#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0 11028 11029/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */ 11030#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018 11031#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_vddo_volts_ALIGN 0 11032#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_vddo_volts_BITS 2 11033#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_vddo_volts_SHIFT 3 11034#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0 11035 11036/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: rt60b [02:02] */ 11037#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rt60b_MASK 0x00000004 11038#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rt60b_ALIGN 0 11039#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rt60b_BITS 1 11040#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rt60b_SHIFT 2 11041#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rt60b_DEFAULT 0 11042 11043/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */ 11044#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rt120b_g_MASK 0x00000002 11045#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rt120b_g_ALIGN 0 11046#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rt120b_g_BITS 1 11047#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rt120b_g_SHIFT 1 11048#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1 11049 11050/* DDR40_CORE_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: g_ddr [00:00] */ 11051#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_g_ddr_MASK 0x00000001 11052#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_g_ddr_ALIGN 0 11053#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_g_ddr_BITS 1 11054#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_g_ddr_SHIFT 0 11055#define DDR40_CORE_PHY_WORD_LANE_1_DRIVE_PAD_CTL_g_ddr_DEFAULT 0 11056 11057/*************************************************************************** 11058 *CLOCK_PAD_DISABLE - Clock pad disable register 11059 ***************************************************************************/ 11060/* DDR40_CORE_PHY_WORD_LANE_1 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */ 11061#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8 11062#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_reserved0_ALIGN 0 11063#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_reserved0_BITS 29 11064#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_reserved0_SHIFT 3 11065 11066/* DDR40_CORE_PHY_WORD_LANE_1 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */ 11067#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004 11068#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_dm_pad_dis_ALIGN 0 11069#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_dm_pad_dis_BITS 1 11070#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2 11071#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0 11072 11073/* DDR40_CORE_PHY_WORD_LANE_1 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */ 11074#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002 11075#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_clk1_pad_dis_ALIGN 0 11076#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_clk1_pad_dis_BITS 1 11077#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1 11078#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0 11079 11080/* DDR40_CORE_PHY_WORD_LANE_1 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */ 11081#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001 11082#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_clk0_pad_dis_ALIGN 0 11083#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_clk0_pad_dis_BITS 1 11084#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0 11085#define DDR40_CORE_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0 11086 11087/*************************************************************************** 11088 *WR_PREAMBLE_MODE - Write cycle preamble control register 11089 ***************************************************************************/ 11090/* DDR40_CORE_PHY_WORD_LANE_1 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */ 11091#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc 11092#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_reserved0_ALIGN 0 11093#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_reserved0_BITS 30 11094#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_reserved0_SHIFT 2 11095 11096/* DDR40_CORE_PHY_WORD_LANE_1 :: WR_PREAMBLE_MODE :: long [01:01] */ 11097#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_long_MASK 0x00000002 11098#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_long_ALIGN 0 11099#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_long_BITS 1 11100#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_long_SHIFT 1 11101#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_long_DEFAULT 0 11102 11103/* DDR40_CORE_PHY_WORD_LANE_1 :: WR_PREAMBLE_MODE :: mode [00:00] */ 11104#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_mode_MASK 0x00000001 11105#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_mode_ALIGN 0 11106#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_mode_BITS 1 11107#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_mode_SHIFT 0 11108#define DDR40_CORE_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_mode_DEFAULT 0 11109 11110#endif /* #ifndef DDR40_PHY_REGISTERS_H__ */ 11111 11112/* End of File */ 11113