1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Memory Controller constants File: sb1250_mc.h 5 * 6 * This module contains constants and macros useful for 7 * programming the memory controller. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * MA 02111-1307 USA 32 ********************************************************************* */ 33 34 35#ifndef _SB1250_MC_H 36#define _SB1250_MC_H 37 38#include "sb1250_defs.h" 39 40/* 41 * Memory Channel Config Register (table 6-14) 42 */ 43 44#define S_MC_RESERVED0 0 45#define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0) 46 47#define S_MC_CHANNEL_SEL 8 48#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL) 49#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL) 50#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL) 51 52#define S_MC_BANK0_MAP 16 53#define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP) 54#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP) 55#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP) 56 57#define K_MC_BANK0_MAP_DEFAULT 0x00 58#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) 59 60#define S_MC_BANK1_MAP 20 61#define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP) 62#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP) 63#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP) 64 65#define K_MC_BANK1_MAP_DEFAULT 0x08 66#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) 67 68#define S_MC_BANK2_MAP 24 69#define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP) 70#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP) 71#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP) 72 73#define K_MC_BANK2_MAP_DEFAULT 0x09 74#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) 75 76#define S_MC_BANK3_MAP 28 77#define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP) 78#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP) 79#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP) 80 81#define K_MC_BANK3_MAP_DEFAULT 0x0C 82#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) 83 84#define M_MC_RESERVED1 _SB_MAKEMASK(8,32) 85 86#define S_MC_QUEUE_SIZE 40 87#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE) 88#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE) 89#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE) 90#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) 91 92#define S_MC_AGE_LIMIT 44 93#define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT) 94#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT) 95#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT) 96#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) 97 98#define S_MC_WR_LIMIT 48 99#define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT) 100#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT) 101#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT) 102#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) 103 104#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) 105 106#define M_MC_RESERVED2 _SB_MAKEMASK(3,53) 107 108#define S_MC_CS_MODE 56 109#define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE) 110#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE) 111#define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE) 112 113#define K_MC_CS_MODE_MSB_CS 0 114#define K_MC_CS_MODE_INTLV_CS 15 115#define K_MC_CS_MODE_MIXED_CS_10 12 116#define K_MC_CS_MODE_MIXED_CS_30 6 117#define K_MC_CS_MODE_MIXED_CS_32 3 118 119#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS) 120#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS) 121#define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10) 122#define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30) 123#define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32) 124 125#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60) 126#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61) 127#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62) 128#define M_MC_DEBUG _SB_MAKEMASK1(63) 129 130#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \ 131 V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \ 132 V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \ 133 M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT 134 135 136/* 137 * Memory clock config register (Table 6-15) 138 * 139 * Note: this field has been updated to be consistent with the errata to 0.2 140 */ 141 142#define S_MC_CLK_RATIO 0 143#define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO) 144#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO) 145#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO) 146 147#define K_MC_CLK_RATIO_2X 4 148#define K_MC_CLK_RATIO_25X 5 149#define K_MC_CLK_RATIO_3X 6 150#define K_MC_CLK_RATIO_35X 7 151#define K_MC_CLK_RATIO_4X 8 152#define K_MC_CLK_RATIO_45X 9 153 154#define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X) 155#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X) 156#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X) 157#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X) 158#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X) 159#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X) 160#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X 161 162#define S_MC_REF_RATE 8 163#define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE) 164#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE) 165#define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE) 166 167#define K_MC_REF_RATE_100MHz 0x62 168#define K_MC_REF_RATE_133MHz 0x81 169#define K_MC_REF_RATE_200MHz 0xC4 170 171#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) 172#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) 173#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz) 174#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz 175 176#define S_MC_CLOCK_DRIVE 16 177#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE) 178#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE) 179#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE) 180#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) 181 182#define S_MC_DATA_DRIVE 20 183#define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE) 184#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE) 185#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE) 186#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) 187 188#define S_MC_ADDR_DRIVE 24 189#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE) 190#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE) 191#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE) 192#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) 193 194#if SIBYTE_HDR_FEATURE(112x, PASS1) 195#define M_MC_REF_DISABLE _SB_MAKEMASK1(30) 196#endif /* 112x PASS1 */ 197 198#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) 199 200#define S_MC_DQI_SKEW 32 201#define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW) 202#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW) 203#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW) 204#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) 205 206#define S_MC_DQO_SKEW 40 207#define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW) 208#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW) 209#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW) 210#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) 211 212#define S_MC_ADDR_SKEW 48 213#define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW) 214#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW) 215#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW) 216#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) 217 218#define S_MC_DLL_DEFAULT 56 219#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT) 220#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT) 221#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT) 222#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) 223 224#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ 225 V_MC_ADDR_SKEW_DEFAULT | \ 226 V_MC_DQO_SKEW_DEFAULT | \ 227 V_MC_DQI_SKEW_DEFAULT | \ 228 V_MC_ADDR_DRIVE_DEFAULT | \ 229 V_MC_DATA_DRIVE_DEFAULT | \ 230 V_MC_CLOCK_DRIVE_DEFAULT | \ 231 V_MC_REF_RATE_DEFAULT 232 233 234 235/* 236 * DRAM Command Register (Table 6-13) 237 */ 238 239#define S_MC_COMMAND 0 240#define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND) 241#define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND) 242#define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND) 243 244#define K_MC_COMMAND_EMRS 0 245#define K_MC_COMMAND_MRS 1 246#define K_MC_COMMAND_PRE 2 247#define K_MC_COMMAND_AR 3 248#define K_MC_COMMAND_SETRFSH 4 249#define K_MC_COMMAND_CLRRFSH 5 250#define K_MC_COMMAND_SETPWRDN 6 251#define K_MC_COMMAND_CLRPWRDN 7 252 253#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS) 254#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS) 255#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE) 256#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR) 257#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH) 258#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH) 259#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN) 260#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN) 261 262#define M_MC_CS0 _SB_MAKEMASK1(4) 263#define M_MC_CS1 _SB_MAKEMASK1(5) 264#define M_MC_CS2 _SB_MAKEMASK1(6) 265#define M_MC_CS3 _SB_MAKEMASK1(7) 266 267/* 268 * DRAM Mode Register (Table 6-14) 269 */ 270 271#define S_MC_EMODE 0 272#define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE) 273#define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE) 274#define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE) 275#define V_MC_EMODE_DEFAULT V_MC_EMODE(0) 276 277#define S_MC_MODE 16 278#define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE) 279#define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE) 280#define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE) 281#define V_MC_MODE_DEFAULT V_MC_MODE(0x22) 282 283#define S_MC_DRAM_TYPE 32 284#define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE) 285#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE) 286#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE) 287 288#define K_MC_DRAM_TYPE_JEDEC 0 289#define K_MC_DRAM_TYPE_FCRAM 1 290#define K_MC_DRAM_TYPE_SGRAM 2 291 292#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC) 293#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM) 294#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM) 295 296#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35) 297 298#if SIBYTE_HDR_FEATURE(112x, PASS1) 299#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) 300#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(38) 301#endif /* 112x PASS1 */ 302 303 304 305/* 306 * SDRAM Timing Register (Table 6-15) 307 */ 308 309#define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60) 310#define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61) 311#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) 312 313#define S_MC_tFIFO 56 314#define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO) 315#define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO) 316#define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO) 317#define K_MC_tFIFO_DEFAULT 1 318#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) 319 320#define S_MC_tRFC 52 321#define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC) 322#define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC) 323#define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC) 324#define K_MC_tRFC_DEFAULT 12 325#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) 326 327#define S_MC_tCwCr 40 328#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) 329#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) 330#define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr) 331#define K_MC_tCwCr_DEFAULT 4 332#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) 333 334#define S_MC_tRCr 28 335#define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr) 336#define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr) 337#define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr) 338#define K_MC_tRCr_DEFAULT 9 339#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) 340 341#define S_MC_tRCw 24 342#define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw) 343#define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw) 344#define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw) 345#define K_MC_tRCw_DEFAULT 10 346#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) 347 348#define S_MC_tRRD 20 349#define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD) 350#define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD) 351#define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD) 352#define K_MC_tRRD_DEFAULT 2 353#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) 354 355#define S_MC_tRP 16 356#define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP) 357#define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP) 358#define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP) 359#define K_MC_tRP_DEFAULT 4 360#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) 361 362#define S_MC_tCwD 8 363#define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD) 364#define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD) 365#define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD) 366#define K_MC_tCwD_DEFAULT 1 367#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) 368 369#define M_tCrDh _SB_MAKEMASK1(7) 370#define M_MC_tCrDh M_tCrDh 371 372#define S_MC_tCrD 4 373#define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD) 374#define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD) 375#define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD) 376#define K_MC_tCrD_DEFAULT 2 377#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) 378 379#define S_MC_tRCD 0 380#define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD) 381#define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD) 382#define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD) 383#define K_MC_tRCD_DEFAULT 3 384#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) 385 386#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \ 387 V_MC_tRFC(K_MC_tRFC_DEFAULT) | \ 388 V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \ 389 V_MC_tRCr(K_MC_tRCr_DEFAULT) | \ 390 V_MC_tRCw(K_MC_tRCw_DEFAULT) | \ 391 V_MC_tRRD(K_MC_tRRD_DEFAULT) | \ 392 V_MC_tRP(K_MC_tRP_DEFAULT) | \ 393 V_MC_tCwD(K_MC_tCwD_DEFAULT) | \ 394 V_MC_tCrD(K_MC_tCrD_DEFAULT) | \ 395 V_MC_tRCD(K_MC_tRCD_DEFAULT) | \ 396 M_MC_r2rIDLE_TWOCYCLES 397 398/* 399 * Errata says these are not the default 400 * M_MC_w2rIDLE_TWOCYCLES | \ 401 * M_MC_r2wIDLE_TWOCYCLES | \ 402 */ 403 404 405/* 406 * Chip Select Start Address Register (Table 6-17) 407 */ 408 409#define S_MC_CS0_START 0 410#define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START) 411#define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START) 412#define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START) 413 414#define S_MC_CS1_START 16 415#define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START) 416#define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START) 417#define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START) 418 419#define S_MC_CS2_START 32 420#define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START) 421#define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START) 422#define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START) 423 424#define S_MC_CS3_START 48 425#define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START) 426#define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START) 427#define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START) 428 429/* 430 * Chip Select End Address Register (Table 6-18) 431 */ 432 433#define S_MC_CS0_END 0 434#define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END) 435#define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END) 436#define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END) 437 438#define S_MC_CS1_END 16 439#define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END) 440#define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END) 441#define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END) 442 443#define S_MC_CS2_END 32 444#define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END) 445#define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END) 446#define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END) 447 448#define S_MC_CS3_END 48 449#define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END) 450#define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END) 451#define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END) 452 453/* 454 * Chip Select Interleave Register (Table 6-19) 455 */ 456 457#define S_MC_INTLV_RESERVED 0 458#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED) 459 460#define S_MC_INTERLEAVE 7 461#define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE) 462#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE) 463 464#define S_MC_INTLV_MBZ 25 465#define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ) 466 467/* 468 * Row Address Bits Register (Table 6-20) 469 */ 470 471#define S_MC_RAS_RESERVED 0 472#define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED) 473 474#define S_MC_RAS_SELECT 12 475#define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT) 476#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT) 477 478#define S_MC_RAS_MBZ 37 479#define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ) 480 481 482/* 483 * Column Address Bits Register (Table 6-21) 484 */ 485 486#define S_MC_CAS_RESERVED 0 487#define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED) 488 489#define S_MC_CAS_SELECT 5 490#define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT) 491#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT) 492 493#define S_MC_CAS_MBZ 23 494#define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ) 495 496 497/* 498 * Bank Address Address Bits Register (Table 6-22) 499 */ 500 501#define S_MC_BA_RESERVED 0 502#define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED) 503 504#define S_MC_BA_SELECT 5 505#define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT) 506#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT) 507 508#define S_MC_BA_MBZ 25 509#define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ) 510 511/* 512 * Chip Select Attribute Register (Table 6-23) 513 */ 514 515#define K_MC_CS_ATTR_CLOSED 0 516#define K_MC_CS_ATTR_CASCHECK 1 517#define K_MC_CS_ATTR_HINT 2 518#define K_MC_CS_ATTR_OPEN 3 519 520#define S_MC_CS0_PAGE 0 521#define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE) 522#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE) 523#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE) 524 525#define S_MC_CS1_PAGE 16 526#define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE) 527#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE) 528#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE) 529 530#define S_MC_CS2_PAGE 32 531#define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE) 532#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE) 533#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE) 534 535#define S_MC_CS3_PAGE 48 536#define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE) 537#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE) 538#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE) 539 540/* 541 * ECC Test ECC Register (Table 6-25) 542 */ 543 544#define S_MC_ECC_INVERT 0 545#define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT) 546 547 548#endif 549