1/* 2 * ng1hw.h: Tweaks the newport.h structures and definations to be compatible 3 * with IRIX. Quite ugly, but it works. 4 * 5 * Copyright (C) 1999 Ulf Carlsson (ulfc@thepuffingroup.com) 6 */ 7#ifndef _SGI_NG1HW_H 8#define _SGI_NG1HW_H 9 10#include <video/newport.h> 11 12#define rex3regs newport_rexregs 13#define configregs newport_cregs 14#define float_long npfreg_t 15 16typedef struct newport_rexregs Rex3regs; 17typedef struct newport_cregs Configregs; 18typedef union np_dcb DCB_reg; 19 20 21/* It looks like I can't do a simple tweak with this structure because the IRIX 22 * version is just *too* stupid. Ok, here's a new version of it.. 23 */ 24 25struct rex3chip { 26 struct newport_rexregs set; 27 unsigned long _unused0[0x16e]; 28 struct newport_rexregs go; 29 unsigned long _unused1[0x22e]; 30 struct { 31 struct newport_cregs set; 32 unsigned long _unused2[0x1ef]; 33 struct newport_cregs go; 34 } p1; 35}; 36 37typedef struct rex3chip rex3Chip; 38typedef struct rex3chip Rex3chip; 39 40/* Tweak the defines .. */ 41 42#define DM0_OPCODE NPORT_DMODE0_OPMASK 43#define DM0_NOP NPORT_DMODE0_NOP 44#define DM0_READ NPORT_DMODE0_RD 45#define DM0_DRAW NPORT_DMODE0_DRAW 46#define DM0_SCR2SCR NPORT_DMODE0_S2S 47 48#define DM0_ADRMODE_SHIFT 2 49#define DM0_ADRMODE NPORT_DMODE0_AMMASK 50#define DM0_SPAN NPORT_DMODE0_SPAN 51#define DM0_BLOCK NPORT_DMODE0_BLOCK 52#define DM0_ILINE NPORT_DMODE0_ILINE 53#define DM0_FLINE NPORT_DMODE0_FLINE 54#define DM0_ALINE NPORT_DMODE0_ALINE 55#define DM0_TLINE NPORT_DMODE0_TLINE 56#define DM0_BLINE NPORT_DMODE0_BLINE 57 58#define DM0_DOSETUP NPORT_DMODE0_DOSETUP 59#define DM0_COLORHOST NPORT_DMODE0_CHOST 60#define DM0_ALPHAHOST NPORT_DMODE0_AHOST 61#define DM0_STOPONX NPORT_DMODE0_STOPX 62#define DM0_STOPONY NPORT_DMODE0_STOPY 63#define DM0_STOPONXY (NPORT_DMODE0_STOPX | NPORT_DMODE0_STOPY) 64#define DM0_SKIPFIRST NPORT_DMODE0_SK1ST 65#define DM0_SKIPLAST NPORT_DMODE0_SKLST 66#define DM0_ENZPATTERN NPORT_DMODE0_ZPENAB 67#define DM0_ENLSPATTERN NPORT_DMODE0_LISPENAB 68#define DM0_LSADVLAST NPORT_DMODE0_LISLST 69#define DM0_LENGTH32 NPORT_DMODE0_L32 70#define DM0_ZOPAQUE NPORT_DMODE0_ZOPQ 71#define DM0_LSOPAQUE NPORT_DMODE0_LISOPQ 72#define DM0_SHADE NPORT_DMODE0_SHADE 73#define DM0_LRONLY NPORT_DMODE0_LRONLY 74#define DM0_XYOFFSET NPORT_DMODE0_XYOFF 75#define DM0_CICLAMP NPORT_DMODE0_CLAMP 76#define DM0_ENDPTFILTER NPORT_DMODE0_ENDPF 77#define DM0_YSTRIDE NPORT_DMODE0_YSTR 78 79#define DM1_PLANES_SHIFT 0 80/* The rest of the DM1 planes defines are in newport.h */ 81 82#define DM1_DRAWDEPTH_SHIFT 3 83#define DM1_DRAWDEPTH_MASK NPORT_DMODE1_DDMASK 84#define DM1_DRAWDEPTH NPORT_DMODE1_DD24 /* An alias? */ 85#define DM1_DRAWDEPTH4 NPORT_DMODE1_DD4 86#define DM1_DRAWDEPTH8 NPORT_DMODE1_DD8 87#define DM1_DRAWDEPTH12 NPORT_DMODE1_DD12 88#define DM1_DRAWDEPTH24 NPORT_DMODE1_DD24 89 90#define DM1_DBLSRC NPORT_DMODE1_DSRC 91#define DM1_YFLIP NPORT_DMODE1_YFLIP 92#define DM1_RWPACKED NPORT_DMODE1_RWPCKD 93 94#define DM1_HOSTDEPTH_SHIFT 8 95#define DM1_HOSTDEPTH_MASK NPORT_DMODE1_HDMASK 96#define DM1_HOSTDEPTH NPORT_DMODE1_HD32 /* An alias? */ 97#define DM1_HOSTDEPTH4 NPORT_DMODE1_HD4 98#define DM1_HOSTDEPTH8 NPORT_DMODE1_HD8 99#define DM1_HOSTDEPTH12 NPORT_DMODE1_HD12 100#define DM1_HOSTDEPTH32 NPORT_DMODE1_HD32 101 102#define DM1_RWDOUBLE NPORT_DMODE1_RWDBL 103#define DM1_SWAPENDIAN NPORT_DMODE1_ESWAP 104 105#define DM1_COLORCOMPARE_SHIFT 12 106#define DM1_COLORCOMPARE_MASK NPORT_DMODE1_CCMASK 107#define DM1_COLORCOMPARE NPORT_DMODE1_CCMASK 108#define DM1_COLORCOMPLT NPORT_DMODE1_CCLT 109#define DM1_COLORCOMPEQ NPORT_DMODE1_CCEQ 110#define DM1_COLORCOMPGT NPORT_DMODE1_CCGT 111 112#define DM1_RGBMODE NPORT_DMODE1_RGBMD 113#define DM1_ENDITHER NPORT_DMODE1_DENAB 114#define DM1_FASTCLEAR NPORT_DMODE1_FCLR 115#define DM1_ENBLEND NPORT_DMODE1_BENAB 116 117#define DM1_SF_SHIFT 19 118#define DM1_SF_MASK NPORT_DMODE1_SFMASK 119#define DM1_SF NPORT_DMODE1_SFMASK 120#define DM1_SF_ZERO NPORT_DMODE1_SF0 121#define DM1_SF_ONE NPORT_DMODE1_SF1 122#define DM1_SF_DC NPORT_DMODE1_SFDC 123#define DM1_SF_MDC NPORT_DMODE1_SFMDC 124#define DM1_SF_SA NPORT_DMODE1_SFSA 125#define DM1_SF_MSA NPORT_DMODE1_SFMSA 126 127#define DM1_DF_SHIFT 22 /* dfactor(2:0) */ 128#define DM1_DF_MASK NPORT_DMODE1_DFMASK 129#define DM1_DF NPORT_DMODE1_DFMASK 130#define DM1_DF_ZERO NPORT_DMODE1_DF0 131#define DM1_DF_ONE NPORT_DMODE1_DF1 132#define DM1_DF_SC NPORT_DMODE1_DFSC 133#define DM1_DF_MSC NPORT_DMODE1_DFMSC 134#define DM1_DF_SA NPORT_DMODE1_DFSA 135#define DM1_DF_MSA NPORT_DMODE1_DFMSA 136 137#define DM1_ENBACKBLEND NPORT_DMODE1_BBENAB 138#define DM1_ENPREFETCH NPORT_DMODE1_PFENAB 139#define DM1_BLENDALPHA NPORT_DMODE1_ABLEND 140 141#define DM1_LO_SHIFT 28 142#define DM1_LO NPORT_DMODE1_LOMASK 143#define DM1_LO_MASK NPORT_DMODE1_LOMASK 144#define DM1_LO_ZERO NPORT_DMODE1_LOZERO 145#define DM1_LO_AND NPORT_DMODE1_LOAND 146#define DM1_LO_ANDR NPORT_DMODE1_LOANDR 147#define DM1_LO_SRC NPORT_DMODE1_LOSRC 148#define DM1_LO_ANDI NPORT_DMODE1_LOANDI 149#define DM1_LO_DST NPORT_DMODE1_LODST 150#define DM1_LO_XOR NPORT_DMODE1_LOXOR 151#define DM1_LO_OR NPORT_DMODE1_LOOR 152#define DM1_LO_NOR NPORT_DMODE1_LONOR 153#define DM1_LO_XNOR NPORT_DMODE1_LOXNOR 154#define DM1_LO_NDST NPORT_DMODE1_LONDST 155#define DM1_LO_ORR NPORT_DMODE1_LOORR 156#define DM1_LO_NSRC NPORT_DMODE1_LONSRC 157#define DM1_LO_ORI NPORT_DMODE1_LOORI 158#define DM1_LO_NAND NPORT_DMODE1_LONAND 159#define DM1_LO_ONE NPORT_DMODE1_LOONE 160 161#define SMASK0 NPORT_CMODE_SM0 162#define SMASK1 NPORT_CMODE_SM1 163#define SMASK2 NPORT_CMODE_SM2 164#define SMASK3 NPORT_CMODE_SM3 165#define SMASK4 NPORT_CMODE_SM4 166#define ALL_SMASKS 0x1f 167 168#define CM_CIDMATCH_SHIFT 9 169#define CM_CIDMATCH_MASK NPORT_CMODE_CMSK 170 171#define REX3VERSION_MASK NPORT_STAT_VERS 172#define GFXBUSY NPORT_STAT_GBUSY 173#define BACKBUSY NPORT_STAT_BBUSY 174#define VRINT NPORT_STAT_VRINT 175#define VIDEOINT NPORT_STAT_VIDINT 176#define GFIFO_LEVEL_SHIFT 7 177#define GFIFO_LEVEL_MASK NPORT_STAT_GLMSK 178#define BFIFO_LEVEL_SHIFT 13 179#define BFIFO_LEVEL_MASK NPORT_STAT_BLMSK 180#define BFIFO_INT NPORT_STAT_BFIRQ 181#define GFIFO_INT NPORT_STAT_GFIRQ 182 183#define GIO32MODE NPORT_CFG_G32MD 184#define BUSWIDTH NPORT_CFG_BWIDTH 185#define EXTREGXCVR NPORT_CFG_ERCVR 186#define BFIFODEPTH_SHIFT 3 187#define BFIFODEPTH_MASK NPORT_CFG_BDMSK 188#define BFIFOABOVEINT NPORT_CFG_BFAINT 189#define GFIFODEPTH_SHIFT 8 190#define GFIFODEPTH_MASK NPORT_CFG_GDMSK 191#define GFIFOABOVEINT NPORT_CFG_GFAINT 192#define TIMEOUT_SHIFT 14 193#define TIMEOUT_MASK NPORT_CFG_TOMSK 194#define VREFRESH_SHIFT 17 195#define VREFRESH_MASK NPORT_CFG_VRMSK 196#define FB_TYPE NPORT_CFG_FBTYP 197 198#define DCB_DATAWIDTH_MASK (0x3) 199 200#define DCB_CRS_MASK (0x7 << DCB_CRS_SHIFT) 201#define DCB_ADDR_MASK (0xf << DCB_ADDR_SHIFT) 202#define DCB_CSWIDTH_MASK (0x1f << DCB_CSWIDTH_SHIFT) 203#define DCB_CSHOLD_MASK (0x1f << DCB_CSHOLD_SHIFT) 204#define DCB_CSSETUP_MASK (0x1f << DCB_CSSETUP_SHIFT) 205 206#define DCB_SWAPENDIAN (1 << 28) 207 208#define REX3WAIT(rex3) while ((rex3)->p1.set.status & GFXBUSY) 209#define BFIFOWAIT(rex3) while ((rex3)->p1.set.status & BACKBUSY) 210 211#define REX3_GIO_ADDR_0 0x1f0f0000 212#define REX3_GIO_ADDR_1 0x1f4f0000 213#define REX3_GIO_ADDR_2 0x1f8f0000 214#define REX3_GIO_ADDR_3 0x1fcf0000 215 216#define NG1_XSIZE 1280 217#define NG1_YSIZE 1024 218 219#endif 220