1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000 Toshiba Corporation 7 */ 8#ifndef __ASM_TX3927_H 9#define __ASM_TX3927_H 10 11#include <asm/jmr3927/txx927.h> 12 13#define TX3927_SDRAMC_REG 0xfffe8000 14#define TX3927_ROMC_REG 0xfffe9000 15#define TX3927_DMA_REG 0xfffeb000 16#define TX3927_IRC_REG 0xfffec000 17#define TX3927_PCIC_REG 0xfffed000 18#define TX3927_CCFG_REG 0xfffee000 19#define TX3927_NR_TMR 3 20#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100) 21#define TX3927_NR_SIO 2 22#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) 23#define TX3927_PIO_REG 0xfffef500 24 25#ifndef __ASSEMBLY__ 26 27struct tx3927_sdramc_reg { 28 volatile unsigned long cr[8]; 29 volatile unsigned long tr[3]; 30 volatile unsigned long cmd; 31 volatile unsigned long smrs[2]; 32}; 33 34struct tx3927_romc_reg { 35 volatile unsigned long cr[8]; 36}; 37 38struct tx3927_dma_reg { 39 struct tx3927_dma_ch_reg { 40 volatile unsigned long cha; 41 volatile unsigned long sar; 42 volatile unsigned long dar; 43 volatile unsigned long cntr; 44 volatile unsigned long sair; 45 volatile unsigned long dair; 46 volatile unsigned long ccr; 47 volatile unsigned long csr; 48 } ch[4]; 49 volatile unsigned long dbr[8]; 50 volatile unsigned long tdhr; 51 volatile unsigned long mcr; 52 volatile unsigned long unused0; 53}; 54 55struct tx3927_irc_reg { 56 volatile unsigned long cer; 57 volatile unsigned long cr[2]; 58 volatile unsigned long unused0; 59 volatile unsigned long ilr[8]; 60 volatile unsigned long unused1[4]; 61 volatile unsigned long imr; 62 volatile unsigned long unused2[7]; 63 volatile unsigned long scr; 64 volatile unsigned long unused3[7]; 65 volatile unsigned long ssr; 66 volatile unsigned long unused4[7]; 67 volatile unsigned long csr; 68}; 69 70#include <asm/byteorder.h> 71 72#ifdef __BIG_ENDIAN 73#define endian_def_s2(e1,e2) \ 74 volatile unsigned short e1,e2 75#define endian_def_sb2(e1,e2,e3) \ 76 volatile unsigned short e1;volatile unsigned char e2,e3 77#define endian_def_b2s(e1,e2,e3) \ 78 volatile unsigned char e1,e2;volatile unsigned short e3 79#define endian_def_b4(e1,e2,e3,e4) \ 80 volatile unsigned char e1,e2,e3,e4 81#else 82#define endian_def_s2(e1,e2) \ 83 volatile unsigned short e2,e1 84#define endian_def_sb2(e1,e2,e3) \ 85 volatile unsigned char e3,e2;volatile unsigned short e1 86#define endian_def_b2s(e1,e2,e3) \ 87 volatile unsigned short e3;volatile unsigned char e2,e1 88#define endian_def_b4(e1,e2,e3,e4) \ 89 volatile unsigned char e4,e3,e2,e1 90#endif 91 92struct tx3927_pcic_reg { 93 endian_def_s2(did, vid); 94 endian_def_s2(pcistat, pcicmd); 95 endian_def_b4(cc, scc, rpli, rid); 96 endian_def_b4(unused0, ht, mlt, cls); 97 volatile unsigned long ioba; /* +10 */ 98 volatile unsigned long mba; 99 volatile unsigned long unused1[5]; 100 endian_def_s2(svid, ssvid); 101 volatile unsigned long unused2; /* +30 */ 102 endian_def_sb2(unused3, unused4, capptr); 103 volatile unsigned long unused5; 104 endian_def_b4(ml, mg, ip, il); 105 volatile unsigned long unused6; /* +40 */ 106 volatile unsigned long istat; 107 volatile unsigned long iim; 108 volatile unsigned long rrt; 109 volatile unsigned long unused7[3]; /* +50 */ 110 volatile unsigned long ipbmma; 111 volatile unsigned long ipbioma; /* +60 */ 112 volatile unsigned long ilbmma; 113 volatile unsigned long ilbioma; 114 volatile unsigned long unused8[9]; 115 volatile unsigned long tc; /* +90 */ 116 volatile unsigned long tstat; 117 volatile unsigned long tim; 118 volatile unsigned long tccmd; 119 volatile unsigned long pcirrt; /* +a0 */ 120 volatile unsigned long pcirrt_cmd; 121 volatile unsigned long pcirrdt; 122 volatile unsigned long unused9[3]; 123 volatile unsigned long tlboap; 124 volatile unsigned long tlbiap; 125 volatile unsigned long tlbmma; /* +c0 */ 126 volatile unsigned long tlbioma; 127 volatile unsigned long sc_msg; 128 volatile unsigned long sc_be; 129 volatile unsigned long tbl; /* +d0 */ 130 volatile unsigned long unused10[3]; 131 volatile unsigned long pwmng; /* +e0 */ 132 volatile unsigned long pwmngs; 133 volatile unsigned long unused11[6]; 134 volatile unsigned long req_trace; /* +100 */ 135 volatile unsigned long pbapmc; 136 volatile unsigned long pbapms; 137 volatile unsigned long pbapmim; 138 volatile unsigned long bm; /* +110 */ 139 volatile unsigned long cpcibrs; 140 volatile unsigned long cpcibgs; 141 volatile unsigned long pbacs; 142 volatile unsigned long iobas; /* +120 */ 143 volatile unsigned long mbas; 144 volatile unsigned long lbc; 145 volatile unsigned long lbstat; 146 volatile unsigned long lbim; /* +130 */ 147 volatile unsigned long pcistatim; 148 volatile unsigned long ica; 149 volatile unsigned long icd; 150 volatile unsigned long iiadp; /* +140 */ 151 volatile unsigned long iscdp; 152 volatile unsigned long mmas; 153 volatile unsigned long iomas; 154 volatile unsigned long ipciaddr; /* +150 */ 155 volatile unsigned long ipcidata; 156 volatile unsigned long ipcibe; 157}; 158 159struct tx3927_ccfg_reg { 160 volatile unsigned long ccfg; 161 volatile unsigned long crir; 162 volatile unsigned long pcfg; 163 volatile unsigned long tear; 164 volatile unsigned long pdcr; 165}; 166 167#endif /* !__ASSEMBLY__ */ 168 169/* 170 * SDRAMC 171 */ 172 173/* 174 * ROMC 175 */ 176 177/* 178 * DMA 179 */ 180/* bits for MCR */ 181#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch)) 182#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch)) 183#define TX3927_DMA_MCR_RSFIF 0x00000080 184#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) 185#define TX3927_DMA_MCR_LE 0x00000004 186#define TX3927_DMA_MCR_RPRT 0x00000002 187#define TX3927_DMA_MCR_MSTEN 0x00000001 188 189/* bits for CCRn */ 190#define TX3927_DMA_CCR_DBINH 0x04000000 191#define TX3927_DMA_CCR_SBINH 0x02000000 192#define TX3927_DMA_CCR_CHRST 0x01000000 193#define TX3927_DMA_CCR_RVBYTE 0x00800000 194#define TX3927_DMA_CCR_ACKPOL 0x00400000 195#define TX3927_DMA_CCR_REQPL 0x00200000 196#define TX3927_DMA_CCR_EGREQ 0x00100000 197#define TX3927_DMA_CCR_CHDN 0x00080000 198#define TX3927_DMA_CCR_DNCTL 0x00060000 199#define TX3927_DMA_CCR_EXTRQ 0x00010000 200#define TX3927_DMA_CCR_INTRQD 0x0000e000 201#define TX3927_DMA_CCR_INTENE 0x00001000 202#define TX3927_DMA_CCR_INTENC 0x00000800 203#define TX3927_DMA_CCR_INTENT 0x00000400 204#define TX3927_DMA_CCR_CHNEN 0x00000200 205#define TX3927_DMA_CCR_XFACT 0x00000100 206#define TX3927_DMA_CCR_SNOP 0x00000080 207#define TX3927_DMA_CCR_DSTINC 0x00000040 208#define TX3927_DMA_CCR_SRCINC 0x00000020 209#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) 210#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2) 211#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4) 212#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5) 213#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6) 214#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7) 215#define TX3927_DMA_CCR_MEMIO 0x00000002 216#define TX3927_DMA_CCR_ONEAD 0x00000001 217 218/* bits for CSRn */ 219#define TX3927_DMA_CSR_CHNACT 0x00000100 220#define TX3927_DMA_CSR_ABCHC 0x00000080 221#define TX3927_DMA_CSR_NCHNC 0x00000040 222#define TX3927_DMA_CSR_NTRNFC 0x00000020 223#define TX3927_DMA_CSR_EXTDN 0x00000010 224#define TX3927_DMA_CSR_CFERR 0x00000008 225#define TX3927_DMA_CSR_CHERR 0x00000004 226#define TX3927_DMA_CSR_DESERR 0x00000002 227#define TX3927_DMA_CSR_SORERR 0x00000001 228 229/* 230 * IRC 231 */ 232#define TX3927_IR_MAX_LEVEL 7 233 234/* IRCER : Int. Control Enable */ 235#define TX3927_IRCER_ICE 0x00000001 236 237/* IRCR : Int. Control */ 238#define TX3927_IRCR_LOW 0x00000000 239#define TX3927_IRCR_HIGH 0x00000001 240#define TX3927_IRCR_DOWN 0x00000002 241#define TX3927_IRCR_UP 0x00000003 242 243/* IRSCR : Int. Status Control */ 244#define TX3927_IRSCR_EIClrE 0x00000100 245#define TX3927_IRSCR_EIClr_MASK 0x0000000f 246 247/* IRCSR : Int. Current Status */ 248#define TX3927_IRCSR_IF 0x00010000 249#define TX3927_IRCSR_ILV_MASK 0x00000700 250#define TX3927_IRCSR_IVL_MASK 0x0000001f 251 252#define TX3927_IR_INT0 0 253#define TX3927_IR_INT1 1 254#define TX3927_IR_INT2 2 255#define TX3927_IR_INT3 3 256#define TX3927_IR_INT4 4 257#define TX3927_IR_INT5 5 258#define TX3927_IR_SIO0 6 259#define TX3927_IR_SIO1 7 260#define TX3927_IR_SIO(ch) (6 + (ch)) 261#define TX3927_IR_DMA 8 262#define TX3927_IR_PIO 9 263#define TX3927_IR_PCI 10 264#define TX3927_IR_TMR0 13 265#define TX3927_IR_TMR1 14 266#define TX3927_IR_TMR2 15 267#define TX3927_NUM_IR 16 268 269/* 270 * PCIC 271 */ 272/* bits for PCICMD */ 273/* see PCI_COMMAND_XXX in linux/pci.h */ 274 275/* bits for PCISTAT */ 276/* see PCI_STATUS_XXX in linux/pci.h */ 277#define PCI_STATUS_NEW_CAP 0x0010 278 279/* bits for TC */ 280#define TX3927_PCIC_TC_OF16E 0x00000020 281#define TX3927_PCIC_TC_IF8E 0x00000010 282#define TX3927_PCIC_TC_OF8E 0x00000008 283 284/* bits for IOBA/MBA */ 285/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ 286 287/* bits for PBAPMC */ 288#define TX3927_PCIC_PBAPMC_RPBA 0x00000004 289#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002 290#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001 291 292/* bits for LBSTAT/LBIM */ 293#define TX3927_PCIC_LBIM_ALL 0x0000003e 294 295/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */ 296#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900 297 298/* bits for LBC */ 299#define TX3927_PCIC_LBC_IBSE 0x00004000 300#define TX3927_PCIC_LBC_TIBSE 0x00002000 301#define TX3927_PCIC_LBC_TMFBSE 0x00001000 302#define TX3927_PCIC_LBC_HRST 0x00000800 303#define TX3927_PCIC_LBC_SRST 0x00000400 304#define TX3927_PCIC_LBC_EPCAD 0x00000200 305#define TX3927_PCIC_LBC_MSDSE 0x00000100 306#define TX3927_PCIC_LBC_CRR 0x00000080 307#define TX3927_PCIC_LBC_ILMDE 0x00000040 308#define TX3927_PCIC_LBC_ILIDE 0x00000020 309 310#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) 311#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32) 312 313/* 314 * CCFG 315 */ 316/* CCFG : Chip Configuration */ 317#define TX3927_CCFG_TLBOFF 0x00020000 318#define TX3927_CCFG_BEOW 0x00010000 319#define TX3927_CCFG_WR 0x00008000 320#define TX3927_CCFG_TOE 0x00004000 321#define TX3927_CCFG_PCIXARB 0x00002000 322#define TX3927_CCFG_PCI3 0x00001000 323#define TX3927_CCFG_PSNP 0x00000800 324#define TX3927_CCFG_PPRI 0x00000400 325#define TX3927_CCFG_PLLM 0x00000030 326#define TX3927_CCFG_ENDIAN 0x00000004 327#define TX3927_CCFG_HALT 0x00000002 328#define TX3927_CCFG_ACEHOLD 0x00000001 329 330/* PCFG : Pin Configuration */ 331#define TX3927_PCFG_SYSCLKEN 0x08000000 332#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000 333#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch)) 334#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000 335#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch)) 336#define TX3927_PCFG_SELALL 0x0003ffff 337#define TX3927_PCFG_SELCS 0x00020000 338#define TX3927_PCFG_SELDSF 0x00010000 339#define TX3927_PCFG_SELSIOC_ALL 0x0000c000 340#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch)) 341#define TX3927_PCFG_SELSIO_ALL 0x00003000 342#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch)) 343#define TX3927_PCFG_SELTMR_ALL 0x00000e00 344#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch)) 345#define TX3927_PCFG_SELDONE 0x00000100 346#define TX3927_PCFG_INTDMA_ALL 0x000000f0 347#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch)) 348#define TX3927_PCFG_SELDMA_ALL 0x0000000f 349#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) 350 351#ifndef __ASSEMBLY__ 352 353#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) 354#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) 355#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) 356#define tx3927_ircptr ((struct tx3927_irc_reg *)TX3927_IRC_REG) 357#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) 358#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) 359#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) 360#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) 361#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG) 362 363#endif /* !__ASSEMBLY__ */ 364 365#endif /* __ASM_TX3927_H */ 366