1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle
7 */
8#ifndef __ASM_JAZZ_H
9#define __ASM_JAZZ_H
10
11/*
12 * The addresses below are virtual address. The mappings are
13 * created on startup via wired entries in the tlb. The Mips
14 * Magnum R3000 and R4000 machines are similar in many aspects,
15 * but many hardware register are accessible at 0xb9000000 in
16 * instead of 0xe0000000.
17 */
18
19#define JAZZ_LOCAL_IO_SPACE     0xe0000000
20
21/*
22 * Revision numbers in PICA_ASIC_REVISION
23 *
24 * 0xf0000000 - Rev1
25 * 0xf0000001 - Rev2
26 * 0xf0000002 - Rev3
27 */
28#define PICA_ASIC_REVISION      0xe0000008
29
30/*
31 * The segments of the seven segment LED are mapped
32 * to the control bits as follows:
33 *
34 *         (7)
35 *      ---------
36 *      |       |
37 *  (2) |       | (6)
38 *      |  (1)  |
39 *      ---------
40 *      |       |
41 *  (3) |       | (5)
42 *      |  (4)  |
43 *      --------- . (0)
44 */
45#define PICA_LED                0xe000f000
46
47/*
48 * Some characters for the LED control registers
49 * The original Mips machines seem to have a LED display
50 * with integrated decoder while the Acer machines can
51 * control each of the seven segments and the dot independently.
52 * It's only a toy, anyway...
53 */
54#define LED_DOT                 0x01
55#define LED_SPACE               0x00
56#define LED_0                   0xfc
57#define LED_1                   0x60
58#define LED_2                   0xda
59#define LED_3                   0xf2
60#define LED_4                   0x66
61#define LED_5                   0xb6
62#define LED_6                   0xbe
63#define LED_7                   0xe0
64#define LED_8                   0xfe
65#define LED_9                   0xf6
66#define LED_A                   0xee
67#define LED_b                   0x3e
68#define LED_C                   0x9c
69#define LED_d                   0x7a
70#define LED_E                   0x9e
71#define LED_F                   0x8e
72
73#ifndef __ASSEMBLY__
74
75extern __inline__ void pica_set_led(unsigned int bits)
76{
77	volatile unsigned int *led_register = (unsigned int *) PICA_LED;
78
79	*led_register = bits;
80}
81
82#endif /* !__ASSEMBLY__ */
83
84/*
85 * Base address of the Sonic Ethernet adapter in Jazz machines.
86 */
87#define JAZZ_ETHERNET_BASE  0xe0001000
88
89/*
90 * Base address of the 53C94 SCSI hostadapter in Jazz machines.
91 */
92#define JAZZ_SCSI_BASE		0xe0002000
93
94/*
95 * i8042 keyboard controller for JAZZ and PICA chipsets.
96 * This address is just a guess and seems to differ from
97 * other mips machines such as RC3xxx...
98 */
99#define JAZZ_KEYBOARD_ADDRESS   0xe0005000
100#define JAZZ_KEYBOARD_DATA      0xe0005000
101#define JAZZ_KEYBOARD_COMMAND   0xe0005001
102
103#ifndef __ASSEMBLY__
104
105typedef struct {
106	unsigned char data;
107	unsigned char command;
108} jazz_keyboard_hardware;
109
110typedef struct {
111	unsigned char pad0[3];
112	unsigned char data;
113	unsigned char pad1[3];
114	unsigned char command;
115} mips_keyboard_hardware;
116
117/*
118 * For now. Needs to be changed for RC3xxx support. See below.
119 */
120#define keyboard_hardware       jazz_keyboard_hardware
121
122#endif /* !__ASSEMBLY__ */
123
124/*
125 * i8042 keyboard controller for most other Mips machines.
126 */
127#define MIPS_KEYBOARD_ADDRESS   0xb9005000
128#define MIPS_KEYBOARD_DATA      0xb9005003
129#define MIPS_KEYBOARD_COMMAND   0xb9005007
130
131/*
132 * Serial and parallel ports (WD 16C552) on the Mips JAZZ
133 */
134#define JAZZ_SERIAL1_BASE       (unsigned int)0xe0006000
135#define JAZZ_SERIAL2_BASE       (unsigned int)0xe0007000
136#define JAZZ_PARALLEL_BASE      (unsigned int)0xe0008000
137
138/*
139 * Dummy Device Address. Used in jazzdma.c
140 */
141#define JAZZ_DUMMY_DEVICE       0xe000d000
142
143/*
144 * JAZZ timer registers and interrupt no.
145 * Note that the hardware timer interrupt is actually on
146 * cpu level 6, but to keep compatibility with PC stuff
147 * it is remapped to vector 0. See arch/mips/kernel/entry.S.
148 */
149#define JAZZ_TIMER_INTERVAL     0xe0000228
150#define JAZZ_TIMER_REGISTER     0xe0000230
151
152/*
153 * DRAM configuration register
154 */
155#ifndef __ASSEMBLY__
156#ifdef __MIPSEL__
157typedef struct {
158	unsigned int bank2 : 3;
159	unsigned int bank1 : 3;
160	unsigned int mem_bus_width : 1;
161	unsigned int reserved2 : 1;
162	unsigned int page_mode : 1;
163	unsigned int reserved1 : 23;
164} dram_configuration;
165#else /* defined (__MIPSEB__) */
166typedef struct {
167	unsigned int reserved1 : 23;
168	unsigned int page_mode : 1;
169	unsigned int reserved2 : 1;
170	unsigned int mem_bus_width : 1;
171	unsigned int bank1 : 3;
172	unsigned int bank2 : 3;
173} dram_configuration;
174#endif
175#endif /* !__ASSEMBLY__ */
176
177#define PICA_DRAM_CONFIG        0xe00fffe0
178
179/*
180 * JAZZ interrupt control registers
181 */
182#define JAZZ_IO_IRQ_SOURCE      0xe0010000
183#define JAZZ_IO_IRQ_ENABLE      0xe0010002
184
185/*
186 * JAZZ interrupt enable bits
187 */
188#define JAZZ_IE_PARALLEL            (1 << 0)
189#define JAZZ_IE_FLOPPY              (1 << 1)
190#define JAZZ_IE_SOUND               (1 << 2)
191#define JAZZ_IE_VIDEO               (1 << 3)
192#define JAZZ_IE_ETHERNET            (1 << 4)
193#define JAZZ_IE_SCSI                (1 << 5)
194#define JAZZ_IE_KEYBOARD            (1 << 6)
195#define JAZZ_IE_MOUSE               (1 << 7)
196#define JAZZ_IE_SERIAL1             (1 << 8)
197#define JAZZ_IE_SERIAL2             (1 << 9)
198
199/*
200 * JAZZ Interrupt Level definitions
201 *
202 * This is somewhat broken.  For reasons which nobody can remember anymore
203 * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
204 */
205#define JAZZ_PARALLEL_IRQ       16
206#define JAZZ_FLOPPY_IRQ          6 /* needs to be consistent with floppy driver! */
207#define JAZZ_SOUND_IRQ          18
208#define JAZZ_VIDEO_IRQ          19
209#define JAZZ_ETHERNET_IRQ       20
210#define JAZZ_SCSI_IRQ           21
211#define JAZZ_KEYBOARD_IRQ       22
212#define JAZZ_MOUSE_IRQ          23
213#define JAZZ_SERIAL1_IRQ        24
214#define JAZZ_SERIAL2_IRQ        25
215
216#define JAZZ_TIMER_IRQ          31
217
218
219/*
220 * JAZZ DMA Channels
221 * Note: Channels 4...7 are not used with respect to the Acer PICA-61
222 * chipset which does not provide these DMA channels.
223 */
224#define JAZZ_SCSI_DMA           0              /* SCSI */
225#define JAZZ_FLOPPY_DMA         1              /* FLOPPY */
226#define JAZZ_AUDIOL_DMA         2              /* AUDIO L */
227#define JAZZ_AUDIOR_DMA         3              /* AUDIO R */
228
229/*
230 * JAZZ R4030 MCT_ADR chip (DMA controller)
231 * Note: Virtual Addresses !
232 */
233#define JAZZ_R4030_CONFIG	0xE0000000	/* R4030 config register */
234#define JAZZ_R4030_REVISION     0xE0000008	/* same as PICA_ASIC_REVISION */
235#define JAZZ_R4030_INV_ADDR	0xE0000010	/* Invalid Address register */
236
237#define JAZZ_R4030_TRSTBL_BASE  0xE0000018	/* Translation Table Base */
238#define JAZZ_R4030_TRSTBL_LIM   0xE0000020	/* Translation Table Limit */
239#define JAZZ_R4030_TRSTBL_INV   0xE0000028	/* Translation Table Invalidate */
240
241#define JAZZ_R4030_CACHE_MTNC   0xE0000030	/* Cache Maintenance */
242#define JAZZ_R4030_R_FAIL_ADDR  0xE0000038	/* Remote Failed Address */
243#define JAZZ_R4030_M_FAIL_ADDR  0xE0000040	/* Memory Failed Address */
244
245#define JAZZ_R4030_CACHE_PTAG   0xE0000048	/* I/O Cache Physical Tag */
246#define JAZZ_R4030_CACHE_LTAG   0xE0000050	/* I/O Cache Logical Tag */
247#define JAZZ_R4030_CACHE_BMASK  0xE0000058	/* I/O Cache Byte Mask */
248#define JAZZ_R4030_CACHE_BWIN   0xE0000060	/* I/O Cache Buffer Window */
249
250/*
251 * Remote Speed Registers.
252 *
253 *  0: free,      1: Ethernet,  2: SCSI,      3: Floppy,
254 *  4: RTC,       5: Kb./Mouse  6: serial 1,  7: serial 2,
255 *  8: parallel,  9: NVRAM,    10: CPU,      11: PROM,
256 * 12: reserved, 13: free,     14: 7seg LED, 15: ???
257 */
258#define JAZZ_R4030_REM_SPEED	0xE0000070	/* 16 Remote Speed Registers */
259						/* 0xE0000070,78,80... 0xE00000E8 */
260#define JAZZ_R4030_IRQ_ENABLE   0xE00000E8	/* Internal Interrupt Enable */
261#define JAZZ_R4030_INVAL_ADDR   0xE0000010	/* Invalid address Register */
262#define JAZZ_R4030_IRQ_SOURCE   0xE0000200	/* Interrupt Source Register */
263#define JAZZ_R4030_I386_ERROR   0xE0000208	/* i386/EISA Bus Error */
264
265/*
266 * Virtual (E)ISA controller address
267 */
268#define JAZZ_EISA_IRQ_ACK	0xE0000238	/* EISA interrupt acknowledge */
269
270/*
271 * Access the R4030 DMA and I/O Controller
272 */
273#ifndef __ASSEMBLY__
274
275static inline void r4030_delay(void)
276{
277__asm__ __volatile__(
278	".set\tnoreorder\n\t"
279	"nop\n\t"
280	"nop\n\t"
281	"nop\n\t"
282	"nop\n\t"
283	".set\treorder");
284}
285
286static inline unsigned short r4030_read_reg16(unsigned addr)
287{
288	unsigned short ret = *((volatile unsigned short *)addr);
289	r4030_delay();
290	return ret;
291}
292
293static inline unsigned int r4030_read_reg32(unsigned addr)
294{
295	unsigned int ret = *((volatile unsigned int *)addr);
296	r4030_delay();
297	return ret;
298}
299
300static inline void r4030_write_reg16(unsigned addr, unsigned val)
301{
302	*((volatile unsigned short *)addr) = val;
303	r4030_delay();
304}
305
306static inline void r4030_write_reg32(unsigned addr, unsigned val)
307{
308	*((volatile unsigned int *)addr) = val;
309	r4030_delay();
310}
311
312#endif /* !__ASSEMBLY__ */
313
314#define JAZZ_FDC_BASE	0xe0003000
315#define JAZZ_RTC_BASE	0xe0004000
316#define JAZZ_PORT_BASE	0xe2000000
317
318#define JAZZ_EISA_BASE	0xe3000000
319
320#endif /* __ASM_JAZZ_H */
321