1/* $Id: pgtsrmmu.h,v 1.1.1.1 2008/10/15 03:29:17 james26_jang Exp $
2 * pgtsrmmu.h:  SRMMU page table defines and code.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_PGTSRMMU_H
8#define _SPARC_PGTSRMMU_H
9
10#include <asm/page.h>
11
12/* PMD_SHIFT determines the size of the area a second-level page table can map */
13#define SRMMU_PMD_SHIFT         18
14#define SRMMU_PMD_SIZE          (1UL << SRMMU_PMD_SHIFT)
15#define SRMMU_PMD_MASK          (~(SRMMU_PMD_SIZE-1))
16#define SRMMU_PMD_ALIGN(addr)   (((addr)+SRMMU_PMD_SIZE-1)&SRMMU_PMD_MASK)
17
18/* PGDIR_SHIFT determines what a third-level page table entry can map */
19#define SRMMU_PGDIR_SHIFT       24
20#define SRMMU_PGDIR_SIZE        (1UL << SRMMU_PGDIR_SHIFT)
21#define SRMMU_PGDIR_MASK        (~(SRMMU_PGDIR_SIZE-1))
22#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
23
24#define SRMMU_PTRS_PER_PTE      64
25#define SRMMU_PTRS_PER_PMD      64
26#define SRMMU_PTRS_PER_PGD      256
27
28#define SRMMU_PTE_TABLE_SIZE    0x100 /* 64 entries, 4 bytes a piece */
29#define SRMMU_PMD_TABLE_SIZE    0x100 /* 64 entries, 4 bytes a piece */
30#define SRMMU_PGD_TABLE_SIZE    0x400 /* 256 entries, 4 bytes a piece */
31
32/* Definition of the values in the ET field of PTD's and PTE's */
33#define SRMMU_ET_MASK         0x3
34#define SRMMU_ET_INVALID      0x0
35#define SRMMU_ET_PTD          0x1
36#define SRMMU_ET_PTE          0x2
37#define SRMMU_ET_REPTE        0x3 /* AIEEE, SuperSparc II reverse endian page! */
38
39/* Physical page extraction from PTP's and PTE's. */
40#define SRMMU_CTX_PMASK    0xfffffff0
41#define SRMMU_PTD_PMASK    0xfffffff0
42#define SRMMU_PTE_PMASK    0xffffff00
43
44/* The pte non-page bits.  Some notes:
45 * 1) cache, dirty, valid, and ref are frobbable
46 *    for both supervisor and user pages.
47 * 2) exec and write will only give the desired effect
48 *    on user pages
49 * 3) use priv and priv_readonly for changing the
50 *    characteristics of supervisor ptes
51 */
52#define SRMMU_CACHE        0x80
53#define SRMMU_DIRTY        0x40
54#define SRMMU_REF          0x20
55#define SRMMU_EXEC         0x08
56#define SRMMU_WRITE        0x04
57#define SRMMU_VALID        0x02 /* SRMMU_ET_PTE */
58#define SRMMU_PRIV         0x1c
59#define SRMMU_PRIV_RDONLY  0x18
60
61#define SRMMU_CHG_MASK    (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
62
63#define SRMMU_PAGE_NONE    __pgprot(SRMMU_VALID | SRMMU_CACHE | \
64				    SRMMU_PRIV | SRMMU_REF)
65#define SRMMU_PAGE_SHARED  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
66				    SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
67#define SRMMU_PAGE_COPY    __pgprot(SRMMU_VALID | SRMMU_CACHE | \
68				    SRMMU_EXEC | SRMMU_REF)
69#define SRMMU_PAGE_RDONLY  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
70				    SRMMU_EXEC | SRMMU_REF)
71#define SRMMU_PAGE_KERNEL  __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
72				    SRMMU_DIRTY | SRMMU_REF)
73
74/* SRMMU Register addresses in ASI 0x4.  These are valid for all
75 * current SRMMU implementations that exist.
76 */
77#define SRMMU_CTRL_REG           0x00000000
78#define SRMMU_CTXTBL_PTR         0x00000100
79#define SRMMU_CTX_REG            0x00000200
80#define SRMMU_FAULT_STATUS       0x00000300
81#define SRMMU_FAULT_ADDR         0x00000400
82
83#define WINDOW_FLUSH(tmp1, tmp2)					\
84	mov	0, tmp1;						\
8598:	ld	[%g6 + AOFF_task_thread + AOFF_thread_uwinmask], tmp2;	\
86	orcc	%g0, tmp2, %g0;						\
87	add	tmp1, 1, tmp1;						\
88	bne	98b;							\
89	 save	%sp, -64, %sp;						\
9099:	subcc	tmp1, 1, tmp1;						\
91	bne	99b;							\
92	 restore %g0, %g0, %g0;
93
94#ifndef __ASSEMBLY__
95
96/* Accessing the MMU control register. */
97extern __inline__ unsigned int srmmu_get_mmureg(void)
98{
99        unsigned int retval;
100	__asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
101			     "=r" (retval) :
102			     "i" (ASI_M_MMUREGS));
103	return retval;
104}
105
106extern __inline__ void srmmu_set_mmureg(unsigned long regval)
107{
108	__asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
109			     "r" (regval), "i" (ASI_M_MMUREGS) : "memory");
110
111}
112
113extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr)
114{
115	paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
116	__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
117			     "r" (paddr), "r" (SRMMU_CTXTBL_PTR),
118			     "i" (ASI_M_MMUREGS) :
119			     "memory");
120}
121
122extern __inline__ unsigned long srmmu_get_ctable_ptr(void)
123{
124	unsigned int retval;
125
126	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
127			     "=r" (retval) :
128			     "r" (SRMMU_CTXTBL_PTR),
129			     "i" (ASI_M_MMUREGS));
130	return (retval & SRMMU_CTX_PMASK) << 4;
131}
132
133extern __inline__ void srmmu_set_context(int context)
134{
135	__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
136			     "r" (context), "r" (SRMMU_CTX_REG),
137			     "i" (ASI_M_MMUREGS) : "memory");
138}
139
140extern __inline__ int srmmu_get_context(void)
141{
142	register int retval;
143	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
144			     "=r" (retval) :
145			     "r" (SRMMU_CTX_REG),
146			     "i" (ASI_M_MMUREGS));
147	return retval;
148}
149
150extern __inline__ unsigned int srmmu_get_fstatus(void)
151{
152	unsigned int retval;
153
154	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
155			     "=r" (retval) :
156			     "r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
157	return retval;
158}
159
160extern __inline__ unsigned int srmmu_get_faddr(void)
161{
162	unsigned int retval;
163
164	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
165			     "=r" (retval) :
166			     "r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
167	return retval;
168}
169
170/* This is guaranteed on all SRMMU's. */
171extern __inline__ void srmmu_flush_whole_tlb(void)
172{
173	__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
174			     "r" (0x400),        /* Flush entire TLB!! */
175			     "i" (ASI_M_FLUSH_PROBE) : "memory");
176
177}
178
179/* These flush types are not available on all chips... */
180extern __inline__ void srmmu_flush_tlb_ctx(void)
181{
182	__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
183			     "r" (0x300),        /* Flush TLB ctx.. */
184			     "i" (ASI_M_FLUSH_PROBE) : "memory");
185
186}
187
188extern __inline__ void srmmu_flush_tlb_region(unsigned long addr)
189{
190	addr &= SRMMU_PGDIR_MASK;
191	__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
192			     "r" (addr | 0x200), /* Flush TLB region.. */
193			     "i" (ASI_M_FLUSH_PROBE) : "memory");
194
195}
196
197
198extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
199{
200	addr &= SRMMU_PMD_MASK;
201	__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
202			     "r" (addr | 0x100), /* Flush TLB segment.. */
203			     "i" (ASI_M_FLUSH_PROBE) : "memory");
204
205}
206
207extern __inline__ void srmmu_flush_tlb_page(unsigned long page)
208{
209	page &= PAGE_MASK;
210	__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
211			     "r" (page),        /* Flush TLB page.. */
212			     "i" (ASI_M_FLUSH_PROBE) : "memory");
213
214}
215
216extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr)
217{
218	unsigned long retval;
219
220	vaddr &= PAGE_MASK;
221	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
222			     "=r" (retval) :
223			     "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
224
225	return retval;
226}
227
228extern __inline__ int
229srmmu_get_pte (unsigned long addr)
230{
231	register unsigned long entry;
232
233	__asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
234				"=r" (entry):
235				"r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
236	return entry;
237}
238
239extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
240extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
241
242#endif /* !(__ASSEMBLY__) */
243
244#endif /* !(_SPARC_PGTSRMMU_H) */
245