1#ifndef __ASM_SH_PTRACE_H
2#define __ASM_SH_PTRACE_H
3
4#include <asm/processor.h>
5
6/*
7 * Copyright (C) 1999, 2000  Niibe Yutaka
8 *
9 */
10
11/*
12 * GCC defines register number like this:
13 * -----------------------------
14 *	 0 - 15 are integer registers
15 *	17 - 22 are control/special registers
16 *	24 - 39 fp registers
17 *	40 - 47 xd registers
18 *	48 -    fpscr register
19 * -----------------------------
20 *
21 * We follows above, except:
22 *	16 --- program counter (PC)
23 *	22 --- syscall #
24 *	23 --- floating point communication register
25 */
26#define REG_REG0	 0
27#define REG_REG15	15
28
29#define REG_PC		16
30
31#define REG_PR		17
32#define REG_SR		18
33#define REG_GBR      	19
34#define REG_MACH	20
35#define REG_MACL	21
36
37#define REG_SYSCALL	22
38
39#define REG_FPUL	23
40
41#define REG_FPREG0	24
42#define REG_FPREG15	39
43#define REG_XDREG0	40
44#define REG_XDREG14	47
45#define REG_FPSCR	48
46
47#define PTRACE_SETOPTIONS         21
48
49/* options set using PTRACE_SETOPTIONS */
50#define PTRACE_O_TRACESYSGOOD     0x00000001
51
52/*
53 * This struct defines the way the registers are stored on the
54 * kernel stack during a system call or other kernel entry.
55 */
56struct pt_regs {
57	unsigned long regs[16];
58	unsigned long pc;
59	unsigned long pr;
60	unsigned long sr;
61	unsigned long gbr;
62	unsigned long mach;
63	unsigned long macl;
64	long syscall_nr;
65};
66
67#ifdef __KERNEL__
68#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
69#define instruction_pointer(regs) ((regs)->pc)
70extern void show_regs(struct pt_regs *);
71
72/* User Break Controller */
73
74#if defined(CONFIG_CPU_SUBTYPE_SH7709)
75#define UBC_TYPE_SH7729	(cpu_data->type == CPU_SH7729)
76#else
77#define UBC_TYPE_SH7729	0
78#endif
79
80#if defined(__sh3__)
81#define UBC_BARA                0xffffffb0
82#define UBC_BAMRA               0xffffffb4
83#define UBC_BBRA                0xffffffb8
84#define UBC_BASRA               0xffffffe4
85#define UBC_BARB                0xffffffa0
86#define UBC_BAMRB               0xffffffa4
87#define UBC_BBRB                0xffffffa8
88#define UBC_BASRB               0xffffffe8
89#define UBC_BDRB                0xffffff90
90#define UBC_BDMRB               0xffffff94
91#define UBC_BRCR                0xffffff98
92#elif defined(__SH4__)
93#define UBC_BARA		0xff200000
94#define UBC_BAMRA		0xff200004
95#define UBC_BBRA		0xff200008
96#define UBC_BASRA		0xff000014
97#define UBC_BARB		0xff20000c
98#define UBC_BAMRB		0xff200010
99#define UBC_BBRB		0xff200014
100#define UBC_BASRB		0xff000018
101#define UBC_BDRB		0xff200018
102#define UBC_BDMRB		0xff20001c
103#define UBC_BRCR		0xff200020
104#endif
105
106#define BAMR_ASID		(1 << 2)
107#define BAMR_NONE		0
108#define BAMR_10			0x1
109#define BAMR_12			0x2
110#define BAMR_ALL		0x3
111#define BAMR_16			0x8
112#define BAMR_20			0x9
113
114#define BBR_INST		(1 << 4)
115#define BBR_DATA		(2 << 4)
116#define BBR_READ		(1 << 2)
117#define BBR_WRITE		(2 << 2)
118#define BBR_BYTE		0x1
119#define BBR_HALF		0x2
120#define BBR_LONG		0x3
121#define BBR_QUAD		(1 << 6)	/* SH7750 */
122#define BBR_CPU			(1 << 6)	/* SH7709A,SH7729 */
123#define BBR_DMA			(2 << 6)	/* SH7709A,SH7729 */
124
125#define BRCR_CMFA		(1 << 15)
126#define BRCR_CMFB		(1 << 14)
127#define BRCR_PCTE		(1 << 11)
128#define BRCR_PCBA		(1 << 10)	/* 1: after execution */
129#define BRCR_DBEB		(1 << 7)
130#define BRCR_PCBB		(1 << 6)
131#define BRCR_SEQ		(1 << 3)
132#define BRCR_UBDE		(1 << 0)
133#endif
134
135#endif /* __ASM_SH_PTRACE_H */
136