1#ifndef __ASM_PPC64_PROCESSOR_H 2#define __ASM_PPC64_PROCESSOR_H 3 4/* 5 * Copyright (C) 2001 PPC 64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13#include <linux/stringify.h> 14#ifndef __ASSEMBLY__ 15#include <asm/atomic.h> 16#include <asm/ppcdebug.h> 17#include <asm/a.out.h> 18#endif 19#include <asm/ptrace.h> 20#include <asm/types.h> 21#include <asm/delay.h> 22 23/* 24 * Default implementation of macro that returns current 25 * instruction pointer ("program counter"). 26 */ 27#define current_text_addr() ({ __label__ _l; _l: &&_l;}) 28 29/* Machine State Register (MSR) Fields */ 30#define MSR_SF_LG 63 /* Enable 64 bit mode */ 31#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ 32#define MSR_HV_LG 60 /* Hypervisor state */ 33#define MSR_VEC_LG 25 /* Enable AltiVec */ 34#define MSR_POW_LG 18 /* Enable Power Management */ 35#define MSR_WE_LG 18 /* Wait State Enable */ 36#define MSR_TGPR_LG 17 /* TLB Update registers in use */ 37#define MSR_CE_LG 17 /* Critical Interrupt Enable */ 38#define MSR_ILE_LG 16 /* Interrupt Little Endian */ 39#define MSR_EE_LG 15 /* External Interrupt Enable */ 40#define MSR_PR_LG 14 /* Problem State / Privilege Level */ 41#define MSR_FP_LG 13 /* Floating Point enable */ 42#define MSR_ME_LG 12 /* Machine Check Enable */ 43#define MSR_FE0_LG 11 /* Floating Exception mode 0 */ 44#define MSR_SE_LG 10 /* Single Step */ 45#define MSR_BE_LG 9 /* Branch Trace */ 46#define MSR_DE_LG 9 /* Debug Exception Enable */ 47#define MSR_FE1_LG 8 /* Floating Exception mode 1 */ 48#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */ 49#define MSR_IR_LG 5 /* Instruction Relocate */ 50#define MSR_DR_LG 4 /* Data Relocate */ 51#define MSR_PE_LG 3 /* Protection Enable */ 52#define MSR_PX_LG 2 /* Protection Exclusive Mode */ 53#define MSR_RI_LG 1 /* Recoverable Exception */ 54#define MSR_LE_LG 0 /* Little Endian */ 55 56#ifdef __ASSEMBLY__ 57#define __MASK(X) (1<<(X)) 58#else 59#define __MASK(X) (1UL<<(X)) 60#endif 61 62#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ 63#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ 64#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ 65#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ 66#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ 67#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ 68#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ 69#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */ 70#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */ 71#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */ 72#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */ 73#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */ 74#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */ 75#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */ 76#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */ 77#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */ 78#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */ 79#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */ 80#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */ 81#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */ 82#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */ 83#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */ 84#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */ 85#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ 86#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ 87 88#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF 89#define MSR_KERNEL MSR_ | MSR_SF | MSR_HV 90 91#define MSR_USER32 MSR_ | MSR_PR | MSR_EE 92#define MSR_USER64 MSR_USER32 | MSR_SF 93 94/* Floating Point Status and Control Register (FPSCR) Fields */ 95 96#define FPSCR_FX 0x80000000 /* FPU exception summary */ 97#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ 98#define FPSCR_VX 0x20000000 /* Invalid operation summary */ 99#define FPSCR_OX 0x10000000 /* Overflow exception summary */ 100#define FPSCR_UX 0x08000000 /* Underflow exception summary */ 101#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */ 102#define FPSCR_XX 0x02000000 /* Inexact exception summary */ 103#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ 104#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ 105#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ 106#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ 107#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ 108#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ 109#define FPSCR_FR 0x00040000 /* Fraction rounded */ 110#define FPSCR_FI 0x00020000 /* Fraction inexact */ 111#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ 112#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ 113#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ 114#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ 115#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ 116#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ 117#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ 118#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ 119#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ 120#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ 121#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ 122#define FPSCR_RN 0x00000003 /* FPU rounding control */ 123 124/* Special Purpose Registers (SPRNs)*/ 125 126#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ 127#define SPRN_CTR 0x009 /* Count Register */ 128#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 129#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ 130#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ 131#define SPRN_DAR 0x013 /* Data Address Register */ 132#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ 133#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ 134#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ 135#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ 136#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ 137#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ 138#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ 139#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ 140#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ 141#define DBCR_EDM 0x80000000 142#define DBCR_IDM 0x40000000 143#define DBCR_RST(x) (((x) & 0x3) << 28) 144#define DBCR_RST_NONE 0 145#define DBCR_RST_CORE 1 146#define DBCR_RST_CHIP 2 147#define DBCR_RST_SYSTEM 3 148#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ 149#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ 150#define DBCR_EDE 0x02000000 /* Exception Debug Event */ 151#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ 152#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ 153#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ 154#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ 155#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ 156#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ 157#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ 158#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ 159#define DAC_BYTE 0 160#define DAC_HALF 1 161#define DAC_WORD 2 162#define DAC_QUAD 3 163#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ 164#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ 165#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ 166#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ 167#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ 168#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ 169#define DBCR_SIA 0x00000008 /* Second IAC Enable */ 170#define DBCR_SDA 0x00000004 /* Second DAC Enable */ 171#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ 172#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ 173#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ 174#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ 175#define SPRN_DBSR 0x3F0 /* Debug Status Register */ 176#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ 177#define DCCR_NOCACHE 0 /* Noncacheable */ 178#define DCCR_CACHE 1 /* Cacheable */ 179#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ 180#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ 181#define DCWR_COPY 0 /* Copy-back */ 182#define DCWR_WRITE 1 /* Write-through */ 183#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ 184#define SPRN_DEC 0x016 /* Decrement Register */ 185#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ 186#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 187#define SPRN_EAR 0x11A /* External Address Register */ 188#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ 189#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ 190#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ 191#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ 192#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ 193#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ 194#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ 195#define ESR_PTR 0x02000000 /* Program Exception - Trap */ 196#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ 197#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ 198#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ 199#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ 200#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ 201#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ 202#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ 203#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ 204#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ 205#define HID0_SBCLK (1<<27) 206#define HID0_EICE (1<<26) 207#define HID0_ECLK (1<<25) 208#define HID0_PAR (1<<24) 209#define HID0_DOZE (1<<23) 210#define HID0_NAP (1<<22) 211#define HID0_SLEEP (1<<21) 212#define HID0_DPM (1<<20) 213#define HID0_ICE (1<<15) /* Instruction Cache Enable */ 214#define HID0_DCE (1<<14) /* Data Cache Enable */ 215#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ 216#define HID0_DLOCK (1<<12) /* Data Cache Lock */ 217#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ 218#define HID0_DCI (1<<10) /* Data Cache Invalidate */ 219#define HID0_SPD (1<<9) /* Speculative disable */ 220#define HID0_SGE (1<<7) /* Store Gathering Enable */ 221#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ 222#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ 223#define HID0_ABE (1<<3) /* Address Broadcast Enable */ 224#define HID0_BHTE (1<<2) /* Branch History Table Enable */ 225#define HID0_BTCD (1<<1) /* Branch target cache disable */ 226#define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */ 227#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 228#define SPRN_NIADORM 0x3F3 /* Hardware Implementation Register 2 */ 229#define SPRN_TSC 0x3FD /* Thread switch control */ 230#define SPRN_TST 0x3FC /* Thread switch timeout */ 231#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ 232#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ 233#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ 234#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ 235#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ 236#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ 237#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ 238#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ 239#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ 240#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ 241#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ 242#define ICCR_NOCACHE 0 /* Noncacheable */ 243#define ICCR_CACHE 1 /* Cacheable */ 244#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ 245#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ 246#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ 247#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ 248#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ 249#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ 250#define SPRN_LR 0x008 /* Link Register */ 251#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ 252#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ 253#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ 254#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ 255#define SPRN_PID 0x3B1 /* Process ID */ 256#define SPRN_PIR 0x3FF /* Processor Identification Register */ 257#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 258#define SPRN_PVR 0x11F /* Processor Version Register */ 259#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 260#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 261#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ 262#define SGR_NORMAL 0 263#define SGR_GUARDED 1 264#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 265#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 266#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ 267#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 268#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 269#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 270#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ 271#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ 272#define SPRN_TBHI 0x3DC /* Time Base High */ 273#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ 274#define SPRN_TBLO 0x3DD /* Time Base Low */ 275#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ 276#define SPRN_TBRL 0x10D /* Time Base Read Lower Register */ 277#define SPRN_TBRU 0x10C /* Time Base Read Upper Register */ 278#define SPRN_TBWL 0x11D /* Time Base Write Lower Register */ 279#define SPRN_TBWU 0x11C /* Time Base Write Upper Register */ 280#define SPRN_TCR 0x3DA /* Timer Control Register */ 281#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ 282#define WP_2_17 0 /* 2^17 clocks */ 283#define WP_2_21 1 /* 2^21 clocks */ 284#define WP_2_25 2 /* 2^25 clocks */ 285#define WP_2_29 3 /* 2^29 clocks */ 286#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ 287#define WRC_NONE 0 /* No reset will occur */ 288#define WRC_CORE 1 /* Core reset will occur */ 289#define WRC_CHIP 2 /* Chip reset will occur */ 290#define WRC_SYSTEM 3 /* System reset will occur */ 291#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ 292#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 293#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ 294#define FP_2_9 0 /* 2^9 clocks */ 295#define FP_2_13 1 /* 2^13 clocks */ 296#define FP_2_17 2 /* 2^17 clocks */ 297#define FP_2_21 3 /* 2^21 clocks */ 298#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 299#define TCR_ARE 0x00400000 /* Auto Reload Enable */ 300#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ 301#define THRM1_TIN (1<<0) 302#define THRM1_TIV (1<<1) 303#define THRM1_THRES (0x7f<<2) 304#define THRM1_TID (1<<29) 305#define THRM1_TIE (1<<30) 306#define THRM1_V (1<<31) 307#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ 308#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ 309#define THRM3_E (1<<31) 310#define SPRN_TSR 0x3D8 /* Timer Status Register */ 311#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 312#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ 313#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ 314#define WRS_NONE 0 /* No WDT reset occurred */ 315#define WRS_CORE 1 /* WDT forced core reset */ 316#define WRS_CHIP 2 /* WDT forced chip reset */ 317#define WRS_SYSTEM 3 /* WDT forced system reset */ 318#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 319#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 320#define SPRN_XER 0x001 /* Fixed Point Exception Register */ 321#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ 322 323/* Short-hand versions for a number of the above SPRNs */ 324 325#define CTR SPRN_CTR /* Counter Register */ 326#define DAR SPRN_DAR /* Data Address Register */ 327#define DABR SPRN_DABR /* Data Address Breakpoint Register */ 328#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ 329#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ 330#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ 331#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ 332#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ 333#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ 334#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ 335#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ 336#define DCMP SPRN_DCMP /* Data TLB Compare Register */ 337#define DEC SPRN_DEC /* Decrement Register */ 338#define DMISS SPRN_DMISS /* Data TLB Miss Register */ 339#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ 340#define EAR SPRN_EAR /* External Address Register */ 341#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ 342#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ 343#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ 344#define MSRDORM SPRN_MSRDORM /* MSR Dormant Register */ 345#define NIADORM SPRN_NIADORM /* NIA Dormant Register */ 346#define TSC SPRN_TSC /* Thread switch control */ 347#define TST SPRN_TST /* Thread switch timeout */ 348#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ 349#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ 350#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ 351#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ 352#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ 353#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ 354#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ 355#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ 356#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ 357#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ 358#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ 359#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ 360#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ 361#define LR SPRN_LR 362#define PVR SPRN_PVR /* Processor Version */ 363#define PIR SPRN_PIR /* Processor ID */ 364#define RPA SPRN_RPA /* Required Physical Address Register */ 365#define SDR1 SPRN_SDR1 /* MMU hash base register */ 366#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ 367#define SPR1 SPRN_SPRG1 368#define SPR2 SPRN_SPRG2 369#define SPR3 SPRN_SPRG3 370#define SPRG0 SPRN_SPRG0 371#define SPRG1 SPRN_SPRG1 372#define SPRG2 SPRN_SPRG2 373#define SPRG3 SPRN_SPRG3 374#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ 375#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ 376#define TBRL SPRN_TBRL /* Time Base Read Lower Register */ 377#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ 378#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ 379#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ 380#define ICTC 1019 381#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ 382#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ 383#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ 384#define XER SPRN_XER 385#define PMC1 0x313 386#define PMC2 0x314 387#define PMC3 0x315 388#define PMC4 0x316 389#define PMC5 0x317 390#define PMC6 0x318 391#define PMC7 0x319 392#define PMC8 0x31a 393#define MMCR0 0x31b 394#define MMCR1 0x31e 395#define MMCRA 0x312 396#define SIAR 0x30c 397#define SDAR 0x30d 398 399/* Device Control Registers */ 400 401#define DCRN_BEAR 0x090 /* Bus Error Address Register */ 402#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ 403#define BESR_DSES 0x80000000 /* Data-Side Error Status */ 404#define BESR_DMES 0x40000000 /* DMA Error Status */ 405#define BESR_RWS 0x20000000 /* Read/Write Status */ 406#define BESR_ETMASK 0x1C000000 /* Error Type */ 407#define ET_PROT 0 408#define ET_PARITY 1 409#define ET_NCFG 2 410#define ET_BUSERR 4 411#define ET_BUSTO 6 412#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ 413#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ 414#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ 415#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ 416#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ 417#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ 418#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ 419#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ 420#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ 421#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ 422#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ 423#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ 424#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ 425#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ 426#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ 427#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ 428#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ 429#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ 430#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ 431#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ 432#define DCRN_DMASR 0x0E0 /* DMA Status Register */ 433#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ 434#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ 435#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ 436#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ 437#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ 438#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ 439#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ 440#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ 441#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ 442#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ 443#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ 444#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ 445#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ 446#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ 447#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ 448#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ 449#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ 450#define IOCR_E0TE 0x80000000 451#define IOCR_E0LP 0x40000000 452#define IOCR_E1TE 0x20000000 453#define IOCR_E1LP 0x10000000 454#define IOCR_E2TE 0x08000000 455#define IOCR_E2LP 0x04000000 456#define IOCR_E3TE 0x02000000 457#define IOCR_E3LP 0x01000000 458#define IOCR_E4TE 0x00800000 459#define IOCR_E4LP 0x00400000 460#define IOCR_EDT 0x00080000 461#define IOCR_SOR 0x00040000 462#define IOCR_EDO 0x00008000 463#define IOCR_2XC 0x00004000 464#define IOCR_ATC 0x00002000 465#define IOCR_SPD 0x00001000 466#define IOCR_BEM 0x00000800 467#define IOCR_PTD 0x00000400 468#define IOCR_ARE 0x00000080 469#define IOCR_DRC 0x00000020 470#define IOCR_RDM(x) (((x) & 0x3) << 3) 471#define IOCR_TCS 0x00000004 472#define IOCR_SCS 0x00000002 473#define IOCR_SPC 0x00000001 474 475 476/* Processor Version Register */ 477 478/* Processor Version Register (PVR) field extraction */ 479 480#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ 481#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ 482 483/* Processor Version Numbers */ 484#define PV_NORTHSTAR 0x0033 485#define PV_PULSAR 0x0034 486#define PV_POWER4 0x0035 487#define PV_ICESTAR 0x0036 488#define PV_SSTAR 0x0037 489#define PV_POWER4p 0x0038 490#define PV_630 0x0040 491#define PV_630p 0x0041 492 493/* Platforms supported by PPC64 */ 494#define PLATFORM_PSERIES 0x0100 495#define PLATFORM_PSERIES_LPAR 0x0101 496#define PLATFORM_ISERIES_LPAR 0x0201 497 498/* 499 * List of interrupt controllers. 500 */ 501#define IC_INVALID 0 502#define IC_OPEN_PIC 1 503#define IC_PPC_XIC 2 504 505#define XGLUE(a,b) a##b 506#define GLUE(a,b) XGLUE(a,b) 507 508/* 509 * Begining of traceback info work for asm functions. 510 */ 511#define TB_ASM 0x000C000000000000 512#define TB_GLOBALLINK 0x0000800000000000 513#define TB_IS_EPROL 0x0000400000000000 514#define TB_HAS_TBOFF 0x0000200000000000 515#define TB_INT_PROC 0x0000100000000000 516#define TB_HAS_CTL 0x0000080000000000 517#define TB_TOCLESS 0x0000040000000000 518#define TB_FP_PRESENT 0x0000020000000000 519#define TB_LOG_ABORT 0x0000010000000000 520#define TB_INT_HNDL 0x0000008000000000 521#define TB_NAME_PRESENT 0x0000004000000000 522#define TB_SAVES_CR 0x0000000200000000 523#define TB_SAVES_LR 0x0000000100000000 524#define TB_STORES_BC 0x0000000080000000 525#define TB_PARMINFO 0x000000000000FFFF 526#define TB_DEFAULT TB_ASM | TB_HAS_TBOFF | TB_NAME_PRESENT 527 528#ifdef __ASSEMBLY__ 529 530#define _GLOBAL(name) \ 531 .section ".text"; \ 532 .align 2 ; \ 533 .globl name; \ 534 .globl GLUE(.,name); \ 535 .section ".opd","aw"; \ 536name: \ 537 .quad GLUE(.,name); \ 538 .quad .TOC.@tocbase; \ 539 .quad 0; \ 540 .previous; \ 541 .type GLUE(.,name),@function; \ 542GLUE(.,name): 543 544#define _STATIC(name) \ 545 .section ".text"; \ 546 .align 2 ; \ 547 .section ".opd","aw"; \ 548name: \ 549 .quad GLUE(.,name); \ 550 .quad .TOC.@tocbase; \ 551 .quad 0; \ 552 .previous; \ 553 .type GLUE(.,name),@function; \ 554GLUE(.,name): 555 556#define _TRACEBACK(NAME) \ 557GLUE(.LT,NAME): ;\ 558 .long 0 ;\ 559 .llong TB_DEFAULT ;\ 560 .long GLUE(.LT,NAME)-GLUE(.,NAME) ;\ 561 .short GLUE(GLUE(.LT,NAME),_procname_end)-GLUE(GLUE(.LT,NAME),_procname_start) ;\ 562GLUE(GLUE(.LT,NAME),_procname_start): ;\ 563 .ascii __stringify(NAME) ;\ 564GLUE(GLUE(.LT,NAME),_procname_end): 565 566#endif /* __ASSEMBLY__ */ 567 568 569/* Macros for setting and retrieving special purpose registers */ 570 571#define mfmsr() ({unsigned long rval; \ 572 asm volatile("mfmsr %0" : "=r" (rval)); rval;}) 573 574#define mtmsrd(v) asm volatile("mtmsrd %0" : : "r" (v)) 575 576#define mfspr(rn) ({unsigned long rval; \ 577 asm volatile("mfspr %0," __stringify(rn) \ 578 : "=r" (rval)); rval;}) 579#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)) 580 581#define mftb() ({unsigned long rval; \ 582 asm volatile("mftb %0" : "=r" (rval)); rval;}) 583 584/* iSeries CTRL register (for runlatch) */ 585 586#define CTRLT 0x098 587#define CTRLF 0x088 588#define RUNLATCH 0x0001 589#define RUN_FLAG 0x0002 590 591/* Macros for adjusting thread priority (hardware multi-threading) */ 592#define HMT_low() asm volatile("or 1,1,1") 593#define HMT_medium() asm volatile("or 2,2,2") 594#define HMT_high() asm volatile("or 3,3,3") 595 596/* Size of an exception stack frame contained in the paca. */ 597#define EXC_FRAME_SIZE 64 598 599#define mfasr() ({unsigned long rval; \ 600 asm volatile("mfasr %0" : "=r" (rval)); rval;}) 601 602#ifndef __ASSEMBLY__ 603extern int have_of; 604 605struct task_struct; 606void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp); 607void release_thread(struct task_struct *); 608 609/* 610 * Create a new kernel thread. 611 */ 612extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); 613 614/* 615 * Bus types 616 */ 617#define EISA_bus 0 618#define EISA_bus__is_a_macro /* for versions in ksyms.c */ 619#define MCA_bus 0 620#define MCA_bus__is_a_macro /* for versions in ksyms.c */ 621 622/* Lazy FPU handling on uni-processor */ 623extern struct task_struct *last_task_used_math; 624 625 626#ifdef __KERNEL__ 627/* 64-bit user address space is 41-bits (2TBs user VM) */ 628#define TASK_SIZE_USER64 (0x0000020000000000UL) 629 630/* 631 * 32-bit user address space is 4GB - 1 page 632 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT 633 */ 634#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE)) 635 636#define TASK_SIZE ((current->thread.flags & PPC_FLAG_32BIT) ? \ 637 TASK_SIZE_USER32 : TASK_SIZE_USER64) 638#endif /* __KERNEL__ */ 639 640 641/* This decides where the kernel will search for a free chunk of vm 642 * space during mmap's. 643 */ 644#define TASK_UNMAPPED_BASE_USER32 (STACK_TOP_USER32 / 4) 645#define TASK_UNMAPPED_BASE_USER64 (STACK_TOP_USER64 / 4) 646 647#define TASK_UNMAPPED_BASE (((current->thread.flags & PPC_FLAG_32BIT)||(ppcdebugset(PPCDBG_BINFMT_32ADDR))) ? \ 648 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) 649 650typedef struct { 651 unsigned long seg; 652} mm_segment_t; 653 654struct thread_struct { 655 unsigned long ksp; /* Kernel stack pointer */ 656 struct pt_regs *regs; /* Pointer to saved register state */ 657 mm_segment_t fs; /* for get_fs() validation */ 658 void *pgdir; /* root of page-table tree */ 659 signed long last_syscall; 660 unsigned long flags; 661 double fpr[32]; /* Complete floating point set */ 662 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ 663 unsigned long fpscr; /* Floating point status */ 664}; 665 666#define PPC_FLAG_32BIT 0x01 667#define PPC_FLAG_RUN_LIGHT RUN_FLAG 668 669#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) 670 671#define INIT_THREAD { \ 672 INIT_SP, /* ksp */ \ 673 (struct pt_regs *)INIT_SP - 1, /* regs */ \ 674 KERNEL_DS, /*fs*/ \ 675 swapper_pg_dir, /* pgdir */ \ 676 0, /* last_syscall */ \ 677 PPC_FLAG_RUN_LIGHT, /* flags */ \ 678 {0}, 0, 0 \ 679} 680 681/* 682 * Note: the vm_start and vm_end fields here should *not* 683 * be in kernel space. (Could vm_end == vm_start perhaps?) 684 */ 685#define IOREMAP_MMAP { &ioremap_mm, 0, 0x1000, NULL, \ 686 PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ 687 1, NULL, NULL } 688 689extern struct mm_struct ioremap_mm; 690 691/* 692 * Return saved PC of a blocked thread. For now, this is the "user" PC 693 */ 694static inline unsigned long thread_saved_pc(struct thread_struct *t) 695{ 696 return (t->regs) ? t->regs->nip : 0; 697} 698 699#define copy_segments(tsk, mm) do { } while (0) 700#define release_segments(mm) do { } while (0) 701#define forget_segments() do { } while (0) 702 703unsigned long get_wchan(struct task_struct *p); 704 705#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 706#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) 707 708/* 709 * NOTE! The task struct and the stack go together 710 */ 711#define THREAD_SIZE (4*PAGE_SIZE) 712struct task_struct * alloc_task_struct(void); 713 714void free_task_struct(struct task_struct *); 715#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count) 716 717#define init_task (init_task_union.task) 718#define init_stack (init_task_union.stack) 719 720#define cpu_relax() udelay(1) 721 722/* 723 * Prefetch macros. 724 */ 725#define ARCH_HAS_PREFETCH 726#define ARCH_HAS_PREFETCHW 727#define ARCH_HAS_SPINLOCK_PREFETCH 728 729static inline void prefetch(const void *x) 730{ 731 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x)); 732} 733 734static inline void prefetchw(const void *x) 735{ 736 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x)); 737} 738 739#define spin_lock_prefetch(x) prefetchw(x) 740 741#define cpu_has_largepage() (__is_processor(PV_POWER4) || \ 742 __is_processor(PV_POWER4p)) 743 744#define cpu_has_slb() (__is_processor(PV_POWER4) || \ 745 __is_processor(PV_POWER4p)) 746 747#define cpu_has_tlbiel() (__is_processor(PV_POWER4) || \ 748 __is_processor(PV_POWER4p)) 749 750#define cpu_has_noexecute() (__is_processor(PV_POWER4) || \ 751 __is_processor(PV_POWER4p)) 752 753#endif /* ASSEMBLY */ 754 755#endif /* __ASM_PPC64_PROCESSOR_H */ 756