1/* 2 * linux/include/asm/dma.h: Defines for using and allocating dma channels. 3 * Written by Hennus Bergman, 1992. 4 * High DMA channel support & info by Hannu Savolainen 5 * and John Boyd, Nov. 1992. 6 * Changes for ppc sound by Christoph Nadig 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14#ifndef _ASM_DMA_H 15#define _ASM_DMA_H 16 17#include <linux/config.h> 18#include <asm/io.h> 19#include <linux/spinlock.h> 20#include <asm/system.h> 21 22#ifndef MAX_DMA_CHANNELS 23#define MAX_DMA_CHANNELS 8 24#endif 25 26/* The maximum address that we can perform a DMA transfer to on this platform */ 27/* Doesn't really apply... */ 28#define MAX_DMA_ADDRESS (~0UL) 29 30#define dma_outb outb 31#define dma_inb inb 32 33/* 34 * NOTES about DMA transfers: 35 * 36 * controller 1: channels 0-3, byte operations, ports 00-1F 37 * controller 2: channels 4-7, word operations, ports C0-DF 38 * 39 * - ALL registers are 8 bits only, regardless of transfer size 40 * - channel 4 is not used - cascades 1 into 2. 41 * - channels 0-3 are byte - addresses/counts are for physical bytes 42 * - channels 5-7 are word - addresses/counts are for physical words 43 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries 44 * - transfer count loaded to registers is 1 less than actual count 45 * - controller 2 offsets are all even (2x offsets for controller 1) 46 * - page registers for 5-7 don't use data bit 0, represent 128K pages 47 * - page registers for 0-3 use bit 0, represent 64K pages 48 * 49 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory. 50 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing. 51 * Note that addresses loaded into registers must be _physical_ addresses, 52 * not logical addresses (which may differ if paging is active). 53 * 54 * Address mapping for channels 0-3: 55 * 56 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) 57 * | ... | | ... | | ... | 58 * | ... | | ... | | ... | 59 * | ... | | ... | | ... | 60 * P7 ... P0 A7 ... A0 A7 ... A0 61 * | Page | Addr MSB | Addr LSB | (DMA registers) 62 * 63 * Address mapping for channels 5-7: 64 * 65 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) 66 * | ... | \ \ ... \ \ \ ... \ \ 67 * | ... | \ \ ... \ \ \ ... \ (not used) 68 * | ... | \ \ ... \ \ \ ... \ 69 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 70 * | Page | Addr MSB | Addr LSB | (DMA registers) 71 * 72 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses 73 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at 74 * the hardware level, so odd-byte transfers aren't possible). 75 * 76 * Transfer count (_not # bytes_) is limited to 64K, represented as actual 77 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, 78 * and up to 128K bytes may be transferred on channels 5-7 in one operation. 79 * 80 */ 81 82/* 8237 DMA controllers */ 83#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 84#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ 85 86/* DMA controller registers */ 87#define DMA1_CMD_REG 0x08 /* command register (w) */ 88#define DMA1_STAT_REG 0x08 /* status register (r) */ 89#define DMA1_REQ_REG 0x09 /* request register (w) */ 90#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ 91#define DMA1_MODE_REG 0x0B /* mode register (w) */ 92#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ 93#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ 94#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ 95#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ 96#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ 97 98#define DMA2_CMD_REG 0xD0 /* command register (w) */ 99#define DMA2_STAT_REG 0xD0 /* status register (r) */ 100#define DMA2_REQ_REG 0xD2 /* request register (w) */ 101#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ 102#define DMA2_MODE_REG 0xD6 /* mode register (w) */ 103#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ 104#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ 105#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ 106#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ 107#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ 108 109#define DMA_ADDR_0 0x00 /* DMA address registers */ 110#define DMA_ADDR_1 0x02 111#define DMA_ADDR_2 0x04 112#define DMA_ADDR_3 0x06 113#define DMA_ADDR_4 0xC0 114#define DMA_ADDR_5 0xC4 115#define DMA_ADDR_6 0xC8 116#define DMA_ADDR_7 0xCC 117 118#define DMA_CNT_0 0x01 /* DMA count registers */ 119#define DMA_CNT_1 0x03 120#define DMA_CNT_2 0x05 121#define DMA_CNT_3 0x07 122#define DMA_CNT_4 0xC2 123#define DMA_CNT_5 0xC6 124#define DMA_CNT_6 0xCA 125#define DMA_CNT_7 0xCE 126 127#define DMA_LO_PAGE_0 0x87 /* DMA page registers */ 128#define DMA_LO_PAGE_1 0x83 129#define DMA_LO_PAGE_2 0x81 130#define DMA_LO_PAGE_3 0x82 131#define DMA_LO_PAGE_5 0x8B 132#define DMA_LO_PAGE_6 0x89 133#define DMA_LO_PAGE_7 0x8A 134 135#define DMA_HI_PAGE_0 0x487 /* DMA page registers */ 136#define DMA_HI_PAGE_1 0x483 137#define DMA_HI_PAGE_2 0x481 138#define DMA_HI_PAGE_3 0x482 139#define DMA_HI_PAGE_5 0x48B 140#define DMA_HI_PAGE_6 0x489 141#define DMA_HI_PAGE_7 0x48A 142 143#define DMA1_EXT_REG 0x40B 144#define DMA2_EXT_REG 0x4D6 145 146#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ 147#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ 148#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ 149 150#define DMA_AUTOINIT 0x10 151 152extern spinlock_t dma_spin_lock; 153 154static __inline__ unsigned long claim_dma_lock(void) 155{ 156 unsigned long flags; 157 spin_lock_irqsave(&dma_spin_lock, flags); 158 return flags; 159} 160 161static __inline__ void release_dma_lock(unsigned long flags) 162{ 163 spin_unlock_irqrestore(&dma_spin_lock, flags); 164} 165 166/* enable/disable a specific DMA channel */ 167static __inline__ void enable_dma(unsigned int dmanr) 168{ 169 unsigned char ucDmaCmd=0x00; 170 171 if (dmanr != 4) 172 { 173 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */ 174 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */ 175 } 176 if (dmanr<=3) 177 { 178 dma_outb(dmanr, DMA1_MASK_REG); 179 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */ 180 } else 181 { 182 dma_outb(dmanr & 3, DMA2_MASK_REG); 183 } 184} 185 186static __inline__ void disable_dma(unsigned int dmanr) 187{ 188 if (dmanr<=3) 189 dma_outb(dmanr | 4, DMA1_MASK_REG); 190 else 191 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); 192} 193 194/* Clear the 'DMA Pointer Flip Flop'. 195 * Write 0 for LSB/MSB, 1 for MSB/LSB access. 196 * Use this once to initialize the FF to a known state. 197 * After that, keep track of it. :-) 198 * --- In order to do that, the DMA routines below should --- 199 * --- only be used while interrupts are disabled! --- 200 */ 201static __inline__ void clear_dma_ff(unsigned int dmanr) 202{ 203 if (dmanr<=3) 204 dma_outb(0, DMA1_CLEAR_FF_REG); 205 else 206 dma_outb(0, DMA2_CLEAR_FF_REG); 207} 208 209/* set mode (above) for a specific DMA channel */ 210static __inline__ void set_dma_mode(unsigned int dmanr, char mode) 211{ 212 if (dmanr<=3) 213 dma_outb(mode | dmanr, DMA1_MODE_REG); 214 else 215 dma_outb(mode | (dmanr&3), DMA2_MODE_REG); 216} 217 218/* Set only the page register bits of the transfer address. 219 * This is used for successive transfers when we know the contents of 220 * the lower 16 bits of the DMA current address register, but a 64k boundary 221 * may have been crossed. 222 */ 223static __inline__ void set_dma_page(unsigned int dmanr, int pagenr) 224{ 225 switch(dmanr) { 226 case 0: 227 dma_outb(pagenr, DMA_LO_PAGE_0); 228 dma_outb(pagenr>>8, DMA_HI_PAGE_0); 229 break; 230 case 1: 231 dma_outb(pagenr, DMA_LO_PAGE_1); 232 dma_outb(pagenr>>8, DMA_HI_PAGE_1); 233 break; 234 case 2: 235 dma_outb(pagenr, DMA_LO_PAGE_2); 236 dma_outb(pagenr>>8, DMA_HI_PAGE_2); 237 break; 238 case 3: 239 dma_outb(pagenr, DMA_LO_PAGE_3); 240 dma_outb(pagenr>>8, DMA_HI_PAGE_3); 241 break; 242 case 5: 243 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5); 244 dma_outb(pagenr>>8, DMA_HI_PAGE_5); 245 break; 246 case 6: 247 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6); 248 dma_outb(pagenr>>8, DMA_HI_PAGE_6); 249 break; 250 case 7: 251 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7); 252 dma_outb(pagenr>>8, DMA_HI_PAGE_7); 253 break; 254 } 255} 256 257 258/* Set transfer address & page bits for specific DMA channel. 259 * Assumes dma flipflop is clear. 260 */ 261static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys) 262{ 263 if (dmanr <= 3) { 264 dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); 265 dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); 266 } else { 267 dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 268 dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 269 } 270 set_dma_page(dmanr, phys>>16); 271} 272 273 274/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for 275 * a specific DMA channel. 276 * You must ensure the parameters are valid. 277 * NOTE: from a manual: "the number of transfers is one more 278 * than the initial word count"! This is taken into account. 279 * Assumes dma flip-flop is clear. 280 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. 281 */ 282static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) 283{ 284 count--; 285 if (dmanr <= 3) { 286 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); 287 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); 288 } else { 289 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 290 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 291 } 292} 293 294 295/* Get DMA residue count. After a DMA transfer, this 296 * should return zero. Reading this while a DMA transfer is 297 * still in progress will return unpredictable results. 298 * If called before the channel has been used, it may return 1. 299 * Otherwise, it returns the number of _bytes_ left to transfer. 300 * 301 * Assumes DMA flip-flop is clear. 302 */ 303static __inline__ int get_dma_residue(unsigned int dmanr) 304{ 305 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE 306 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; 307 308 /* using short to get 16-bit wrap around */ 309 unsigned short count; 310 311 count = 1 + dma_inb(io_port); 312 count += dma_inb(io_port) << 8; 313 314 return (dmanr <= 3)? count : (count<<1); 315} 316 317/* These are in kernel/dma.c: */ 318extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ 319extern void free_dma(unsigned int dmanr); /* release it again */ 320 321#ifdef CONFIG_PCI 322extern int isa_dma_bridge_buggy; 323#else 324#define isa_dma_bridge_buggy (0) 325#endif 326#endif /* _ASM_DMA_H */ 327