1/*
2 * BK Id: %F% %I% %G% %U% %#%
3 */
4#ifdef __KERNEL__
5#ifndef _ASM_PCI_BRIDGE_H
6#define _ASM_PCI_BRIDGE_H
7
8#include <linux/ioport.h>
9#include <linux/pci.h>
10
11struct device_node;
12struct pci_controller;
13
14/*
15 * pci_io_base returns the memory address at which you can access
16 * the I/O space for PCI bus number `bus' (or NULL on error).
17 */
18extern void *pci_bus_io_base(unsigned int bus);
19extern unsigned long pci_bus_io_base_phys(unsigned int bus);
20extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
21
22/* Allocate a new PCI host bridge structure */
23extern struct pci_controller* pcibios_alloc_controller(void);
24
25/* Helper function for setting up resources */
26extern void pci_init_resource(struct resource *res, unsigned long start,
27			      unsigned long end, int flags, char *name);
28
29/*
30 * PCI <-> OF matching functions
31 */
32extern int pci_device_from_OF_node(struct device_node *node,
33				   u8* bus, u8* devfn);
34extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
35extern void pci_create_OF_bus_map(void);
36
37/* Get the PCI host controller for a bus */
38extern struct pci_controller* pci_bus_to_hose(int bus);
39
40/* Get the PCI host controller for an OF device */
41extern struct pci_controller*
42pci_find_hose_for_OF_device(struct device_node* node);
43
44/* Fill up host controller resources from the OF node */
45extern void
46pci_process_bridge_OF_ranges(struct pci_controller *hose,
47			   struct device_node *dev, int primary);
48
49/*
50 * Structure of a PCI controller (host bridge)
51 */
52struct pci_controller {
53	int index;			/* used for pci_controller_num */
54	struct pci_controller *next;
55        struct pci_bus *bus;
56	void *arch_data;
57
58	int first_busno;
59	int last_busno;
60
61	void *io_base_virt;
62	unsigned long io_base_phys;
63
64	/* Some machines (PReP) have a non 1:1 mapping of
65	 * the PCI memory space in the CPU bus space
66	 */
67	unsigned long pci_mem_offset;
68
69	struct pci_ops *ops;
70	volatile unsigned int *cfg_addr;
71	volatile unsigned char *cfg_data;
72
73	/* Currently, we limit ourselves to 1 IO range and 3 mem
74	 * ranges since the common pci_bus structure can't handle more
75	 */
76	struct resource	io_resource;
77	struct resource mem_resources[3];
78	int mem_resource_count;
79
80	/* Host bridge I/O and Memory space
81	 * Used for BAR placement algorithms
82	 */
83	struct resource io_space;
84	struct resource mem_space;
85};
86
87/* These are used for config access before all the PCI probing
88   has been done. */
89int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, int where, u8 *val);
90int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn, int where, u16 *val);
91int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn, int where, u32 *val);
92int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn, int where, u8 val);
93int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, int where, u16 val);
94int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, int where, u32 val);
95
96extern void setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr,
97		u32 cfg_data);
98extern void setup_grackle(struct pci_controller *hose);
99
100extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
101
102/*
103 *   The following code swizzles for exactly one bridge.  The routine
104 *   common_swizzle below handles multiple bridges.  But there are a
105 *   some boards that don't follow the PCI spec's suggestion so we
106 *   break this piece out separately.
107 */
108static inline unsigned char bridge_swizzle(unsigned char pin,
109		unsigned char idsel)
110{
111	return (((pin-1) + idsel) % 4) + 1;
112}
113
114/*
115 * The following macro is used to lookup irqs in a standard table
116 * format for those PPC systems that do not already have PCI
117 * interrupts properly routed.
118 */
119#define PCI_IRQ_TABLE_LOOKUP						    \
120({ long _ctl_ = -1; 							    \
121   if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot)    \
122     _ctl_ = pci_irq_table[idsel - min_idsel][pin-1];			    \
123   _ctl_; })
124
125/*
126 * Scan the buses below a given PCI host bridge and assign suitable
127 * resources to all devices found.
128 */
129extern int pciauto_bus_scan(struct pci_controller *, int);
130
131#endif
132#endif /* __KERNEL__ */
133